1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_RTC_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_RTC_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for RTC peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */ 13 #define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */ 14 #define REG_RTC_GP0 (0x40002440) /**< \brief (RTC) General Purpose 0 */ 15 #define REG_RTC_GP1 (0x40002444) /**< \brief (RTC) General Purpose 1 */ 16 #define REG_RTC_GP2 (0x40002448) /**< \brief (RTC) General Purpose 2 */ 17 #define REG_RTC_GP3 (0x4000244C) /**< \brief (RTC) General Purpose 3 */ 18 #define REG_RTC_TAMPCTRL (0x40002460) /**< \brief (RTC) Tamper Control */ 19 #define REG_RTC_TAMPID (0x40002468) /**< \brief (RTC) Tamper ID */ 20 #define REG_RTC_BKUP0 (0x40002480) /**< \brief (RTC) Backup 0 */ 21 #define REG_RTC_BKUP1 (0x40002484) /**< \brief (RTC) Backup 1 */ 22 #define REG_RTC_BKUP2 (0x40002488) /**< \brief (RTC) Backup 2 */ 23 #define REG_RTC_BKUP3 (0x4000248C) /**< \brief (RTC) Backup 3 */ 24 #define REG_RTC_BKUP4 (0x40002490) /**< \brief (RTC) Backup 4 */ 25 #define REG_RTC_BKUP5 (0x40002494) /**< \brief (RTC) Backup 5 */ 26 #define REG_RTC_BKUP6 (0x40002498) /**< \brief (RTC) Backup 6 */ 27 #define REG_RTC_BKUP7 (0x4000249C) /**< \brief (RTC) Backup 7 */ 28 #define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */ 29 #define REG_RTC_MODE0_CTRLB (0x40002402) /**< \brief (RTC) MODE0 Control B */ 30 #define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */ 31 #define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ 32 #define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */ 33 #define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ 34 #define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */ 35 #define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */ 36 #define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */ 37 #define REG_RTC_MODE0_COMP1 (0x40002424) /**< \brief (RTC) MODE0 Compare 1 Value */ 38 #define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE0 Timestamp */ 39 #define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */ 40 #define REG_RTC_MODE1_CTRLB (0x40002402) /**< \brief (RTC) MODE1 Control B */ 41 #define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */ 42 #define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ 43 #define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */ 44 #define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ 45 #define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */ 46 #define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */ 47 #define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */ 48 #define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */ 49 #define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */ 50 #define REG_RTC_MODE1_COMP2 (0x40002424) /**< \brief (RTC) MODE1 Compare 2 Value */ 51 #define REG_RTC_MODE1_COMP3 (0x40002426) /**< \brief (RTC) MODE1 Compare 3 Value */ 52 #define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE1 Timestamp */ 53 #define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */ 54 #define REG_RTC_MODE2_CTRLB (0x40002402) /**< \brief (RTC) MODE2 Control B */ 55 #define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */ 56 #define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ 57 #define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */ 58 #define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ 59 #define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */ 60 #define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */ 61 #define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE2 Timestamp */ 62 #define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ 63 #define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ 64 #define REG_RTC_MODE2_ALARM_ALARM1 (0x40002428) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */ 65 #define REG_RTC_MODE2_ALARM_MASK1 (0x4000242C) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */ 66 #else 67 #define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */ 68 #define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */ 69 #define REG_RTC_GP0 (*(RwReg *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */ 70 #define REG_RTC_GP1 (*(RwReg *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */ 71 #define REG_RTC_GP2 (*(RwReg *)0x40002448UL) /**< \brief (RTC) General Purpose 2 */ 72 #define REG_RTC_GP3 (*(RwReg *)0x4000244CUL) /**< \brief (RTC) General Purpose 3 */ 73 #define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460UL) /**< \brief (RTC) Tamper Control */ 74 #define REG_RTC_TAMPID (*(RwReg *)0x40002468UL) /**< \brief (RTC) Tamper ID */ 75 #define REG_RTC_BKUP0 (*(RwReg *)0x40002480UL) /**< \brief (RTC) Backup 0 */ 76 #define REG_RTC_BKUP1 (*(RwReg *)0x40002484UL) /**< \brief (RTC) Backup 1 */ 77 #define REG_RTC_BKUP2 (*(RwReg *)0x40002488UL) /**< \brief (RTC) Backup 2 */ 78 #define REG_RTC_BKUP3 (*(RwReg *)0x4000248CUL) /**< \brief (RTC) Backup 3 */ 79 #define REG_RTC_BKUP4 (*(RwReg *)0x40002490UL) /**< \brief (RTC) Backup 4 */ 80 #define REG_RTC_BKUP5 (*(RwReg *)0x40002494UL) /**< \brief (RTC) Backup 5 */ 81 #define REG_RTC_BKUP6 (*(RwReg *)0x40002498UL) /**< \brief (RTC) Backup 6 */ 82 #define REG_RTC_BKUP7 (*(RwReg *)0x4000249CUL) /**< \brief (RTC) Backup 7 */ 83 #define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */ 84 #define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */ 85 #define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */ 86 #define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ 87 #define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */ 88 #define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ 89 #define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */ 90 #define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */ 91 #define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */ 92 #define REG_RTC_MODE0_COMP1 (*(RwReg *)0x40002424UL) /**< \brief (RTC) MODE0 Compare 1 Value */ 93 #define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */ 94 #define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */ 95 #define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */ 96 #define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */ 97 #define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ 98 #define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */ 99 #define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ 100 #define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */ 101 #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */ 102 #define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */ 103 #define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */ 104 #define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */ 105 #define REG_RTC_MODE1_COMP2 (*(RwReg16*)0x40002424UL) /**< \brief (RTC) MODE1 Compare 2 Value */ 106 #define REG_RTC_MODE1_COMP3 (*(RwReg16*)0x40002426UL) /**< \brief (RTC) MODE1 Compare 3 Value */ 107 #define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */ 108 #define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */ 109 #define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */ 110 #define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */ 111 #define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ 112 #define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */ 113 #define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ 114 #define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */ 115 #define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */ 116 #define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */ 117 #define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ 118 #define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ 119 #define REG_RTC_MODE2_ALARM_ALARM1 (*(RwReg *)0x40002428UL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */ 120 #define REG_RTC_MODE2_ALARM_MASK1 (*(RwReg8 *)0x4000242CUL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */ 121 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 122 123 #endif /* _MICROCHIP_PIC32CXSG_RTC_INSTANCE_FIXUP_H_ */ 124
