1 /** 2 * \file 3 * 4 * \brief Instance description for RTC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_RTC_INSTANCE_ 30 #define _SAML21_RTC_INSTANCE_ 31 32 /* ========== Register definition for RTC peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_RTC_DBGCTRL (0x4000200E) /**< \brief (RTC) Debug Control */ 35 #define REG_RTC_FREQCORR (0x40002014) /**< \brief (RTC) Frequency Correction */ 36 #define REG_RTC_GP0 (0x40002040) /**< \brief (RTC) General Purpose 0 */ 37 #define REG_RTC_GP1 (0x40002044) /**< \brief (RTC) General Purpose 1 */ 38 #define REG_RTC_GP2 (0x40002048) /**< \brief (RTC) General Purpose 2 */ 39 #define REG_RTC_GP3 (0x4000204C) /**< \brief (RTC) General Purpose 3 */ 40 #define REG_RTC_MODE0_CTRLA (0x40002000) /**< \brief (RTC) MODE0 Control A */ 41 #define REG_RTC_MODE0_EVCTRL (0x40002004) /**< \brief (RTC) MODE0 Event Control */ 42 #define REG_RTC_MODE0_INTENCLR (0x40002008) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ 43 #define REG_RTC_MODE0_INTENSET (0x4000200A) /**< \brief (RTC) MODE0 Interrupt Enable Set */ 44 #define REG_RTC_MODE0_INTFLAG (0x4000200C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ 45 #define REG_RTC_MODE0_SYNCBUSY (0x40002010) /**< \brief (RTC) MODE0 Synchronization Busy Status */ 46 #define REG_RTC_MODE0_COUNT (0x40002018) /**< \brief (RTC) MODE0 Counter Value */ 47 #define REG_RTC_MODE0_COMP0 (0x40002020) /**< \brief (RTC) MODE0 Compare 0 Value */ 48 #define REG_RTC_MODE1_CTRLA (0x40002000) /**< \brief (RTC) MODE1 Control A */ 49 #define REG_RTC_MODE1_EVCTRL (0x40002004) /**< \brief (RTC) MODE1 Event Control */ 50 #define REG_RTC_MODE1_INTENCLR (0x40002008) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ 51 #define REG_RTC_MODE1_INTENSET (0x4000200A) /**< \brief (RTC) MODE1 Interrupt Enable Set */ 52 #define REG_RTC_MODE1_INTFLAG (0x4000200C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ 53 #define REG_RTC_MODE1_SYNCBUSY (0x40002010) /**< \brief (RTC) MODE1 Synchronization Busy Status */ 54 #define REG_RTC_MODE1_COUNT (0x40002018) /**< \brief (RTC) MODE1 Counter Value */ 55 #define REG_RTC_MODE1_PER (0x4000201C) /**< \brief (RTC) MODE1 Counter Period */ 56 #define REG_RTC_MODE1_COMP0 (0x40002020) /**< \brief (RTC) MODE1 Compare 0 Value */ 57 #define REG_RTC_MODE1_COMP1 (0x40002022) /**< \brief (RTC) MODE1 Compare 1 Value */ 58 #define REG_RTC_MODE2_CTRLA (0x40002000) /**< \brief (RTC) MODE2 Control A */ 59 #define REG_RTC_MODE2_EVCTRL (0x40002004) /**< \brief (RTC) MODE2 Event Control */ 60 #define REG_RTC_MODE2_INTENCLR (0x40002008) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ 61 #define REG_RTC_MODE2_INTENSET (0x4000200A) /**< \brief (RTC) MODE2 Interrupt Enable Set */ 62 #define REG_RTC_MODE2_INTFLAG (0x4000200C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ 63 #define REG_RTC_MODE2_SYNCBUSY (0x40002010) /**< \brief (RTC) MODE2 Synchronization Busy Status */ 64 #define REG_RTC_MODE2_CLOCK (0x40002018) /**< \brief (RTC) MODE2 Clock Value */ 65 #define REG_RTC_MODE2_ALARM_ALARM0 (0x40002020) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ 66 #define REG_RTC_MODE2_ALARM_MASK0 (0x40002024) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ 67 #else 68 #define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000200EUL) /**< \brief (RTC) Debug Control */ 69 #define REG_RTC_FREQCORR (*(RwReg8 *)0x40002014UL) /**< \brief (RTC) Frequency Correction */ 70 #define REG_RTC_GP0 (*(RwReg *)0x40002040UL) /**< \brief (RTC) General Purpose 0 */ 71 #define REG_RTC_GP1 (*(RwReg *)0x40002044UL) /**< \brief (RTC) General Purpose 1 */ 72 #define REG_RTC_GP2 (*(RwReg *)0x40002048UL) /**< \brief (RTC) General Purpose 2 */ 73 #define REG_RTC_GP3 (*(RwReg *)0x4000204CUL) /**< \brief (RTC) General Purpose 3 */ 74 #define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002000UL) /**< \brief (RTC) MODE0 Control A */ 75 #define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002004UL) /**< \brief (RTC) MODE0 Event Control */ 76 #define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002008UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ 77 #define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000200AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */ 78 #define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000200CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ 79 #define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002010UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */ 80 #define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002018UL) /**< \brief (RTC) MODE0 Counter Value */ 81 #define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002020UL) /**< \brief (RTC) MODE0 Compare 0 Value */ 82 #define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002000UL) /**< \brief (RTC) MODE1 Control A */ 83 #define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002004UL) /**< \brief (RTC) MODE1 Event Control */ 84 #define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002008UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ 85 #define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000200AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */ 86 #define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000200CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ 87 #define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002010UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */ 88 #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002018UL) /**< \brief (RTC) MODE1 Counter Value */ 89 #define REG_RTC_MODE1_PER (*(RwReg16*)0x4000201CUL) /**< \brief (RTC) MODE1 Counter Period */ 90 #define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002020UL) /**< \brief (RTC) MODE1 Compare 0 Value */ 91 #define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002022UL) /**< \brief (RTC) MODE1 Compare 1 Value */ 92 #define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002000UL) /**< \brief (RTC) MODE2 Control A */ 93 #define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002004UL) /**< \brief (RTC) MODE2 Event Control */ 94 #define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002008UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ 95 #define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000200AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */ 96 #define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000200CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ 97 #define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002010UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */ 98 #define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002018UL) /**< \brief (RTC) MODE2 Clock Value */ 99 #define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002020UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ 100 #define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x40002024UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ 101 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 102 103 /* ========== Instance parameters for RTC peripheral ========== */ 104 #define RTC_ALARM_NUM 1 // Number of Alarms 105 #define RTC_COMP16_NUM 2 // Number of 16-bit Comparators 106 #define RTC_COMP32_NUM 1 // Number of 32-bit Comparators 107 #define RTC_GPR_NUM 4 // Number of General-Purpose Registers 108 #define RTC_PER_NUM 8 // Number of Periodic Intervals 109 110 #endif /* _SAML21_RTC_INSTANCE_ */ 111
