1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_RAMECC_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_RAMECC_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for RAMECC peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_RAMECC_INTENCLR (0x41020000) /**< \brief (RAMECC) Interrupt Enable Clear */ 13 #define REG_RAMECC_INTENSET (0x41020001) /**< \brief (RAMECC) Interrupt Enable Set */ 14 #define REG_RAMECC_INTFLAG (0x41020002) /**< \brief (RAMECC) Interrupt Flag */ 15 #define REG_RAMECC_STATUS (0x41020003) /**< \brief (RAMECC) Status */ 16 #define REG_RAMECC_ERRADDR (0x41020004) /**< \brief (RAMECC) Error Address */ 17 #define REG_RAMECC_DBGCTRL (0x4102000F) /**< \brief (RAMECC) Debug Control */ 18 #else 19 #define REG_RAMECC_INTENCLR (*(RwReg8 *)0x41020000UL) /**< \brief (RAMECC) Interrupt Enable Clear */ 20 #define REG_RAMECC_INTENSET (*(RwReg8 *)0x41020001UL) /**< \brief (RAMECC) Interrupt Enable Set */ 21 #define REG_RAMECC_INTFLAG (*(RwReg8 *)0x41020002UL) /**< \brief (RAMECC) Interrupt Flag */ 22 #define REG_RAMECC_STATUS (*(RoReg8 *)0x41020003UL) /**< \brief (RAMECC) Status */ 23 #define REG_RAMECC_ERRADDR (*(RoReg *)0x41020004UL) /**< \brief (RAMECC) Error Address */ 24 #define REG_RAMECC_DBGCTRL (*(RwReg8 *)0x4102000FUL) /**< \brief (RAMECC) Debug Control */ 25 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 26 27 #endif /* _MICROCHIP_PIC32CXSG_RAMECC_INSTANCE_FIXUP_H_ */ 28
