1 /** 2 * \file 3 * 4 * \brief Instance description for PM 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_PM_INSTANCE_ 30 #define _SAML21_PM_INSTANCE_ 31 32 /* ========== Register definition for PM peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_PM_CTRLA (0x40000000) /**< \brief (PM) Control A */ 35 #define REG_PM_SLEEPCFG (0x40000001) /**< \brief (PM) Sleep Configuration */ 36 #define REG_PM_PLCFG (0x40000002) /**< \brief (PM) Performance Level Configuration */ 37 #define REG_PM_INTENCLR (0x40000004) /**< \brief (PM) Interrupt Enable Clear */ 38 #define REG_PM_INTENSET (0x40000005) /**< \brief (PM) Interrupt Enable Set */ 39 #define REG_PM_INTFLAG (0x40000006) /**< \brief (PM) Interrupt Flag Status and Clear */ 40 #define REG_PM_STDBYCFG (0x40000008) /**< \brief (PM) Standby Configuration */ 41 #define REG_PM_PWSAKDLY (0x4000000C) /**< \brief (PM) Power Switch Acknowledge Delay */ 42 #else 43 #define REG_PM_CTRLA (*(RwReg8 *)0x40000000UL) /**< \brief (PM) Control A */ 44 #define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000001UL) /**< \brief (PM) Sleep Configuration */ 45 #define REG_PM_PLCFG (*(RwReg8 *)0x40000002UL) /**< \brief (PM) Performance Level Configuration */ 46 #define REG_PM_INTENCLR (*(RwReg8 *)0x40000004UL) /**< \brief (PM) Interrupt Enable Clear */ 47 #define REG_PM_INTENSET (*(RwReg8 *)0x40000005UL) /**< \brief (PM) Interrupt Enable Set */ 48 #define REG_PM_INTFLAG (*(RwReg8 *)0x40000006UL) /**< \brief (PM) Interrupt Flag Status and Clear */ 49 #define REG_PM_STDBYCFG (*(RwReg16*)0x40000008UL) /**< \brief (PM) Standby Configuration */ 50 #define REG_PM_PWSAKDLY (*(RwReg8 *)0x4000000CUL) /**< \brief (PM) Power Switch Acknowledge Delay */ 51 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 /* ========== Instance parameters for PM peripheral ========== */ 54 #define PM_PD_NUM 3 // Number of switchable Power Domain 55 56 #endif /* _SAML21_PM_INSTANCE_ */ 57
