1 /** 2 * \file 3 * 4 * \brief Instance description for PAC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_PAC_INSTANCE_ 30 #define _SAML21_PAC_INSTANCE_ 31 32 /* ========== Register definition for PAC peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_PAC_WRCTRL (0x44000000) /**< \brief (PAC) Write control */ 35 #define REG_PAC_EVCTRL (0x44000004) /**< \brief (PAC) Event control */ 36 #define REG_PAC_INTENCLR (0x44000008) /**< \brief (PAC) Interrupt enable clear */ 37 #define REG_PAC_INTENSET (0x44000009) /**< \brief (PAC) Interrupt enable set */ 38 #define REG_PAC_INTFLAGAHB (0x44000010) /**< \brief (PAC) Bridge interrupt flag status */ 39 #define REG_PAC_INTFLAGA (0x44000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ 40 #define REG_PAC_INTFLAGB (0x44000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ 41 #define REG_PAC_INTFLAGC (0x4400001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ 42 #define REG_PAC_INTFLAGD (0x44000020) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */ 43 #define REG_PAC_INTFLAGE (0x44000024) /**< \brief (PAC) Peripheral interrupt flag status - Bridge E */ 44 #define REG_PAC_STATUSA (0x44000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */ 45 #define REG_PAC_STATUSB (0x44000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */ 46 #define REG_PAC_STATUSC (0x4400003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */ 47 #define REG_PAC_STATUSD (0x44000040) /**< \brief (PAC) Peripheral write protection status - Bridge D */ 48 #define REG_PAC_STATUSE (0x44000044) /**< \brief (PAC) Peripheral write protection status - Bridge E */ 49 #else 50 #define REG_PAC_WRCTRL (*(RwReg *)0x44000000UL) /**< \brief (PAC) Write control */ 51 #define REG_PAC_EVCTRL (*(RwReg8 *)0x44000004UL) /**< \brief (PAC) Event control */ 52 #define REG_PAC_INTENCLR (*(RwReg8 *)0x44000008UL) /**< \brief (PAC) Interrupt enable clear */ 53 #define REG_PAC_INTENSET (*(RwReg8 *)0x44000009UL) /**< \brief (PAC) Interrupt enable set */ 54 #define REG_PAC_INTFLAGAHB (*(RwReg *)0x44000010UL) /**< \brief (PAC) Bridge interrupt flag status */ 55 #define REG_PAC_INTFLAGA (*(RwReg *)0x44000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ 56 #define REG_PAC_INTFLAGB (*(RwReg *)0x44000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ 57 #define REG_PAC_INTFLAGC (*(RwReg *)0x4400001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ 58 #define REG_PAC_INTFLAGD (*(RwReg *)0x44000020UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */ 59 #define REG_PAC_INTFLAGE (*(RwReg *)0x44000024UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge E */ 60 #define REG_PAC_STATUSA (*(RoReg *)0x44000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */ 61 #define REG_PAC_STATUSB (*(RoReg *)0x44000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */ 62 #define REG_PAC_STATUSC (*(RoReg *)0x4400003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */ 63 #define REG_PAC_STATUSD (*(RoReg *)0x44000040UL) /**< \brief (PAC) Peripheral write protection status - Bridge D */ 64 #define REG_PAC_STATUSE (*(RoReg *)0x44000044UL) /**< \brief (PAC) Peripheral write protection status - Bridge E */ 65 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 /* ========== Instance parameters for PAC peripheral ========== */ 68 #define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock 69 #define PAC_CLK_AHB_ID 14 // AHB clock index 70 #define PAC_HPB_NUM 5 // Number of bridges AHB/APB 71 #define PAC_INTFLAG_NUM 6 // Number of intflag registers 72 73 #endif /* _SAML21_PAC_INSTANCE_ */ 74
