1 /** 2 * \file 3 * 4 * \brief Instance description for OSCCTRL 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_OSCCTRL_INSTANCE_ 30 #define _SAML21_OSCCTRL_INSTANCE_ 31 32 /* ========== Register definition for OSCCTRL peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_OSCCTRL_INTENCLR (0x40000C00) /**< \brief (OSCCTRL) Interrupt Enable Clear */ 35 #define REG_OSCCTRL_INTENSET (0x40000C04) /**< \brief (OSCCTRL) Interrupt Enable Set */ 36 #define REG_OSCCTRL_INTFLAG (0x40000C08) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ 37 #define REG_OSCCTRL_STATUS (0x40000C0C) /**< \brief (OSCCTRL) Power and Clocks Status */ 38 #define REG_OSCCTRL_XOSCCTRL (0x40000C10) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ 39 #define REG_OSCCTRL_OSC16MCTRL (0x40000C14) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ 40 #define REG_OSCCTRL_DFLLCTRL (0x40000C18) /**< \brief (OSCCTRL) DFLL48M Control */ 41 #define REG_OSCCTRL_DFLLVAL (0x40000C1C) /**< \brief (OSCCTRL) DFLL48M Value */ 42 #define REG_OSCCTRL_DFLLMUL (0x40000C20) /**< \brief (OSCCTRL) DFLL48M Multiplier */ 43 #define REG_OSCCTRL_DFLLSYNC (0x40000C24) /**< \brief (OSCCTRL) DFLL48M Synchronization */ 44 #define REG_OSCCTRL_DPLLCTRLA (0x40000C28) /**< \brief (OSCCTRL) DPLL Control */ 45 #define REG_OSCCTRL_DPLLRATIO (0x40000C2C) /**< \brief (OSCCTRL) DPLL Ratio Control */ 46 #define REG_OSCCTRL_DPLLCTRLB (0x40000C30) /**< \brief (OSCCTRL) Digital Core Configuration */ 47 #define REG_OSCCTRL_DPLLPRESC (0x40000C34) /**< \brief (OSCCTRL) DPLL Prescaler */ 48 #define REG_OSCCTRL_DPLLSYNCBUSY (0x40000C38) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ 49 #define REG_OSCCTRL_DPLLSTATUS (0x40000C3C) /**< \brief (OSCCTRL) DPLL Status */ 50 #else 51 #define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40000C00UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */ 52 #define REG_OSCCTRL_INTENSET (*(RwReg *)0x40000C04UL) /**< \brief (OSCCTRL) Interrupt Enable Set */ 53 #define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40000C08UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ 54 #define REG_OSCCTRL_STATUS (*(RoReg *)0x40000C0CUL) /**< \brief (OSCCTRL) Power and Clocks Status */ 55 #define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40000C10UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ 56 #define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40000C14UL) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ 57 #define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40000C18UL) /**< \brief (OSCCTRL) DFLL48M Control */ 58 #define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40000C1CUL) /**< \brief (OSCCTRL) DFLL48M Value */ 59 #define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40000C20UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */ 60 #define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40000C24UL) /**< \brief (OSCCTRL) DFLL48M Synchronization */ 61 #define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40000C28UL) /**< \brief (OSCCTRL) DPLL Control */ 62 #define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x40000C2CUL) /**< \brief (OSCCTRL) DPLL Ratio Control */ 63 #define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40000C30UL) /**< \brief (OSCCTRL) Digital Core Configuration */ 64 #define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40000C34UL) /**< \brief (OSCCTRL) DPLL Prescaler */ 65 #define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40000C38UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ 66 #define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x40000C3CUL) /**< \brief (OSCCTRL) DPLL Status */ 67 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 /* ========== Instance parameters for OSCCTRL peripheral ========== */ 70 #define OSCCTRL_DFLL48M_COARSE_MSB 5 71 #define OSCCTRL_DFLL48M_FINE_MSB 9 72 #define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 73 #define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL 74 #define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K 75 #define OSCCTRL_DFLL48M_VERSION 0x320 76 #define OSCCTRL_FDPLL_VERSION 0x200 77 #define OSCCTRL_OSC16M_VERSION 0x100 78 #define OSCCTRL_XOSC_VERSION 0x120 79 80 #endif /* _SAML21_OSCCTRL_INSTANCE_ */ 81
