1 /** 2 * \file 3 * 4 * \brief Instance description for MCLK 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_MCLK_INSTANCE_ 30 #define _SAML21_MCLK_INSTANCE_ 31 32 /* ========== Register definition for MCLK peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_MCLK_CTRLA (0x40000400) /**< \brief (MCLK) Control A */ 35 #define REG_MCLK_INTENCLR (0x40000401) /**< \brief (MCLK) Interrupt Enable Clear */ 36 #define REG_MCLK_INTENSET (0x40000402) /**< \brief (MCLK) Interrupt Enable Set */ 37 #define REG_MCLK_INTFLAG (0x40000403) /**< \brief (MCLK) Interrupt Flag Status and Clear */ 38 #define REG_MCLK_CPUDIV (0x40000404) /**< \brief (MCLK) CPU Clock Division */ 39 #define REG_MCLK_LPDIV (0x40000405) /**< \brief (MCLK) Low-Power Clock Division */ 40 #define REG_MCLK_BUPDIV (0x40000406) /**< \brief (MCLK) Backup Clock Division */ 41 #define REG_MCLK_AHBMASK (0x40000410) /**< \brief (MCLK) AHB Mask */ 42 #define REG_MCLK_APBAMASK (0x40000414) /**< \brief (MCLK) APBA Mask */ 43 #define REG_MCLK_APBBMASK (0x40000418) /**< \brief (MCLK) APBB Mask */ 44 #define REG_MCLK_APBCMASK (0x4000041C) /**< \brief (MCLK) APBC Mask */ 45 #define REG_MCLK_APBDMASK (0x40000420) /**< \brief (MCLK) APBD Mask */ 46 #define REG_MCLK_APBEMASK (0x40000424) /**< \brief (MCLK) APBE Mask */ 47 #else 48 #define REG_MCLK_CTRLA (*(RwReg8 *)0x40000400UL) /**< \brief (MCLK) Control A */ 49 #define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000401UL) /**< \brief (MCLK) Interrupt Enable Clear */ 50 #define REG_MCLK_INTENSET (*(RwReg8 *)0x40000402UL) /**< \brief (MCLK) Interrupt Enable Set */ 51 #define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000403UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */ 52 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000404UL) /**< \brief (MCLK) CPU Clock Division */ 53 #define REG_MCLK_LPDIV (*(RwReg8 *)0x40000405UL) /**< \brief (MCLK) Low-Power Clock Division */ 54 #define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000406UL) /**< \brief (MCLK) Backup Clock Division */ 55 #define REG_MCLK_AHBMASK (*(RwReg *)0x40000410UL) /**< \brief (MCLK) AHB Mask */ 56 #define REG_MCLK_APBAMASK (*(RwReg *)0x40000414UL) /**< \brief (MCLK) APBA Mask */ 57 #define REG_MCLK_APBBMASK (*(RwReg *)0x40000418UL) /**< \brief (MCLK) APBB Mask */ 58 #define REG_MCLK_APBCMASK (*(RwReg *)0x4000041CUL) /**< \brief (MCLK) APBC Mask */ 59 #define REG_MCLK_APBDMASK (*(RwReg *)0x40000420UL) /**< \brief (MCLK) APBD Mask */ 60 #define REG_MCLK_APBEMASK (*(RwReg *)0x40000424UL) /**< \brief (MCLK) APBE Mask */ 61 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 /* ========== Instance parameters for MCLK peripheral ========== */ 64 #define MCLK_CTRLA_MCSEL_GCLK 1 65 #define MCLK_CTRLA_MCSEL_OSC8M 0 66 #define MCLK_MCLK_CLK_APB_NUM 5 67 #define MCLK_SYSTEM_CLOCK 4000000 // System Clock Frequency at Reset 68 69 #endif /* _SAML21_MCLK_INSTANCE_ */ 70
