1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_CCL_INSTANCE_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_CCL_INSTANCE_FIXUP_H_ 9 10 /* ========== Register definition for CCL peripheral ========== */ 11 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 #define REG_CCL_CTRL (0x42003800) /**< \brief (CCL) Control */ 13 #define REG_CCL_SEQCTRL0 (0x42003804) /**< \brief (CCL) SEQ Control x 0 */ 14 #define REG_CCL_SEQCTRL1 (0x42003805) /**< \brief (CCL) SEQ Control x 1 */ 15 #define REG_CCL_LUTCTRL0 (0x42003808) /**< \brief (CCL) LUT Control x 0 */ 16 #define REG_CCL_LUTCTRL1 (0x4200380C) /**< \brief (CCL) LUT Control x 1 */ 17 #define REG_CCL_LUTCTRL2 (0x42003810) /**< \brief (CCL) LUT Control x 2 */ 18 #define REG_CCL_LUTCTRL3 (0x42003814) /**< \brief (CCL) LUT Control x 3 */ 19 #else 20 #define REG_CCL_CTRL (*(RwReg8 *)0x42003800UL) /**< \brief (CCL) Control */ 21 #define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42003804UL) /**< \brief (CCL) SEQ Control x 0 */ 22 #define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */ 23 #define REG_CCL_LUTCTRL0 (*(RwReg *)0x42003808UL) /**< \brief (CCL) LUT Control x 0 */ 24 #define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200380CUL) /**< \brief (CCL) LUT Control x 1 */ 25 #define REG_CCL_LUTCTRL2 (*(RwReg *)0x42003810UL) /**< \brief (CCL) LUT Control x 2 */ 26 #define REG_CCL_LUTCTRL3 (*(RwReg *)0x42003814UL) /**< \brief (CCL) LUT Control x 3 */ 27 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 28 29 #endif /* _MICROCHIP_PIC32CXSG_CCL_INSTANCE_FIXUP_H_ */ 30
