1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019 Intel Corporation. All rights reserved. 4 * 5 * Author: Marcin Maka <marcin.maka@linux.intel.com> 6 */ 7 8 /** 9 * \file include/ipc/header-intel-cavs.h 10 * \brief IPC command header for Intel cAVS platforms 11 * \author Marcin Maka <marcin.maka@linux.intel.com> 12 */ 13 14 #ifndef __IPC_HEADER_INTEL_CAVS_H__ 15 #define __IPC_HEADER_INTEL_CAVS_H__ 16 17 #include <sof/bit.h> 18 19 /* Primary register, mapped to 20 * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+) 21 * - DIPCT in cAVS 1.5 IPC 22 * 23 * Secondary register, mapped to: 24 * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+) 25 * - DIPCTE in cAVS 1.5 IPC 26 */ 27 28 /* Common bits in primary register */ 29 30 #define CAVS_IPC_RSVD_31 BIT(31) 31 32 /** \brief Target, 0 - global message, 1 - message to a module */ 33 #define CAVS_IPC_MSG_TGT BIT(30) 34 35 /** \brief Direction, 0 - request, 1 - response */ 36 #define CAVS_IPC_RSP BIT(29) 37 38 #define CAVS_IPC_TYPE_SHIFT 24 39 #define CAVS_IPC_TYPE_MASK MASK(28, 24) 40 #define CAVS_IPC_TYPE(x) ((x) << CAVS_IPC_TYPE_SHIFT) 41 42 /* Bits in primary register for Module messages (CAVS_IPC_MSG_TGT set to 1) */ 43 44 /** \brief ID of the target module instance */ 45 #define CAVS_IPC_MOD_INSTANCE_ID_MASK MASK(23, 16) 46 47 /** \brief ID of the target module */ 48 #define CAVS_IPC_MOD_ID_MASK MASK(15, 0) 49 50 /* Definition of bits in secondary register are message specific 51 * and are defined for each message separately later. 52 */ 53 54 /* Primary register :: type value for Module messages */ 55 56 #define CAVS_IPC_MOD_INIT_INSTANCE CAVS_IPC_TYPE(0x0U) 57 #define CAVS_IPC_MOD_CFG_GET CAVS_IPC_TYPE(0x1U) 58 #define CAVS_IPC_MOD_CFG_SET CAVS_IPC_TYPE(0x2U) 59 #define CAVS_IPC_MOD_LARGE_CFG_GET CAVS_IPC_TYPE(0x3U) 60 #define CAVS_IPC_MOD_LARGE_CFG_SET CAVS_IPC_TYPE(0x4U) 61 #define CAVS_IPC_MOD_BIND CAVS_IPC_TYPE(0x5U) 62 #define CAVS_IPC_MOD_UNBIND CAVS_IPC_TYPE(0x6U) 63 #define CAVS_IPC_MOD_SET_DX CAVS_IPC_TYPE(0x7U) 64 #define CAVS_IPC_MOD_SET_D0IX CAVS_IPC_TYPE(0x8U) 65 #define CAVS_IPC_MOD_ENTER_RESTORE CAVS_IPC_TYPE(0x9U) 66 #define CAVS_IPC_MOD_EXIT_RESTORE CAVS_IPC_TYPE(0xaU) 67 #define CAVS_IPC_MOD_DELETE_INSTANCE CAVS_IPC_TYPE(0xbU) 68 #define CAVS_IPC_MOD_NOTIFICATION CAVS_IPC_TYPE(0xcU) 69 70 /* Secondary register bits for Module::SetD0iX 71 * ( Primary 72 * tgt = 1 (module message) 73 * rsp = 0 (request) 74 * type = CAVS_IPC_MOD_SET_D0IX 75 * ) 76 */ 77 78 /** \brief Valid bits for SetD0ix */ 79 #define CAVS_IPC_MOD_SETD0IX_BIT_MASK MASK(7, 0) 80 81 /** \brief Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) */ 82 #define CAVS_IPC_MOD_SETD0IX_NO_TRACE BIT(4) 83 84 /** \brief Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */ 85 #define CAVS_IPC_MOD_SETD0IX_PCG BIT(3) 86 87 /** \brief Prevent power gating (0 - D0ix transitions allowed) */ 88 #define CAVS_IPC_MOD_SETD0IX_PPG BIT(2) 89 90 /** \brief Streaming active */ 91 #define CAVS_IPC_MOD_SETD0IX_STREAMING BIT(1) 92 93 /** \brief Legacy wake type, unused in cAVS 1.8+ */ 94 #define CAVS_IPC_MOD_SETD0IX_WAKE_TYPE BIT(0) 95 96 #endif /* __IPC_HEADER_INTEL_CAVS_H__ */ 97
