1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_M0PLUS_H 9 #define _HARDWARE_STRUCTS_M0PLUS_H 10 11 /** 12 * \file rp2040/m0plus.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/m0plus.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 uint32_t _pad0[14340]; 28 29 _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR 30 // SysTick Control and Status Register 31 // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read 32 // 0x00000004 [2] CLKSOURCE (0) SysTick clock source 33 // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + 34 // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + 35 io_rw_32 syst_csr; 36 37 _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR 38 // SysTick Reload Value Register 39 // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... 40 io_rw_32 syst_rvr; 41 42 _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR 43 // SysTick Current Value Register 44 // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter 45 io_rw_32 syst_cvr; 46 47 _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB 48 // SysTick Calibration Value Register 49 // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... 50 // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... 51 // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... 52 io_ro_32 syst_calib; 53 54 uint32_t _pad1[56]; 55 56 _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER 57 // Interrupt Set-Enable Register 58 // 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits 59 io_rw_32 nvic_iser; 60 61 uint32_t _pad2[31]; 62 63 _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER 64 // Interrupt Clear-Enable Register 65 // 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits 66 io_rw_32 nvic_icer; 67 68 uint32_t _pad3[31]; 69 70 _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR 71 // Interrupt Set-Pending Register 72 // 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits 73 io_rw_32 nvic_ispr; 74 75 uint32_t _pad4[31]; 76 77 _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR 78 // Interrupt Clear-Pending Register 79 // 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits 80 io_rw_32 nvic_icpr; 81 82 uint32_t _pad5[95]; 83 84 // (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes) 85 _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0 86 // Interrupt Priority Register 0 87 // 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3 88 // 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2 89 // 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1 90 // 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0 91 io_rw_32 nvic_ipr[8]; 92 93 uint32_t _pad6[568]; 94 95 _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID 96 // CPUID Base Register 97 // 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM 98 // 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: + 99 // 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: + 100 // 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+ 101 // 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: + 102 io_ro_32 cpuid; 103 104 _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR 105 // Interrupt Control and State Register 106 // 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI 107 // 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit 108 // 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit 109 // 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit 110 // 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit 111 // 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted 112 // 0x00400000 [22] ISRPENDING (0) External interrupt pending flag 113 // 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority... 114 // 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field 115 io_rw_32 icsr; 116 117 _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR 118 // Vector Table Offset Register 119 // 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address 120 io_rw_32 vtor; 121 122 _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR 123 // Application Interrupt and Reset Control Register 124 // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + 125 // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + 126 // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... 127 // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... 128 io_rw_32 aircr; 129 130 _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR 131 // System Control Register 132 // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + 133 // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... 134 // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... 135 io_rw_32 scr; 136 137 _REG_(M0PLUS_CCR_OFFSET) // M0PLUS_CCR 138 // Configuration and Control Register 139 // 0x00000200 [9] STKALIGN (0) Always reads as one, indicates 8-byte stack alignment on... 140 // 0x00000008 [3] UNALIGN_TRP (0) Always reads as one, indicates that all unaligned... 141 io_ro_32 ccr; 142 143 uint32_t _pad7; 144 145 // (Description copied from array index 0 register M0PLUS_SHPR2 applies similarly to other array indexes) 146 _REG_(M0PLUS_SHPR2_OFFSET) // M0PLUS_SHPR2 147 // System Handler Priority Register 2 148 // 0xc0000000 [31:30] PRI_11 (0x0) Priority of system handler 11, SVCall 149 io_rw_32 shpr[2]; 150 151 _REG_(M0PLUS_SHCSR_OFFSET) // M0PLUS_SHCSR 152 // System Handler Control and State Register 153 // 0x00008000 [15] SVCALLPENDED (0) Reads as 1 if SVCall is Pending 154 io_rw_32 shcsr; 155 156 uint32_t _pad8[26]; 157 158 _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE 159 // MPU Type Register 160 // 0x00ff0000 [23:16] IREGION (0x00) Instruction region 161 // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU 162 // 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps 163 io_ro_32 mpu_type; 164 165 _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL 166 // MPU Control Register 167 // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a... 168 // 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs 169 // 0x00000001 [0] ENABLE (0) Enables the MPU 170 io_rw_32 mpu_ctrl; 171 172 _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR 173 // MPU Region Number Register 174 // 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and... 175 io_rw_32 mpu_rnr; 176 177 _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR 178 // MPU Region Base Address Register 179 // 0xffffff00 [31:8] ADDR (0x000000) Base address of the region 180 // 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the... 181 // 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base... 182 io_rw_32 mpu_rbar; 183 184 _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR 185 // MPU Region Attribute and Size Register 186 // 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field 187 // 0x0000ff00 [15:8] SRD (0x00) Subregion Disable 188 // 0x0000003e [5:1] SIZE (0x00) Indicates the region size 189 // 0x00000001 [0] ENABLE (0) Enables the region 190 io_rw_32 mpu_rasr; 191 } m0plus_hw_t; 192 193 #define ppb_hw ((m0plus_hw_t *)PPB_BASE) 194 static_assert(sizeof (m0plus_hw_t) == 0xeda4, ""); 195 196 #endif // _HARDWARE_STRUCTS_M0PLUS_H 197 198
