1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_HSTX_CTRL_H 9 #define _HARDWARE_STRUCTS_HSTX_CTRL_H 10 11 /** 12 * \file rp2350/hstx_ctrl.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/hstx_ctrl.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_ctrl 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/hstx_ctrl.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(HSTX_CTRL_CSR_OFFSET) // HSTX_CTRL_CSR 28 // 0xf0000000 [31:28] CLKDIV (0x1) Clock period of the generated clock, measured in HSTX... 29 // 0x0f000000 [27:24] CLKPHASE (0x0) Set the initial phase of the generated clock 30 // 0x001f0000 [20:16] N_SHIFTS (0x05) Number of times to shift the shift register before... 31 // 0x00001f00 [12:8] SHIFT (0x06) How many bits to right-rotate the shift register by each cycle 32 // 0x00000060 [6:5] COUPLED_SEL (0x0) Select which PIO to use for coupled mode operation 33 // 0x00000010 [4] COUPLED_MODE (0) Enable the PIO-to-HSTX 1:1 connection 34 // 0x00000002 [1] EXPAND_EN (0) Enable the command expander 35 // 0x00000001 [0] EN (0) When EN is 1, the HSTX will shift out data as it appears... 36 io_rw_32 csr; 37 38 // (Description copied from array index 0 register HSTX_CTRL_BIT0 applies similarly to other array indexes) 39 _REG_(HSTX_CTRL_BIT0_OFFSET) // HSTX_CTRL_BIT0 40 // Data control register for output bit 0 41 // 0x00020000 [17] CLK (0) Connect this output to the generated clock, rather than... 42 // 0x00010000 [16] INV (0) Invert this data output (logical NOT) 43 // 0x00001f00 [12:8] SEL_N (0x00) Shift register data bit select for the second half of... 44 // 0x0000001f [4:0] SEL_P (0x00) Shift register data bit select for the first half of the... 45 io_rw_32 bit[8]; 46 47 _REG_(HSTX_CTRL_EXPAND_SHIFT_OFFSET) // HSTX_CTRL_EXPAND_SHIFT 48 // Configure the optional shifter inside the command expander 49 // 0x1f000000 [28:24] ENC_N_SHIFTS (0x01) Number of times to consume from the shift register... 50 // 0x001f0000 [20:16] ENC_SHIFT (0x00) How many bits to right-rotate the shift register by each... 51 // 0x00001f00 [12:8] RAW_N_SHIFTS (0x01) Number of times to consume from the shift register... 52 // 0x0000001f [4:0] RAW_SHIFT (0x00) How many bits to right-rotate the shift register by each... 53 io_rw_32 expand_shift; 54 55 _REG_(HSTX_CTRL_EXPAND_TMDS_OFFSET) // HSTX_CTRL_EXPAND_TMDS 56 // Configure the optional TMDS encoder inside the command expander 57 // 0x00e00000 [23:21] L2_NBITS (0x0) Number of valid data bits for the lane 2 TMDS encoder,... 58 // 0x001f0000 [20:16] L2_ROT (0x00) Right-rotate applied to the current shifter data before... 59 // 0x0000e000 [15:13] L1_NBITS (0x0) Number of valid data bits for the lane 1 TMDS encoder,... 60 // 0x00001f00 [12:8] L1_ROT (0x00) Right-rotate applied to the current shifter data before... 61 // 0x000000e0 [7:5] L0_NBITS (0x0) Number of valid data bits for the lane 0 TMDS encoder,... 62 // 0x0000001f [4:0] L0_ROT (0x00) Right-rotate applied to the current shifter data before... 63 io_rw_32 expand_tmds; 64 } hstx_ctrl_hw_t; 65 66 #define hstx_ctrl_hw ((hstx_ctrl_hw_t *)HSTX_CTRL_BASE) 67 static_assert(sizeof (hstx_ctrl_hw_t) == 0x002c, ""); 68 69 #endif // _HARDWARE_STRUCTS_HSTX_CTRL_H 70 71
