1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_GLITCH_DETECTOR_H 9 #define _HARDWARE_STRUCTS_GLITCH_DETECTOR_H 10 11 /** 12 * \file rp2350/glitch_detector.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/glitch_detector.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_glitch_detector 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/glitch_detector.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(GLITCH_DETECTOR_ARM_OFFSET) // GLITCH_DETECTOR_ARM 28 // Forcibly arm the glitch detectors, if they are not already armed by OTP 29 // 0x0000ffff [15:0] ARM (0x5bad) 30 io_rw_32 arm; 31 32 _REG_(GLITCH_DETECTOR_DISARM_OFFSET) // GLITCH_DETECTOR_DISARM 33 // 0x0000ffff [15:0] DISARM (0x0000) Forcibly disarm the glitch detectors, if they are armed by OTP 34 io_rw_32 disarm; 35 36 _REG_(GLITCH_DETECTOR_SENSITIVITY_OFFSET) // GLITCH_DETECTOR_SENSITIVITY 37 // Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults 38 // 0xff000000 [31:24] DEFAULT (0x00) 39 // 0x0000c000 [15:14] DET3_INV (0x0) Must be the inverse of DET3, else the default value is used 40 // 0x00003000 [13:12] DET2_INV (0x0) Must be the inverse of DET2, else the default value is used 41 // 0x00000c00 [11:10] DET1_INV (0x0) Must be the inverse of DET1, else the default value is used 42 // 0x00000300 [9:8] DET0_INV (0x0) Must be the inverse of DET0, else the default value is used 43 // 0x000000c0 [7:6] DET3 (0x0) Set sensitivity for detector 3 44 // 0x00000030 [5:4] DET2 (0x0) Set sensitivity for detector 2 45 // 0x0000000c [3:2] DET1 (0x0) Set sensitivity for detector 1 46 // 0x00000003 [1:0] DET0 (0x0) Set sensitivity for detector 0 47 io_rw_32 sensitivity; 48 49 _REG_(GLITCH_DETECTOR_LOCK_OFFSET) // GLITCH_DETECTOR_LOCK 50 // 0x000000ff [7:0] LOCK (0x00) Write any nonzero value to disable writes to ARM,... 51 io_rw_32 lock; 52 53 _REG_(GLITCH_DETECTOR_TRIG_STATUS_OFFSET) // GLITCH_DETECTOR_TRIG_STATUS 54 // Set when a detector output triggers 55 // 0x00000008 [3] DET3 (0) 56 // 0x00000004 [2] DET2 (0) 57 // 0x00000002 [1] DET1 (0) 58 // 0x00000001 [0] DET0 (0) 59 io_rw_32 trig_status; 60 61 _REG_(GLITCH_DETECTOR_TRIG_FORCE_OFFSET) // GLITCH_DETECTOR_TRIG_FORCE 62 // Simulate the firing of one or more detectors 63 // 0x0000000f [3:0] TRIG_FORCE (0x0) 64 io_wo_32 trig_force; 65 } glitch_detector_hw_t; 66 67 #define glitch_detector_hw ((glitch_detector_hw_t *)GLITCH_DETECTOR_BASE) 68 static_assert(sizeof (glitch_detector_hw_t) == 0x0018, ""); 69 70 #endif // _HARDWARE_STRUCTS_GLITCH_DETECTOR_H 71 72
