1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : CORESIGHT_TRACE 10 // Version : 1 11 // Bus type : ahbl 12 // Description : Coresight block - RP specific registers 13 // ============================================================================= 14 #ifndef _HARDWARE_REGS_CORESIGHT_TRACE_H 15 #define _HARDWARE_REGS_CORESIGHT_TRACE_H 16 // ============================================================================= 17 // Register : CORESIGHT_TRACE_CTRL_STATUS 18 // Description : Control and status register 19 #define CORESIGHT_TRACE_CTRL_STATUS_OFFSET _u(0x00000000) 20 #define CORESIGHT_TRACE_CTRL_STATUS_BITS _u(0x00000003) 21 #define CORESIGHT_TRACE_CTRL_STATUS_RESET _u(0x00000001) 22 // ----------------------------------------------------------------------------- 23 // Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW 24 // Description : This status flag is set high when trace data has been dropped 25 // due to the FIFO being full at the point trace data was sampled. 26 // Write 1 to acknowledge and clear the bit. 27 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_RESET _u(0x0) 28 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_BITS _u(0x00000002) 29 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_MSB _u(1) 30 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_LSB _u(1) 31 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_ACCESS "RW" 32 // ----------------------------------------------------------------------------- 33 // Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH 34 // Description : Set to 1 to continuously hold the trace FIFO in a flushed state 35 // and prevent overflow. 36 // 37 // Before clearing this flag, configure and start a DMA channel 38 // with the correct DREQ for the TRACE_CAPTURE_FIFO register. 39 // 40 // Clear this flag to begin sampling trace data, and set once 41 // again once the trace capture buffer is full. You must configure 42 // the TPIU in order to generate trace packets to be captured, as 43 // well as components like the ETM further upstream to generate 44 // the event stream propagated to the TPIU. 45 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_RESET _u(0x1) 46 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_BITS _u(0x00000001) 47 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_MSB _u(0) 48 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_LSB _u(0) 49 #define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_ACCESS "RW" 50 // ============================================================================= 51 // Register : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO 52 // Description : FIFO for trace data captured from the TPIU 53 #define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET _u(0x00000004) 54 #define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_BITS _u(0xffffffff) 55 #define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RESET _u(0x00000000) 56 // ----------------------------------------------------------------------------- 57 // Field : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA 58 // Description : Read from an 8 x 32-bit FIFO containing trace data captured 59 // from the TPIU. 60 // 61 // Hardware pushes to the FIFO on rising edges of clk_sys, when 62 // either of the following is true: 63 // 64 // * TPIU TRACECTL output is low (normal trace data) 65 // 66 // * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and 67 // TRACEDATA1 are both low (trigger packet) 68 // 69 // These conditions are in accordance with Arm Coresight 70 // Architecture Spec v3.0 section D3.3.3: Decoding requirements 71 // for Trace Capture Devices 72 // 73 // The data captured into the FIFO is the full 32-bit TRACEDATA 74 // bus output by the TPIU. Note that the TPIU is a DDR output at 75 // half of clk_sys, therefore this interface can capture the full 76 // 32-bit TPIU DDR output bandwidth as it samples once per active 77 // edge of the TPIU output clock. 78 #define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_RESET _u(0x00000000) 79 #define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_BITS _u(0xffffffff) 80 #define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MSB _u(31) 81 #define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_LSB _u(0) 82 #define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_ACCESS "RF" 83 // ============================================================================= 84 #endif // _HARDWARE_REGS_CORESIGHT_TRACE_H 85 86
