1/*
2 * Copyright 2024 NXP
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include <nxp/nxp_imx/mimx9596avzxn-pinctrl.dtsi>
7
8&pinctrl {
9	lpi2c5_default: lpi2c5_default {
10		group0 {
11			pinmux = <&iomuxc_gpio_io23_lpi2c_scl_lpi2c5_scl>,
12				<&iomuxc_gpio_io22_lpi2c_sda_lpi2c5_sda>;
13			drive-open-drain;
14			slew-rate = "slightly_fast";
15			drive-strength = "x4";
16			input-enable;
17		};
18	};
19
20	lpi2c7_default: lpi2c7_default {
21		group0 {
22			pinmux = <&iomuxc_gpio_io09_lpi2c_scl_lpi2c7_scl>,
23				<&iomuxc_gpio_io08_lpi2c_sda_lpi2c7_sda>;
24			drive-open-drain;
25			slew-rate = "slightly_fast";
26			drive-strength = "x4";
27			input-enable;
28		};
29	};
30
31	lpuart1_default: lpuart1_default {
32		group0 {
33			pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>,
34				<&iomuxc_uart1_txd_lpuart_tx_lpuart1_tx>;
35			bias-pull-up;
36			slew-rate = "slightly_fast";
37			drive-strength = "x4";
38		};
39	};
40
41	lpuart3_default: lpuart3_default {
42		group0 {
43			pinmux = <&iomuxc_gpio_io15_lpuart_rx_lpuart3_rx>,
44				<&iomuxc_gpio_io14_lpuart_tx_lpuart3_tx>;
45			bias-pull-up;
46			slew-rate = "slightly_fast";
47			drive-strength = "x4";
48		};
49	};
50
51	sai3_default: sai3_default {
52		group0 {
53			pinmux = <&iomuxc_gpio_io16_sai_tx_bclk_sai3_tx_bclk>,
54				 <&iomuxc_gpio_io17_sai_mclk_sai3_mclk>,
55				 <&iomuxc_gpio_io20_sai_rx_data_bit_sai3_rx_data_bit0>,
56				 <&iomuxc_gpio_io21_sai_tx_data_bit_sai3_tx_data_bit0>,
57				 <&iomuxc_gpio_io26_sai_tx_sync_sai3_tx_sync>;
58			bias-pull-up;
59			slew-rate = "slightly_fast";
60			drive-strength = "x4";
61		};
62	};
63
64	tpm2_default: tpm2_default {
65		group0 {
66			pinmux = <&iomuxc_i2c2_scl_tpm_ch_tpm2_ch2>,
67				<&iomuxc_i2c2_sda_tpm_ch_tpm2_ch3>;
68			drive-open-drain;
69			slew-rate = "slightly_fast";
70			drive-strength = "x4";
71			input-enable;
72		};
73	};
74};
75