1/*
2 * Copyright 2022,2024 NXP
3 * SPDX-License-Identifier: Apache-2.0
4 *
5 */
6
7#include <nxp/nxp_imx/mimx9352cvuxk-pinctrl.dtsi>
8
9&pinctrl {
10	uart1_default: uart1_default {
11		group0 {
12			pinmux = <&iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx>,
13				<&iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx>;
14			bias-pull-up;
15			slew-rate = "slightly_fast";
16			drive-strength = "x5";
17		};
18	};
19
20	uart2_default: uart2_default {
21		group0 {
22			pinmux = <&iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx>,
23				<&iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx>;
24			bias-pull-up;
25			slew-rate = "slightly_fast";
26			drive-strength = "x5";
27		};
28	};
29
30	i2c1_default: i2c1_default {
31		group0 {
32			pinmux = <&iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl>,
33				<&iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda>;
34			drive-strength = "x5";
35			drive-open-drain;
36			slew-rate = "fast";
37			input-enable;
38		};
39	};
40
41	i2c2_default: i2c2_default {
42		group0 {
43			pinmux = <&iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl>,
44				<&iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda>;
45			drive-strength = "x5";
46			drive-open-drain;
47			slew-rate = "fast";
48			input-enable;
49		};
50	};
51
52	i2c3_default: i2c3_default {
53		group0 {
54			pinmux = <&iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl>,
55				<&iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda>;
56			drive-strength = "x5";
57			drive-open-drain;
58			slew-rate = "fast";
59			input-enable;
60		};
61	};
62
63	i2c4_default: i2c4_default {
64		group0 {
65			pinmux = <&iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl>,
66				<&iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda>;
67			drive-strength = "x5";
68			drive-open-drain;
69			slew-rate = "fast";
70			input-enable;
71		};
72	};
73
74	spi3_default: spi3_default {
75		group0 {
76			pinmux = <&iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1>,
77				<&iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0>,
78				<&iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin>,
79				<&iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout>,
80				<&iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck>;
81			slew-rate = "fast";
82			drive-strength = "x5";
83		};
84	};
85
86	pinmux_mdio: pinmux_mdio {
87		group0 {
88			pinmux = <&iomuxc1_enet2_mdc_enet_mdc_enet1_mdc>,
89				<&iomuxc1_enet2_mdio_enet_mdio_enet1_mdio>;
90			bias-pull-down;
91			slew-rate = "slightly_fast";
92			drive-strength = "x6";
93		};
94	};
95
96	pinmux_enet: pinmux_enet {
97		group0 {
98			pinmux = <&iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
99				<&iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
100				<&iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
101				<&iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
102				<&iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>,
103				<&iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0>,
104				<&iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1>,
105				<&iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2>,
106				<&iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3>,
107				<&iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
108			bias-pull-down;
109			slew-rate = "slightly_fast";
110			drive-strength = "x6";
111		};
112
113		group1 {
114			pinmux = <&iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
115				<&iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc>;
116			bias-pull-down;
117			slew-rate = "fast";
118			drive-strength = "x6";
119		};
120
121	};
122
123};
124