1 /* 2 * Copyright (c) 2017 PHYTEC Messtechnik GmbH 3 * 4 * Portions of this file are derived from ieee802154_cc2520.h that is 5 * Copyright (c) 2016 Intel Corporation. 6 * 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10 #ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_ 11 #define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_ 12 13 #include <zephyr/linker/sections.h> 14 #include <zephyr/sys/atomic.h> 15 #include <zephyr/drivers/spi.h> 16 17 struct mcr20a_config { 18 struct spi_dt_spec bus; 19 struct gpio_dt_spec irq_gpio; 20 struct gpio_dt_spec reset_gpio; 21 }; 22 23 /* Runtime context structure 24 *************************** 25 */ 26 struct mcr20a_context { 27 struct net_if *iface; 28 /**************************/ 29 struct gpio_callback irqb_cb; 30 const struct device *spi; 31 struct spi_config spi_cfg; 32 uint8_t mac_addr[8]; 33 struct k_mutex phy_mutex; 34 struct k_sem isr_sem; 35 /*********TX + CCA*********/ 36 struct k_sem seq_sync; 37 atomic_t seq_retval; 38 /************RX************/ 39 K_KERNEL_STACK_MEMBER(mcr20a_rx_stack, 40 CONFIG_IEEE802154_MCR20A_RX_STACK_SIZE); 41 struct k_thread mcr20a_rx_thread; 42 }; 43 44 #include "ieee802154_mcr20a_regs.h" 45 46 uint8_t z_mcr20a_read_reg(const struct device *dev, bool dreg, uint8_t addr); 47 bool z_mcr20a_write_reg(const struct device *dev, bool dreg, uint8_t addr, 48 uint8_t value); 49 bool z_mcr20a_write_burst(const struct device *dev, bool dreg, uint16_t addr, 50 uint8_t *data_buf, uint8_t len); 51 bool z_mcr20a_read_burst(const struct device *dev, bool dreg, uint16_t addr, 52 uint8_t *data_buf, uint8_t len); 53 54 #define DEFINE_REG_READ(__reg_name, __reg_addr, __dreg) \ 55 static inline uint8_t read_reg_##__reg_name(const struct device *dev) \ 56 { \ 57 return z_mcr20a_read_reg(dev, __dreg, __reg_addr); \ 58 } 59 60 #define DEFINE_REG_WRITE(__reg_name, __reg_addr, __dreg) \ 61 static inline bool write_reg_##__reg_name(const struct device *dev, \ 62 uint8_t value) \ 63 { \ 64 return z_mcr20a_write_reg(dev, __dreg, __reg_addr, value); \ 65 } 66 67 #define DEFINE_DREG_READ(__reg_name, __reg_addr) \ 68 DEFINE_REG_READ(__reg_name, __reg_addr, true) 69 #define DEFINE_DREG_WRITE(__reg_name, __reg_addr) \ 70 DEFINE_REG_WRITE(__reg_name, __reg_addr, true) 71 72 #define DEFINE_IREG_READ(__reg_name, __reg_addr) \ 73 DEFINE_REG_READ(__reg_name, __reg_addr, false) 74 #define DEFINE_IREG_WRITE(__reg_name, __reg_addr) \ 75 DEFINE_REG_WRITE(__reg_name, __reg_addr, false) 76 77 DEFINE_DREG_READ(irqsts1, MCR20A_IRQSTS1) 78 DEFINE_DREG_READ(irqsts2, MCR20A_IRQSTS2) 79 DEFINE_DREG_READ(irqsts3, MCR20A_IRQSTS3) 80 DEFINE_DREG_READ(phy_ctrl1, MCR20A_PHY_CTRL1) 81 DEFINE_DREG_READ(phy_ctrl2, MCR20A_PHY_CTRL2) 82 DEFINE_DREG_READ(phy_ctrl3, MCR20A_PHY_CTRL3) 83 DEFINE_DREG_READ(rx_frm_len, MCR20A_RX_FRM_LEN) 84 DEFINE_DREG_READ(phy_ctrl4, MCR20A_PHY_CTRL4) 85 DEFINE_DREG_READ(src_ctrl, MCR20A_SRC_CTRL) 86 DEFINE_DREG_READ(cca1_ed_fnl, MCR20A_CCA1_ED_FNL) 87 DEFINE_DREG_READ(pll_int0, MCR20A_PLL_INT0) 88 DEFINE_DREG_READ(pa_pwr, MCR20A_PA_PWR) 89 DEFINE_DREG_READ(seq_state, MCR20A_SEQ_STATE) 90 DEFINE_DREG_READ(lqi_value, MCR20A_LQI_VALUE) 91 DEFINE_DREG_READ(rssi_cca_cnt, MCR20A_RSSI_CCA_CNT) 92 DEFINE_DREG_READ(asm_ctrl1, MCR20A_ASM_CTRL1) 93 DEFINE_DREG_READ(asm_ctrl2, MCR20A_ASM_CTRL2) 94 DEFINE_DREG_READ(overwrite_ver, MCR20A_OVERWRITE_VER) 95 DEFINE_DREG_READ(clk_out_ctrl, MCR20A_CLK_OUT_CTRL) 96 DEFINE_DREG_READ(pwr_modes, MCR20A_PWR_MODES) 97 98 DEFINE_DREG_WRITE(irqsts1, MCR20A_IRQSTS1) 99 DEFINE_DREG_WRITE(irqsts2, MCR20A_IRQSTS2) 100 DEFINE_DREG_WRITE(irqsts3, MCR20A_IRQSTS3) 101 DEFINE_DREG_WRITE(phy_ctrl1, MCR20A_PHY_CTRL1) 102 DEFINE_DREG_WRITE(phy_ctrl2, MCR20A_PHY_CTRL2) 103 DEFINE_DREG_WRITE(phy_ctrl3, MCR20A_PHY_CTRL3) 104 DEFINE_DREG_WRITE(phy_ctrl4, MCR20A_PHY_CTRL4) 105 DEFINE_DREG_WRITE(src_ctrl, MCR20A_SRC_CTRL) 106 DEFINE_DREG_WRITE(pll_int0, MCR20A_PLL_INT0) 107 DEFINE_DREG_WRITE(pa_pwr, MCR20A_PA_PWR) 108 DEFINE_DREG_WRITE(asm_ctrl1, MCR20A_ASM_CTRL1) 109 DEFINE_DREG_WRITE(asm_ctrl2, MCR20A_ASM_CTRL2) 110 DEFINE_DREG_WRITE(overwrite_ver, MCR20A_OVERWRITE_VER) 111 DEFINE_DREG_WRITE(clk_out_ctrl, MCR20A_CLK_OUT_CTRL) 112 DEFINE_DREG_WRITE(pwr_modes, MCR20A_PWR_MODES) 113 114 DEFINE_IREG_READ(part_id, MCR20A_PART_ID) 115 DEFINE_IREG_READ(rx_frame_filter, MCR20A_RX_FRAME_FILTER) 116 DEFINE_IREG_READ(cca1_thresh, MCR20A_CCA1_THRESH) 117 DEFINE_IREG_READ(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP) 118 DEFINE_IREG_READ(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP) 119 DEFINE_IREG_READ(cca_ctrl, MCR20A_CCA_CTRL) 120 DEFINE_IREG_READ(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS) 121 DEFINE_IREG_READ(cca2_thresh, MCR20A_CCA2_THRESH) 122 DEFINE_IREG_READ(tmr_prescale, MCR20A_TMR_PRESCALE) 123 DEFINE_IREG_READ(rx_byte_count, MCR20A_RX_BYTE_COUNT) 124 DEFINE_IREG_READ(rx_wtr_mark, MCR20A_RX_WTR_MARK) 125 126 DEFINE_IREG_WRITE(part_id, MCR20A_PART_ID) 127 DEFINE_IREG_WRITE(rx_frame_filter, MCR20A_RX_FRAME_FILTER) 128 DEFINE_IREG_WRITE(cca1_thresh, MCR20A_CCA1_THRESH) 129 DEFINE_IREG_WRITE(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP) 130 DEFINE_IREG_WRITE(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP) 131 DEFINE_IREG_WRITE(cca_ctrl, MCR20A_CCA_CTRL) 132 DEFINE_IREG_WRITE(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS) 133 DEFINE_IREG_WRITE(cca2_thresh, MCR20A_CCA2_THRESH) 134 DEFINE_IREG_WRITE(tmr_prescale, MCR20A_TMR_PRESCALE) 135 DEFINE_IREG_WRITE(rx_byte_count, MCR20A_RX_BYTE_COUNT) 136 DEFINE_IREG_WRITE(rx_wtr_mark, MCR20A_RX_WTR_MARK) 137 138 #define DEFINE_BITS_SET(__reg_name, __reg_addr, __nibble) \ 139 static inline uint8_t set_bits_##__reg_name(uint8_t value) \ 140 { \ 141 value = (value << __reg_addr##__nibble##_SHIFT) & \ 142 __reg_addr##__nibble##_MASK; \ 143 return value; \ 144 } 145 146 DEFINE_BITS_SET(phy_ctrl1_xcvseq, MCR20A_PHY_CTRL1, _XCVSEQ) 147 DEFINE_BITS_SET(phy_ctrl4_ccatype, MCR20A_PHY_CTRL4, _CCATYPE) 148 DEFINE_BITS_SET(pll_int0_val, MCR20A_PLL_INT0, _VAL) 149 DEFINE_BITS_SET(pa_pwr_val, MCR20A_PA_PWR, _VAL) 150 DEFINE_BITS_SET(tmr_prescale, MCR20A_TMR_PRESCALE, _VAL) 151 DEFINE_BITS_SET(clk_out_div, MCR20A_CLK_OUT, _DIV) 152 153 #define DEFINE_BURST_WRITE(__reg_addr, __addr, __sz, __dreg) \ 154 static inline bool write_burst_##__reg_addr( \ 155 const struct device *dev, uint8_t *buf) \ 156 { \ 157 return z_mcr20a_write_burst(dev, __dreg, __addr, buf, __sz); \ 158 } 159 160 #define DEFINE_BURST_READ(__reg_addr, __addr, __sz, __dreg) \ 161 static inline bool read_burst_##__reg_addr(const struct device *dev, \ 162 uint8_t *buf) \ 163 { \ 164 return z_mcr20a_read_burst(dev, __dreg, __addr, buf, __sz); \ 165 } 166 167 DEFINE_BURST_WRITE(t1cmp, MCR20A_T1CMP_LSB, 3, true) 168 DEFINE_BURST_WRITE(t2cmp, MCR20A_T2CMP_LSB, 3, true) 169 DEFINE_BURST_WRITE(t3cmp, MCR20A_T3CMP_LSB, 3, true) 170 DEFINE_BURST_WRITE(t4cmp, MCR20A_T4CMP_LSB, 3, true) 171 DEFINE_BURST_WRITE(t2primecmp, MCR20A_T2PRIMECMP_LSB, 2, true) 172 DEFINE_BURST_WRITE(pll_int0, MCR20A_PLL_INT0, 3, true) 173 DEFINE_BURST_WRITE(irqsts1_irqsts3, MCR20A_IRQSTS1, 3, true) 174 DEFINE_BURST_WRITE(irqsts1_ctrl1, MCR20A_IRQSTS1, 4, true) 175 176 DEFINE_BURST_WRITE(pan_id, MCR20A_MACPANID0_LSB, 2, false) 177 DEFINE_BURST_WRITE(short_addr, MCR20A_MACSHORTADDRS0_LSB, 2, false) 178 DEFINE_BURST_WRITE(ext_addr, MCR20A_MACLONGADDRS0_0, 8, false) 179 180 DEFINE_BURST_READ(event_timer, MCR20A_EVENT_TIMER_LSB, 3, true) 181 DEFINE_BURST_READ(irqsts1_ctrl4, MCR20A_IRQSTS1, 8, true) 182 183 #endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_ */ 184
