1 /** 2 * @file i2s_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2S_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2S_I2S_REVA_REGS_H_ 27 #define LIBRARIES_PERIPHDRIVERS_SOURCE_I2S_I2S_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup i2s_reva 65 * @defgroup i2s_reva_registers I2S_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the I2S_REVA Peripheral Module. 67 * @details Inter-IC Sound Interface. 68 */ 69 70 /** 71 * @ingroup i2s_reva_registers 72 * Structure type to access the I2S_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl0ch0; /**< <tt>\b 0x00:</tt> I2S_REVA CTRL0CH0 Register */ 76 __R uint32_t rsv_0x4_0xf[3]; 77 __IO uint32_t ctrl1ch0; /**< <tt>\b 0x10:</tt> I2S_REVA CTRL1CH0 Register */ 78 __R uint32_t rsv_0x14_0x2f[7]; 79 __IO uint32_t dmach0; /**< <tt>\b 0x30:</tt> I2S_REVA DMACH0 Register */ 80 __R uint32_t rsv_0x34_0x3f[3]; 81 __IO uint32_t fifoch0; /**< <tt>\b 0x40:</tt> I2S_REVA FIFOCH0 Register */ 82 __R uint32_t rsv_0x44_0x4f[3]; 83 __IO uint32_t intfl; /**< <tt>\b 0x50:</tt> I2S_REVA INTFL Register */ 84 __IO uint32_t inten; /**< <tt>\b 0x54:</tt> I2S_REVA INTEN Register */ 85 __IO uint32_t extsetup; /**< <tt>\b 0x58:</tt> I2S_REVA EXTSETUP Register */ 86 } mxc_i2s_reva_regs_t; 87 88 /* Register offsets for module I2S_REVA */ 89 /** 90 * @ingroup i2s_reva_registers 91 * @defgroup I2S_REVA_Register_Offsets Register Offsets 92 * @brief I2S_REVA Peripheral Register Offsets from the I2S_REVA Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_I2S_REVA_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_I2S_REVA_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_I2S_REVA_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0030</tt> */ 98 #define MXC_R_I2S_REVA_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0040</tt> */ 99 #define MXC_R_I2S_REVA_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0050</tt> */ 100 #define MXC_R_I2S_REVA_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0054</tt> */ 101 #define MXC_R_I2S_REVA_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S_REVA Base Address: <tt> 0x0058</tt> */ 102 /**@} end of group i2s_reva_registers */ 103 104 /** 105 * @ingroup i2s_reva_registers 106 * @defgroup I2S_REVA_CTRL0CH0 I2S_REVA_CTRL0CH0 107 * @brief Global mode channel. 108 * @{ 109 */ 110 #define MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ 111 #define MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ 112 113 #define MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ 114 #define MXC_F_I2S_REVA_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ 115 116 #define MXC_F_I2S_REVA_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ 117 #define MXC_F_I2S_REVA_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ 118 119 #define MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ 120 #define MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ 121 122 #define MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ 123 #define MXC_F_I2S_REVA_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ 124 125 #define MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ 126 #define MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ 127 128 #define MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ 129 #define MXC_F_I2S_REVA_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ 130 131 #define MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ 132 #define MXC_F_I2S_REVA_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_REVA_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ 133 134 #define MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ 135 #define MXC_F_I2S_REVA_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ 136 137 #define MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ 138 #define MXC_F_I2S_REVA_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ 139 140 #define MXC_F_I2S_REVA_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ 141 #define MXC_F_I2S_REVA_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ 142 143 #define MXC_F_I2S_REVA_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ 144 #define MXC_F_I2S_REVA_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ 145 146 #define MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB_POS 19 /**< CTRL0CH0_FIFO_LSB Position */ 147 #define MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ 148 149 #define MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ 150 #define MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ 151 152 /**@} end of group I2S_REVA_CTRL0CH0_Register */ 153 154 /** 155 * @ingroup i2s_reva_registers 156 * @defgroup I2S_REVA_CTRL1CH0 I2S_REVA_CTRL1CH0 157 * @brief Local channel Setup. 158 * @{ 159 */ 160 #define MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ 161 #define MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ 162 163 #define MXC_F_I2S_REVA_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ 164 #define MXC_F_I2S_REVA_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ 165 166 #define MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ 167 #define MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ 168 169 #define MXC_F_I2S_REVA_CTRL1CH0_ADJUST_POS 15 /**< CTRL1CH0_ADJUST Position */ 170 #define MXC_F_I2S_REVA_CTRL1CH0_ADJUST ((uint32_t)(0x1UL << MXC_F_I2S_REVA_CTRL1CH0_ADJUST_POS)) /**< CTRL1CH0_ADJUST Mask */ 171 172 #define MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ 173 #define MXC_F_I2S_REVA_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_REVA_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ 174 175 /**@} end of group I2S_REVA_CTRL1CH0_Register */ 176 177 /** 178 * @ingroup i2s_reva_registers 179 * @defgroup I2S_REVA_DMACH0 I2S_REVA_DMACH0 180 * @brief DMA Control. 181 * @{ 182 */ 183 #define MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ 184 #define MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_REVA_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ 185 186 #define MXC_F_I2S_REVA_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ 187 #define MXC_F_I2S_REVA_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ 188 189 #define MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ 190 #define MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_REVA_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ 191 192 #define MXC_F_I2S_REVA_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ 193 #define MXC_F_I2S_REVA_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_REVA_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ 194 195 #define MXC_F_I2S_REVA_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ 196 #define MXC_F_I2S_REVA_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ 197 198 #define MXC_F_I2S_REVA_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ 199 #define MXC_F_I2S_REVA_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_REVA_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ 200 201 /**@} end of group I2S_REVA_DMACH0_Register */ 202 203 /** 204 * @ingroup i2s_reva_registers 205 * @defgroup I2S_REVA_FIFOCH0 I2S_REVA_FIFOCH0 206 * @brief I2S Fifo. 207 * @{ 208 */ 209 #define MXC_F_I2S_REVA_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ 210 #define MXC_F_I2S_REVA_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_REVA_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ 211 212 /**@} end of group I2S_REVA_FIFOCH0_Register */ 213 214 /** 215 * @ingroup i2s_reva_registers 216 * @defgroup I2S_REVA_INTFL I2S_REVA_INTFL 217 * @brief ISR Status. 218 * @{ 219 */ 220 #define MXC_F_I2S_REVA_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ 221 #define MXC_F_I2S_REVA_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ 222 223 #define MXC_F_I2S_REVA_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ 224 #define MXC_F_I2S_REVA_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ 225 226 #define MXC_F_I2S_REVA_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ 227 #define MXC_F_I2S_REVA_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ 228 229 #define MXC_F_I2S_REVA_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ 230 #define MXC_F_I2S_REVA_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ 231 232 /**@} end of group I2S_REVA_INTFL_Register */ 233 234 /** 235 * @ingroup i2s_reva_registers 236 * @defgroup I2S_REVA_INTEN I2S_REVA_INTEN 237 * @brief Interrupt Enable. 238 * @{ 239 */ 240 #define MXC_F_I2S_REVA_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ 241 #define MXC_F_I2S_REVA_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ 242 243 #define MXC_F_I2S_REVA_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ 244 #define MXC_F_I2S_REVA_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ 245 246 #define MXC_F_I2S_REVA_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ 247 #define MXC_F_I2S_REVA_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ 248 249 #define MXC_F_I2S_REVA_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ 250 #define MXC_F_I2S_REVA_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_REVA_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ 251 252 /**@} end of group I2S_REVA_INTEN_Register */ 253 254 /** 255 * @ingroup i2s_reva_registers 256 * @defgroup I2S_REVA_EXTSETUP I2S_REVA_EXTSETUP 257 * @brief Ext Control. 258 * @{ 259 */ 260 #define MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ 261 #define MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_REVA_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ 262 263 /**@} end of group I2S_REVA_EXTSETUP_Register */ 264 265 #ifdef __cplusplus 266 } 267 #endif 268 269 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2S_I2S_REVA_REGS_H_ 270 271
