1 // Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 
15 #pragma once
16 
17 #ifdef __cplusplus
18 extern "C" {
19 #endif
20 
21 // ESP32-S3 have 2 I2C.
22 #define SOC_I2C_NUM            (2)
23 
24 #define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
25 
26 //ESP32-S3 support hardware FSM reset
27 #define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
28 //ESP32-S3 support hardware clear bus
29 #define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
30 
31 #define SOC_I2C_SUPPORT_XTAL       (1)
32 #define SOC_I2C_SUPPORT_RTC        (1)
33 
34 #ifdef __cplusplus
35 }
36 #endif
37