1 /* 2 * Copyright (c) 2022 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #define DT_DRV_COMPAT nxp_imx_src_rev2 8 9 #include <soc.h> 10 #include <zephyr/drivers/hwinfo.h> 11 #include <string.h> 12 #include <zephyr/sys/byteorder.h> 13 #include <fsl_soc_src.h> 14 15 #ifdef CONFIG_CPU_CORTEX_M7 16 #define MCUX_RESET_PIN_FLAG kSRC_M7CoreIppUserResetFlag 17 #define MCUX_RESET_SOFTWARE_FLAG kSRC_M7CoreM7LockUpResetFlag 18 #define MCUX_RESET_POR_FLAG kSRC_M7CoreIppResetFlag 19 #define MCUX_RESET_WATCHDOG_FLAG (kSRC_M7CoreWdogResetFlag | \ 20 kSRC_M7CoreWdog3ResetFlag | \ 21 kSRC_M7CoreWdog4ResetFlag) 22 #define MCUX_RESET_DEBUG_FLAG kSRC_M7CoreJtagResetFlag 23 #define MCUX_RESET_SECURITY_FLAG kSRC_M7CoreCSUResetFlag 24 #define MCUX_RESET_TEMPERATURE_FLAG kSRC_M7CoreTempsenseResetFlag 25 #define MCUX_RESET_USER_FLAG kSRC_M7CoreM7RequestResetFlag 26 #elif defined(CONFIG_CPU_CORTEX_M4) 27 #define MCUX_RESET_PIN_FLAG kSRC_M4CoreIppUserResetFlag 28 #define MCUX_RESET_SOFTWARE_FLAG kSRC_M4CoreM7LockUpResetFlag 29 #define MCUX_RESET_POR_FLAG kSRC_M4CoreIppResetFlag 30 #define MCUX_RESET_WATCHDOG_FLAG (kSRC_M4CoreWdogResetFlag | \ 31 kSRC_M4CoreWdog3ResetFlag | \ 32 kSRC_M4CoreWdog4ResetFlag) 33 #define MCUX_RESET_DEBUG_FLAG kSRC_M4CoreJtagResetFlag 34 #define MCUX_RESET_SECURITY_FLAG kSRC_M4CoreCSUResetFlag 35 #define MCUX_RESET_TEMPERATURE_FLAG kSRC_M4CoreTempsenseResetFlag 36 #define MCUX_RESET_USER_FLAG kSRC_M4CoreM7RequestResetFlag 37 #else 38 /* The SOCs currently supported have an M7 or M4 core */ 39 #error "MCUX SRC driver not supported for this CPU!" 40 #endif 41 42 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compatible device found"); 43 z_impl_hwinfo_get_reset_cause(uint32_t * cause)44int z_impl_hwinfo_get_reset_cause(uint32_t *cause) 45 { 46 uint32_t flags = 0; 47 uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0)); 48 49 if (reason & (MCUX_RESET_PIN_FLAG)) { 50 flags |= RESET_PIN; 51 } 52 if (reason & (MCUX_RESET_SOFTWARE_FLAG)) { 53 flags |= RESET_SOFTWARE; 54 } 55 if (reason & (MCUX_RESET_POR_FLAG)) { 56 flags |= RESET_POR; 57 } 58 if (reason & (MCUX_RESET_WATCHDOG_FLAG)) { 59 flags |= RESET_WATCHDOG; 60 } 61 if (reason & (MCUX_RESET_DEBUG_FLAG)) { 62 flags |= RESET_DEBUG; 63 } 64 if (reason & (MCUX_RESET_SECURITY_FLAG)) { 65 flags |= RESET_SECURITY; 66 } 67 if (reason & (MCUX_RESET_TEMPERATURE_FLAG)) { 68 flags |= RESET_TEMPERATURE; 69 } 70 if (reason & (MCUX_RESET_USER_FLAG)) { 71 flags |= RESET_USER; 72 } 73 74 *cause = flags; 75 76 return 0; 77 } 78 z_impl_hwinfo_clear_reset_cause(void)79int z_impl_hwinfo_clear_reset_cause(void) 80 { 81 uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0)); 82 83 SRC_ClearGlobalSystemResetStatus((SRC_Type *)DT_INST_REG_ADDR(0), reason); 84 85 return 0; 86 } 87 z_impl_hwinfo_get_supported_reset_cause(uint32_t * supported)88int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported) 89 { 90 *supported = (RESET_WATCHDOG 91 | RESET_DEBUG 92 | RESET_TEMPERATURE 93 | RESET_PIN 94 | RESET_SOFTWARE 95 | RESET_POR 96 | RESET_SECURITY 97 | RESET_USER 98 ); 99 100 return 0; 101 } 102
