1 /**
2 * \file
3 *
4 * \brief SAM TC
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_TC_COMPONENT_
44 #ifndef _HRI_TC_L21_H_INCLUDED_
45 #define _HRI_TC_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_TC_CRITICAL_SECTIONS)
55 #define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define TC_CRITICAL_SECTION_ENTER()
59 #define TC_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint16_t hri_tc_cc16_reg_t;
63 typedef uint16_t hri_tc_ccbuf16_reg_t;
64 typedef uint16_t hri_tc_count16_reg_t;
65 typedef uint16_t hri_tc_evctrl_reg_t;
66 typedef uint32_t hri_tc_cc32_reg_t;
67 typedef uint32_t hri_tc_ccbuf32_reg_t;
68 typedef uint32_t hri_tc_count32_reg_t;
69 typedef uint32_t hri_tc_ctrla_reg_t;
70 typedef uint32_t hri_tc_syncbusy_reg_t;
71 typedef uint8_t hri_tc_cc8_reg_t;
72 typedef uint8_t hri_tc_ccbuf8_reg_t;
73 typedef uint8_t hri_tc_count8_reg_t;
74 typedef uint8_t hri_tc_ctrlbset_reg_t;
75 typedef uint8_t hri_tc_dbgctrl_reg_t;
76 typedef uint8_t hri_tc_drvctrl_reg_t;
77 typedef uint8_t hri_tc_intenset_reg_t;
78 typedef uint8_t hri_tc_intflag_reg_t;
79 typedef uint8_t hri_tc_per_reg_t;
80 typedef uint8_t hri_tc_perbuf_reg_t;
81 typedef uint8_t hri_tc_status_reg_t;
82 typedef uint8_t hri_tc_wave_reg_t;
83
hri_tc_wait_for_sync(const void * const hw,hri_tc_syncbusy_reg_t reg)84 static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg)
85 {
86 while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
87 };
88 }
89
hri_tc_is_syncing(const void * const hw,hri_tc_syncbusy_reg_t reg)90 static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg)
91 {
92 return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
93 }
94
hri_tccount16_set_COUNT_COUNT_bf(const void * const hw,hri_tc_count16_reg_t mask)95 static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask)
96 {
97 TC_CRITICAL_SECTION_ENTER();
98 ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask);
99 TC_CRITICAL_SECTION_LEAVE();
100 }
101
hri_tccount16_get_COUNT_COUNT_bf(const void * const hw,hri_tc_count16_reg_t mask)102 static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask)
103 {
104 uint16_t tmp;
105 tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
106 tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos;
107 return tmp;
108 }
109
hri_tccount16_write_COUNT_COUNT_bf(const void * const hw,hri_tc_count16_reg_t data)110 static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t data)
111 {
112 uint16_t tmp;
113 TC_CRITICAL_SECTION_ENTER();
114 tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
115 tmp &= ~TC_COUNT16_COUNT_COUNT_Msk;
116 tmp |= TC_COUNT16_COUNT_COUNT(data);
117 ((Tc *)hw)->COUNT16.COUNT.reg = tmp;
118 TC_CRITICAL_SECTION_LEAVE();
119 }
120
hri_tccount16_clear_COUNT_COUNT_bf(const void * const hw,hri_tc_count16_reg_t mask)121 static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask)
122 {
123 TC_CRITICAL_SECTION_ENTER();
124 ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask);
125 TC_CRITICAL_SECTION_LEAVE();
126 }
127
hri_tccount16_toggle_COUNT_COUNT_bf(const void * const hw,hri_tc_count16_reg_t mask)128 static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask)
129 {
130 TC_CRITICAL_SECTION_ENTER();
131 ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask);
132 TC_CRITICAL_SECTION_LEAVE();
133 }
134
hri_tccount16_read_COUNT_COUNT_bf(const void * const hw)135 static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw)
136 {
137 uint16_t tmp;
138 tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
139 tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos;
140 return tmp;
141 }
142
hri_tccount16_set_COUNT_reg(const void * const hw,hri_tc_count16_reg_t mask)143 static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask)
144 {
145 TC_CRITICAL_SECTION_ENTER();
146 ((Tc *)hw)->COUNT16.COUNT.reg |= mask;
147 TC_CRITICAL_SECTION_LEAVE();
148 }
149
hri_tccount16_get_COUNT_reg(const void * const hw,hri_tc_count16_reg_t mask)150 static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask)
151 {
152 uint16_t tmp;
153 tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
154 tmp &= mask;
155 return tmp;
156 }
157
hri_tccount16_write_COUNT_reg(const void * const hw,hri_tc_count16_reg_t data)158 static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tc_count16_reg_t data)
159 {
160 TC_CRITICAL_SECTION_ENTER();
161 ((Tc *)hw)->COUNT16.COUNT.reg = data;
162 TC_CRITICAL_SECTION_LEAVE();
163 }
164
hri_tccount16_clear_COUNT_reg(const void * const hw,hri_tc_count16_reg_t mask)165 static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask)
166 {
167 TC_CRITICAL_SECTION_ENTER();
168 ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask;
169 TC_CRITICAL_SECTION_LEAVE();
170 }
171
hri_tccount16_toggle_COUNT_reg(const void * const hw,hri_tc_count16_reg_t mask)172 static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask)
173 {
174 TC_CRITICAL_SECTION_ENTER();
175 ((Tc *)hw)->COUNT16.COUNT.reg ^= mask;
176 TC_CRITICAL_SECTION_LEAVE();
177 }
178
hri_tccount16_read_COUNT_reg(const void * const hw)179 static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_reg(const void *const hw)
180 {
181 return ((Tc *)hw)->COUNT16.COUNT.reg;
182 }
183
hri_tccount16_set_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc16_reg_t mask)184 static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
185 {
186 TC_CRITICAL_SECTION_ENTER();
187 ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask);
188 TC_CRITICAL_SECTION_LEAVE();
189 }
190
hri_tccount16_get_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc16_reg_t mask)191 static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
192 {
193 uint16_t tmp;
194 tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
195 tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos;
196 return tmp;
197 }
198
hri_tccount16_write_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc16_reg_t data)199 static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data)
200 {
201 uint16_t tmp;
202 TC_CRITICAL_SECTION_ENTER();
203 tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
204 tmp &= ~TC_COUNT16_CC_CC_Msk;
205 tmp |= TC_COUNT16_CC_CC(data);
206 ((Tc *)hw)->COUNT16.CC[index].reg = tmp;
207 TC_CRITICAL_SECTION_LEAVE();
208 }
209
hri_tccount16_clear_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc16_reg_t mask)210 static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
211 {
212 TC_CRITICAL_SECTION_ENTER();
213 ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask);
214 TC_CRITICAL_SECTION_LEAVE();
215 }
216
hri_tccount16_toggle_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc16_reg_t mask)217 static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
218 {
219 TC_CRITICAL_SECTION_ENTER();
220 ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask);
221 TC_CRITICAL_SECTION_LEAVE();
222 }
223
hri_tccount16_read_CC_CC_bf(const void * const hw,uint8_t index)224 static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index)
225 {
226 uint16_t tmp;
227 tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
228 tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos;
229 return tmp;
230 }
231
hri_tccount16_set_CC_reg(const void * const hw,uint8_t index,hri_tc_cc16_reg_t mask)232 static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
233 {
234 TC_CRITICAL_SECTION_ENTER();
235 ((Tc *)hw)->COUNT16.CC[index].reg |= mask;
236 TC_CRITICAL_SECTION_LEAVE();
237 }
238
hri_tccount16_get_CC_reg(const void * const hw,uint8_t index,hri_tc_cc16_reg_t mask)239 static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
240 {
241 uint16_t tmp;
242 tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
243 tmp &= mask;
244 return tmp;
245 }
246
hri_tccount16_write_CC_reg(const void * const hw,uint8_t index,hri_tc_cc16_reg_t data)247 static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data)
248 {
249 TC_CRITICAL_SECTION_ENTER();
250 ((Tc *)hw)->COUNT16.CC[index].reg = data;
251 TC_CRITICAL_SECTION_LEAVE();
252 }
253
hri_tccount16_clear_CC_reg(const void * const hw,uint8_t index,hri_tc_cc16_reg_t mask)254 static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
255 {
256 TC_CRITICAL_SECTION_ENTER();
257 ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask;
258 TC_CRITICAL_SECTION_LEAVE();
259 }
260
hri_tccount16_toggle_CC_reg(const void * const hw,uint8_t index,hri_tc_cc16_reg_t mask)261 static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask)
262 {
263 TC_CRITICAL_SECTION_ENTER();
264 ((Tc *)hw)->COUNT16.CC[index].reg ^= mask;
265 TC_CRITICAL_SECTION_LEAVE();
266 }
267
hri_tccount16_read_CC_reg(const void * const hw,uint8_t index)268 static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index)
269 {
270 return ((Tc *)hw)->COUNT16.CC[index].reg;
271 }
272
hri_tccount16_set_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t mask)273 static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask)
274 {
275 TC_CRITICAL_SECTION_ENTER();
276 ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask);
277 TC_CRITICAL_SECTION_LEAVE();
278 }
279
hri_tccount16_get_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t mask)280 static inline hri_tc_ccbuf16_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
281 hri_tc_ccbuf16_reg_t mask)
282 {
283 uint16_t tmp;
284 tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
285 tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos;
286 return tmp;
287 }
288
hri_tccount16_write_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t data)289 static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t data)
290 {
291 uint16_t tmp;
292 TC_CRITICAL_SECTION_ENTER();
293 tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
294 tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk;
295 tmp |= TC_COUNT16_CCBUF_CCBUF(data);
296 ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp;
297 TC_CRITICAL_SECTION_LEAVE();
298 }
299
hri_tccount16_clear_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t mask)300 static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask)
301 {
302 TC_CRITICAL_SECTION_ENTER();
303 ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask);
304 TC_CRITICAL_SECTION_LEAVE();
305 }
306
hri_tccount16_toggle_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t mask)307 static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask)
308 {
309 TC_CRITICAL_SECTION_ENTER();
310 ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask);
311 TC_CRITICAL_SECTION_LEAVE();
312 }
313
hri_tccount16_read_CCBUF_CCBUF_bf(const void * const hw,uint8_t index)314 static inline hri_tc_ccbuf16_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
315 {
316 uint16_t tmp;
317 tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
318 tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos;
319 return tmp;
320 }
321
hri_tccount16_set_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t mask)322 static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask)
323 {
324 TC_CRITICAL_SECTION_ENTER();
325 ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask;
326 TC_CRITICAL_SECTION_LEAVE();
327 }
328
hri_tccount16_get_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t mask)329 static inline hri_tc_ccbuf16_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index,
330 hri_tc_ccbuf16_reg_t mask)
331 {
332 uint16_t tmp;
333 tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
334 tmp &= mask;
335 return tmp;
336 }
337
hri_tccount16_write_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t data)338 static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t data)
339 {
340 TC_CRITICAL_SECTION_ENTER();
341 ((Tc *)hw)->COUNT16.CCBUF[index].reg = data;
342 TC_CRITICAL_SECTION_LEAVE();
343 }
344
hri_tccount16_clear_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t mask)345 static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask)
346 {
347 TC_CRITICAL_SECTION_ENTER();
348 ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask;
349 TC_CRITICAL_SECTION_LEAVE();
350 }
351
hri_tccount16_toggle_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf16_reg_t mask)352 static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask)
353 {
354 TC_CRITICAL_SECTION_ENTER();
355 ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask;
356 TC_CRITICAL_SECTION_LEAVE();
357 }
358
hri_tccount16_read_CCBUF_reg(const void * const hw,uint8_t index)359 static inline hri_tc_ccbuf16_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index)
360 {
361 return ((Tc *)hw)->COUNT16.CCBUF[index].reg;
362 }
363
hri_tccount32_set_COUNT_COUNT_bf(const void * const hw,hri_tc_count32_reg_t mask)364 static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask)
365 {
366 TC_CRITICAL_SECTION_ENTER();
367 ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask);
368 TC_CRITICAL_SECTION_LEAVE();
369 }
370
hri_tccount32_get_COUNT_COUNT_bf(const void * const hw,hri_tc_count32_reg_t mask)371 static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask)
372 {
373 uint32_t tmp;
374 tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
375 tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos;
376 return tmp;
377 }
378
hri_tccount32_write_COUNT_COUNT_bf(const void * const hw,hri_tc_count32_reg_t data)379 static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t data)
380 {
381 uint32_t tmp;
382 TC_CRITICAL_SECTION_ENTER();
383 tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
384 tmp &= ~TC_COUNT32_COUNT_COUNT_Msk;
385 tmp |= TC_COUNT32_COUNT_COUNT(data);
386 ((Tc *)hw)->COUNT32.COUNT.reg = tmp;
387 TC_CRITICAL_SECTION_LEAVE();
388 }
389
hri_tccount32_clear_COUNT_COUNT_bf(const void * const hw,hri_tc_count32_reg_t mask)390 static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask)
391 {
392 TC_CRITICAL_SECTION_ENTER();
393 ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask);
394 TC_CRITICAL_SECTION_LEAVE();
395 }
396
hri_tccount32_toggle_COUNT_COUNT_bf(const void * const hw,hri_tc_count32_reg_t mask)397 static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask)
398 {
399 TC_CRITICAL_SECTION_ENTER();
400 ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask);
401 TC_CRITICAL_SECTION_LEAVE();
402 }
403
hri_tccount32_read_COUNT_COUNT_bf(const void * const hw)404 static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw)
405 {
406 uint32_t tmp;
407 tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
408 tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos;
409 return tmp;
410 }
411
hri_tccount32_set_COUNT_reg(const void * const hw,hri_tc_count32_reg_t mask)412 static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask)
413 {
414 TC_CRITICAL_SECTION_ENTER();
415 ((Tc *)hw)->COUNT32.COUNT.reg |= mask;
416 TC_CRITICAL_SECTION_LEAVE();
417 }
418
hri_tccount32_get_COUNT_reg(const void * const hw,hri_tc_count32_reg_t mask)419 static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask)
420 {
421 uint32_t tmp;
422 tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
423 tmp &= mask;
424 return tmp;
425 }
426
hri_tccount32_write_COUNT_reg(const void * const hw,hri_tc_count32_reg_t data)427 static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tc_count32_reg_t data)
428 {
429 TC_CRITICAL_SECTION_ENTER();
430 ((Tc *)hw)->COUNT32.COUNT.reg = data;
431 TC_CRITICAL_SECTION_LEAVE();
432 }
433
hri_tccount32_clear_COUNT_reg(const void * const hw,hri_tc_count32_reg_t mask)434 static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask)
435 {
436 TC_CRITICAL_SECTION_ENTER();
437 ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask;
438 TC_CRITICAL_SECTION_LEAVE();
439 }
440
hri_tccount32_toggle_COUNT_reg(const void * const hw,hri_tc_count32_reg_t mask)441 static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask)
442 {
443 TC_CRITICAL_SECTION_ENTER();
444 ((Tc *)hw)->COUNT32.COUNT.reg ^= mask;
445 TC_CRITICAL_SECTION_LEAVE();
446 }
447
hri_tccount32_read_COUNT_reg(const void * const hw)448 static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_reg(const void *const hw)
449 {
450 return ((Tc *)hw)->COUNT32.COUNT.reg;
451 }
452
hri_tccount32_set_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc32_reg_t mask)453 static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
454 {
455 TC_CRITICAL_SECTION_ENTER();
456 ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask);
457 TC_CRITICAL_SECTION_LEAVE();
458 }
459
hri_tccount32_get_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc32_reg_t mask)460 static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
461 {
462 uint32_t tmp;
463 tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
464 tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos;
465 return tmp;
466 }
467
hri_tccount32_write_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc32_reg_t data)468 static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data)
469 {
470 uint32_t tmp;
471 TC_CRITICAL_SECTION_ENTER();
472 tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
473 tmp &= ~TC_COUNT32_CC_CC_Msk;
474 tmp |= TC_COUNT32_CC_CC(data);
475 ((Tc *)hw)->COUNT32.CC[index].reg = tmp;
476 TC_CRITICAL_SECTION_LEAVE();
477 }
478
hri_tccount32_clear_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc32_reg_t mask)479 static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
480 {
481 TC_CRITICAL_SECTION_ENTER();
482 ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask);
483 TC_CRITICAL_SECTION_LEAVE();
484 }
485
hri_tccount32_toggle_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc32_reg_t mask)486 static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
487 {
488 TC_CRITICAL_SECTION_ENTER();
489 ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask);
490 TC_CRITICAL_SECTION_LEAVE();
491 }
492
hri_tccount32_read_CC_CC_bf(const void * const hw,uint8_t index)493 static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index)
494 {
495 uint32_t tmp;
496 tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
497 tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos;
498 return tmp;
499 }
500
hri_tccount32_set_CC_reg(const void * const hw,uint8_t index,hri_tc_cc32_reg_t mask)501 static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
502 {
503 TC_CRITICAL_SECTION_ENTER();
504 ((Tc *)hw)->COUNT32.CC[index].reg |= mask;
505 TC_CRITICAL_SECTION_LEAVE();
506 }
507
hri_tccount32_get_CC_reg(const void * const hw,uint8_t index,hri_tc_cc32_reg_t mask)508 static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
509 {
510 uint32_t tmp;
511 tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
512 tmp &= mask;
513 return tmp;
514 }
515
hri_tccount32_write_CC_reg(const void * const hw,uint8_t index,hri_tc_cc32_reg_t data)516 static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data)
517 {
518 TC_CRITICAL_SECTION_ENTER();
519 ((Tc *)hw)->COUNT32.CC[index].reg = data;
520 TC_CRITICAL_SECTION_LEAVE();
521 }
522
hri_tccount32_clear_CC_reg(const void * const hw,uint8_t index,hri_tc_cc32_reg_t mask)523 static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
524 {
525 TC_CRITICAL_SECTION_ENTER();
526 ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask;
527 TC_CRITICAL_SECTION_LEAVE();
528 }
529
hri_tccount32_toggle_CC_reg(const void * const hw,uint8_t index,hri_tc_cc32_reg_t mask)530 static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask)
531 {
532 TC_CRITICAL_SECTION_ENTER();
533 ((Tc *)hw)->COUNT32.CC[index].reg ^= mask;
534 TC_CRITICAL_SECTION_LEAVE();
535 }
536
hri_tccount32_read_CC_reg(const void * const hw,uint8_t index)537 static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
538 {
539 return ((Tc *)hw)->COUNT32.CC[index].reg;
540 }
541
hri_tccount32_set_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t mask)542 static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask)
543 {
544 TC_CRITICAL_SECTION_ENTER();
545 ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask);
546 TC_CRITICAL_SECTION_LEAVE();
547 }
548
hri_tccount32_get_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t mask)549 static inline hri_tc_ccbuf32_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
550 hri_tc_ccbuf32_reg_t mask)
551 {
552 uint32_t tmp;
553 tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
554 tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos;
555 return tmp;
556 }
557
hri_tccount32_write_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t data)558 static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t data)
559 {
560 uint32_t tmp;
561 TC_CRITICAL_SECTION_ENTER();
562 tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
563 tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk;
564 tmp |= TC_COUNT32_CCBUF_CCBUF(data);
565 ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp;
566 TC_CRITICAL_SECTION_LEAVE();
567 }
568
hri_tccount32_clear_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t mask)569 static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask)
570 {
571 TC_CRITICAL_SECTION_ENTER();
572 ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask);
573 TC_CRITICAL_SECTION_LEAVE();
574 }
575
hri_tccount32_toggle_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t mask)576 static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask)
577 {
578 TC_CRITICAL_SECTION_ENTER();
579 ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask);
580 TC_CRITICAL_SECTION_LEAVE();
581 }
582
hri_tccount32_read_CCBUF_CCBUF_bf(const void * const hw,uint8_t index)583 static inline hri_tc_ccbuf32_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
584 {
585 uint32_t tmp;
586 tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
587 tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos;
588 return tmp;
589 }
590
hri_tccount32_set_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t mask)591 static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask)
592 {
593 TC_CRITICAL_SECTION_ENTER();
594 ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask;
595 TC_CRITICAL_SECTION_LEAVE();
596 }
597
hri_tccount32_get_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t mask)598 static inline hri_tc_ccbuf32_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index,
599 hri_tc_ccbuf32_reg_t mask)
600 {
601 uint32_t tmp;
602 tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
603 tmp &= mask;
604 return tmp;
605 }
606
hri_tccount32_write_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t data)607 static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t data)
608 {
609 TC_CRITICAL_SECTION_ENTER();
610 ((Tc *)hw)->COUNT32.CCBUF[index].reg = data;
611 TC_CRITICAL_SECTION_LEAVE();
612 }
613
hri_tccount32_clear_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t mask)614 static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask)
615 {
616 TC_CRITICAL_SECTION_ENTER();
617 ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask;
618 TC_CRITICAL_SECTION_LEAVE();
619 }
620
hri_tccount32_toggle_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf32_reg_t mask)621 static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask)
622 {
623 TC_CRITICAL_SECTION_ENTER();
624 ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask;
625 TC_CRITICAL_SECTION_LEAVE();
626 }
627
hri_tccount32_read_CCBUF_reg(const void * const hw,uint8_t index)628 static inline hri_tc_ccbuf32_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index)
629 {
630 return ((Tc *)hw)->COUNT32.CCBUF[index].reg;
631 }
632
hri_tc_set_CTRLB_DIR_bit(const void * const hw)633 static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw)
634 {
635 ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR;
636 }
637
hri_tc_get_CTRLB_DIR_bit(const void * const hw)638 static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw)
639 {
640 return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos;
641 }
642
hri_tc_write_CTRLB_DIR_bit(const void * const hw,bool value)643 static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value)
644 {
645 if (value == 0x0) {
646 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR;
647 } else {
648 ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR;
649 }
650 }
651
hri_tc_clear_CTRLB_DIR_bit(const void * const hw)652 static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw)
653 {
654 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR;
655 }
656
hri_tc_set_CTRLB_LUPD_bit(const void * const hw)657 static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw)
658 {
659 ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_LUPD;
660 }
661
hri_tc_get_CTRLB_LUPD_bit(const void * const hw)662 static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw)
663 {
664 return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos;
665 }
666
hri_tc_write_CTRLB_LUPD_bit(const void * const hw,bool value)667 static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
668 {
669 if (value == 0x0) {
670 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
671 } else {
672 ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_LUPD;
673 }
674 }
675
hri_tc_clear_CTRLB_LUPD_bit(const void * const hw)676 static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw)
677 {
678 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
679 }
680
hri_tc_set_CTRLB_ONESHOT_bit(const void * const hw)681 static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw)
682 {
683 ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
684 }
685
hri_tc_get_CTRLB_ONESHOT_bit(const void * const hw)686 static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw)
687 {
688 return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos;
689 }
690
hri_tc_write_CTRLB_ONESHOT_bit(const void * const hw,bool value)691 static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
692 {
693 if (value == 0x0) {
694 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
695 } else {
696 ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
697 }
698 }
699
hri_tc_clear_CTRLB_ONESHOT_bit(const void * const hw)700 static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw)
701 {
702 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
703 }
704
hri_tc_set_CTRLB_CMD_bf(const void * const hw,hri_tc_ctrlbset_reg_t mask)705 static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
706 {
707 ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(mask);
708 }
709
hri_tc_get_CTRLB_CMD_bf(const void * const hw,hri_tc_ctrlbset_reg_t mask)710 static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
711 {
712 uint8_t tmp;
713 tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg;
714 tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos;
715 return tmp;
716 }
717
hri_tc_read_CTRLB_CMD_bf(const void * const hw)718 static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw)
719 {
720 uint8_t tmp;
721 tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg;
722 tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos;
723 return tmp;
724 }
725
hri_tc_write_CTRLB_CMD_bf(const void * const hw,hri_tc_ctrlbset_reg_t data)726 static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data)
727 {
728 ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(data);
729 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data);
730 }
731
hri_tc_clear_CTRLB_CMD_bf(const void * const hw,hri_tc_ctrlbset_reg_t mask)732 static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
733 {
734 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask);
735 }
736
hri_tc_set_CTRLB_reg(const void * const hw,hri_tc_ctrlbset_reg_t mask)737 static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
738 {
739 ((Tc *)hw)->COUNT8.CTRLBSET.reg = mask;
740 }
741
hri_tc_get_CTRLB_reg(const void * const hw,hri_tc_ctrlbset_reg_t mask)742 static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
743 {
744 uint8_t tmp;
745 tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg;
746 tmp &= mask;
747 return tmp;
748 }
749
hri_tc_read_CTRLB_reg(const void * const hw)750 static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw)
751 {
752 return ((Tc *)hw)->COUNT8.CTRLBSET.reg;
753 }
754
hri_tc_write_CTRLB_reg(const void * const hw,hri_tc_ctrlbset_reg_t data)755 static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data)
756 {
757 ((Tc *)hw)->COUNT8.CTRLBSET.reg = data;
758 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~data;
759 }
760
hri_tc_clear_CTRLB_reg(const void * const hw,hri_tc_ctrlbset_reg_t mask)761 static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
762 {
763 ((Tc *)hw)->COUNT8.CTRLBCLR.reg = mask;
764 }
765
hri_tc_set_INTEN_OVF_bit(const void * const hw)766 static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw)
767 {
768 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF;
769 }
770
hri_tc_get_INTEN_OVF_bit(const void * const hw)771 static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw)
772 {
773 return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos;
774 }
775
hri_tc_write_INTEN_OVF_bit(const void * const hw,bool value)776 static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value)
777 {
778 if (value == 0x0) {
779 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF;
780 } else {
781 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF;
782 }
783 }
784
hri_tc_clear_INTEN_OVF_bit(const void * const hw)785 static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw)
786 {
787 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF;
788 }
789
hri_tc_set_INTEN_ERR_bit(const void * const hw)790 static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw)
791 {
792 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR;
793 }
794
hri_tc_get_INTEN_ERR_bit(const void * const hw)795 static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw)
796 {
797 return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos;
798 }
799
hri_tc_write_INTEN_ERR_bit(const void * const hw,bool value)800 static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value)
801 {
802 if (value == 0x0) {
803 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR;
804 } else {
805 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR;
806 }
807 }
808
hri_tc_clear_INTEN_ERR_bit(const void * const hw)809 static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw)
810 {
811 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR;
812 }
813
hri_tc_set_INTEN_MC0_bit(const void * const hw)814 static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw)
815 {
816 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0;
817 }
818
hri_tc_get_INTEN_MC0_bit(const void * const hw)819 static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw)
820 {
821 return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos;
822 }
823
hri_tc_write_INTEN_MC0_bit(const void * const hw,bool value)824 static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value)
825 {
826 if (value == 0x0) {
827 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0;
828 } else {
829 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0;
830 }
831 }
832
hri_tc_clear_INTEN_MC0_bit(const void * const hw)833 static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw)
834 {
835 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0;
836 }
837
hri_tc_set_INTEN_MC1_bit(const void * const hw)838 static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw)
839 {
840 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1;
841 }
842
hri_tc_get_INTEN_MC1_bit(const void * const hw)843 static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw)
844 {
845 return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos;
846 }
847
hri_tc_write_INTEN_MC1_bit(const void * const hw,bool value)848 static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value)
849 {
850 if (value == 0x0) {
851 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1;
852 } else {
853 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1;
854 }
855 }
856
hri_tc_clear_INTEN_MC1_bit(const void * const hw)857 static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw)
858 {
859 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1;
860 }
861
hri_tc_set_INTEN_reg(const void * const hw,hri_tc_intenset_reg_t mask)862 static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
863 {
864 ((Tc *)hw)->COUNT8.INTENSET.reg = mask;
865 }
866
hri_tc_get_INTEN_reg(const void * const hw,hri_tc_intenset_reg_t mask)867 static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
868 {
869 uint8_t tmp;
870 tmp = ((Tc *)hw)->COUNT8.INTENSET.reg;
871 tmp &= mask;
872 return tmp;
873 }
874
hri_tc_read_INTEN_reg(const void * const hw)875 static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw)
876 {
877 return ((Tc *)hw)->COUNT8.INTENSET.reg;
878 }
879
hri_tc_write_INTEN_reg(const void * const hw,hri_tc_intenset_reg_t data)880 static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data)
881 {
882 ((Tc *)hw)->COUNT8.INTENSET.reg = data;
883 ((Tc *)hw)->COUNT8.INTENCLR.reg = ~data;
884 }
885
hri_tc_clear_INTEN_reg(const void * const hw,hri_tc_intenset_reg_t mask)886 static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
887 {
888 ((Tc *)hw)->COUNT8.INTENCLR.reg = mask;
889 }
890
hri_tc_get_INTFLAG_OVF_bit(const void * const hw)891 static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw)
892 {
893 return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
894 }
895
hri_tc_clear_INTFLAG_OVF_bit(const void * const hw)896 static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw)
897 {
898 ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF;
899 }
900
hri_tc_get_INTFLAG_ERR_bit(const void * const hw)901 static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw)
902 {
903 return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
904 }
905
hri_tc_clear_INTFLAG_ERR_bit(const void * const hw)906 static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw)
907 {
908 ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR;
909 }
910
hri_tc_get_INTFLAG_MC0_bit(const void * const hw)911 static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw)
912 {
913 return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
914 }
915
hri_tc_clear_INTFLAG_MC0_bit(const void * const hw)916 static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw)
917 {
918 ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0;
919 }
920
hri_tc_get_INTFLAG_MC1_bit(const void * const hw)921 static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw)
922 {
923 return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
924 }
925
hri_tc_clear_INTFLAG_MC1_bit(const void * const hw)926 static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw)
927 {
928 ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1;
929 }
930
hri_tc_get_interrupt_OVF_bit(const void * const hw)931 static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw)
932 {
933 return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
934 }
935
hri_tc_clear_interrupt_OVF_bit(const void * const hw)936 static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw)
937 {
938 ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF;
939 }
940
hri_tc_get_interrupt_ERR_bit(const void * const hw)941 static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw)
942 {
943 return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
944 }
945
hri_tc_clear_interrupt_ERR_bit(const void * const hw)946 static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw)
947 {
948 ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR;
949 }
950
hri_tc_get_interrupt_MC0_bit(const void * const hw)951 static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw)
952 {
953 return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
954 }
955
hri_tc_clear_interrupt_MC0_bit(const void * const hw)956 static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw)
957 {
958 ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0;
959 }
960
hri_tc_get_interrupt_MC1_bit(const void * const hw)961 static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw)
962 {
963 return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
964 }
965
hri_tc_clear_interrupt_MC1_bit(const void * const hw)966 static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw)
967 {
968 ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1;
969 }
970
hri_tc_get_INTFLAG_reg(const void * const hw,hri_tc_intflag_reg_t mask)971 static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
972 {
973 uint8_t tmp;
974 tmp = ((Tc *)hw)->COUNT8.INTFLAG.reg;
975 tmp &= mask;
976 return tmp;
977 }
978
hri_tc_read_INTFLAG_reg(const void * const hw)979 static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw)
980 {
981 return ((Tc *)hw)->COUNT8.INTFLAG.reg;
982 }
983
hri_tc_clear_INTFLAG_reg(const void * const hw,hri_tc_intflag_reg_t mask)984 static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
985 {
986 ((Tc *)hw)->COUNT8.INTFLAG.reg = mask;
987 }
988
hri_tc_set_CTRLA_SWRST_bit(const void * const hw)989 static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw)
990 {
991 TC_CRITICAL_SECTION_ENTER();
992 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
993 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_SWRST;
994 TC_CRITICAL_SECTION_LEAVE();
995 }
996
hri_tc_get_CTRLA_SWRST_bit(const void * const hw)997 static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw)
998 {
999 uint32_t tmp;
1000 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
1001 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1002 tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos;
1003 return (bool)tmp;
1004 }
1005
hri_tc_set_CTRLA_ENABLE_bit(const void * const hw)1006 static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw)
1007 {
1008 TC_CRITICAL_SECTION_ENTER();
1009 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
1010 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ENABLE;
1011 TC_CRITICAL_SECTION_LEAVE();
1012 }
1013
hri_tc_get_CTRLA_ENABLE_bit(const void * const hw)1014 static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw)
1015 {
1016 uint32_t tmp;
1017 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
1018 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1019 tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos;
1020 return (bool)tmp;
1021 }
1022
hri_tc_write_CTRLA_ENABLE_bit(const void * const hw,bool value)1023 static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
1024 {
1025 uint32_t tmp;
1026 TC_CRITICAL_SECTION_ENTER();
1027 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
1028 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1029 tmp &= ~TC_CTRLA_ENABLE;
1030 tmp |= value << TC_CTRLA_ENABLE_Pos;
1031 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1032 TC_CRITICAL_SECTION_LEAVE();
1033 }
1034
hri_tc_clear_CTRLA_ENABLE_bit(const void * const hw)1035 static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw)
1036 {
1037 TC_CRITICAL_SECTION_ENTER();
1038 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
1039 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ENABLE;
1040 TC_CRITICAL_SECTION_LEAVE();
1041 }
1042
hri_tc_toggle_CTRLA_ENABLE_bit(const void * const hw)1043 static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw)
1044 {
1045 TC_CRITICAL_SECTION_ENTER();
1046 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
1047 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ENABLE;
1048 TC_CRITICAL_SECTION_LEAVE();
1049 }
1050
hri_tc_set_CTRLA_RUNSTDBY_bit(const void * const hw)1051 static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
1052 {
1053 TC_CRITICAL_SECTION_ENTER();
1054 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1055 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_RUNSTDBY;
1056 TC_CRITICAL_SECTION_LEAVE();
1057 }
1058
hri_tc_get_CTRLA_RUNSTDBY_bit(const void * const hw)1059 static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
1060 {
1061 uint32_t tmp;
1062 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1063 tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos;
1064 return (bool)tmp;
1065 }
1066
hri_tc_write_CTRLA_RUNSTDBY_bit(const void * const hw,bool value)1067 static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
1068 {
1069 uint32_t tmp;
1070 TC_CRITICAL_SECTION_ENTER();
1071 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1072 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1073 tmp &= ~TC_CTRLA_RUNSTDBY;
1074 tmp |= value << TC_CTRLA_RUNSTDBY_Pos;
1075 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1076 TC_CRITICAL_SECTION_LEAVE();
1077 }
1078
hri_tc_clear_CTRLA_RUNSTDBY_bit(const void * const hw)1079 static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
1080 {
1081 TC_CRITICAL_SECTION_ENTER();
1082 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1083 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY;
1084 TC_CRITICAL_SECTION_LEAVE();
1085 }
1086
hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void * const hw)1087 static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
1088 {
1089 TC_CRITICAL_SECTION_ENTER();
1090 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1091 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_RUNSTDBY;
1092 TC_CRITICAL_SECTION_LEAVE();
1093 }
1094
hri_tc_set_CTRLA_ONDEMAND_bit(const void * const hw)1095 static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw)
1096 {
1097 TC_CRITICAL_SECTION_ENTER();
1098 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1099 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ONDEMAND;
1100 TC_CRITICAL_SECTION_LEAVE();
1101 }
1102
hri_tc_get_CTRLA_ONDEMAND_bit(const void * const hw)1103 static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw)
1104 {
1105 uint32_t tmp;
1106 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1107 tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos;
1108 return (bool)tmp;
1109 }
1110
hri_tc_write_CTRLA_ONDEMAND_bit(const void * const hw,bool value)1111 static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
1112 {
1113 uint32_t tmp;
1114 TC_CRITICAL_SECTION_ENTER();
1115 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1116 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1117 tmp &= ~TC_CTRLA_ONDEMAND;
1118 tmp |= value << TC_CTRLA_ONDEMAND_Pos;
1119 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1120 TC_CRITICAL_SECTION_LEAVE();
1121 }
1122
hri_tc_clear_CTRLA_ONDEMAND_bit(const void * const hw)1123 static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
1124 {
1125 TC_CRITICAL_SECTION_ENTER();
1126 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1127 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ONDEMAND;
1128 TC_CRITICAL_SECTION_LEAVE();
1129 }
1130
hri_tc_toggle_CTRLA_ONDEMAND_bit(const void * const hw)1131 static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
1132 {
1133 TC_CRITICAL_SECTION_ENTER();
1134 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1135 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ONDEMAND;
1136 TC_CRITICAL_SECTION_LEAVE();
1137 }
1138
hri_tc_set_CTRLA_ALOCK_bit(const void * const hw)1139 static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw)
1140 {
1141 TC_CRITICAL_SECTION_ENTER();
1142 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1143 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ALOCK;
1144 TC_CRITICAL_SECTION_LEAVE();
1145 }
1146
hri_tc_get_CTRLA_ALOCK_bit(const void * const hw)1147 static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw)
1148 {
1149 uint32_t tmp;
1150 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1151 tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos;
1152 return (bool)tmp;
1153 }
1154
hri_tc_write_CTRLA_ALOCK_bit(const void * const hw,bool value)1155 static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
1156 {
1157 uint32_t tmp;
1158 TC_CRITICAL_SECTION_ENTER();
1159 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1160 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1161 tmp &= ~TC_CTRLA_ALOCK;
1162 tmp |= value << TC_CTRLA_ALOCK_Pos;
1163 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1164 TC_CRITICAL_SECTION_LEAVE();
1165 }
1166
hri_tc_clear_CTRLA_ALOCK_bit(const void * const hw)1167 static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw)
1168 {
1169 TC_CRITICAL_SECTION_ENTER();
1170 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1171 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ALOCK;
1172 TC_CRITICAL_SECTION_LEAVE();
1173 }
1174
hri_tc_toggle_CTRLA_ALOCK_bit(const void * const hw)1175 static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw)
1176 {
1177 TC_CRITICAL_SECTION_ENTER();
1178 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1179 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ALOCK;
1180 TC_CRITICAL_SECTION_LEAVE();
1181 }
1182
hri_tc_set_CTRLA_CAPTEN0_bit(const void * const hw)1183 static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw)
1184 {
1185 TC_CRITICAL_SECTION_ENTER();
1186 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1187 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTEN0;
1188 TC_CRITICAL_SECTION_LEAVE();
1189 }
1190
hri_tc_get_CTRLA_CAPTEN0_bit(const void * const hw)1191 static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw)
1192 {
1193 uint32_t tmp;
1194 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1195 tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos;
1196 return (bool)tmp;
1197 }
1198
hri_tc_write_CTRLA_CAPTEN0_bit(const void * const hw,bool value)1199 static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value)
1200 {
1201 uint32_t tmp;
1202 TC_CRITICAL_SECTION_ENTER();
1203 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1204 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1205 tmp &= ~TC_CTRLA_CAPTEN0;
1206 tmp |= value << TC_CTRLA_CAPTEN0_Pos;
1207 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1208 TC_CRITICAL_SECTION_LEAVE();
1209 }
1210
hri_tc_clear_CTRLA_CAPTEN0_bit(const void * const hw)1211 static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw)
1212 {
1213 TC_CRITICAL_SECTION_ENTER();
1214 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1215 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTEN0;
1216 TC_CRITICAL_SECTION_LEAVE();
1217 }
1218
hri_tc_toggle_CTRLA_CAPTEN0_bit(const void * const hw)1219 static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw)
1220 {
1221 TC_CRITICAL_SECTION_ENTER();
1222 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1223 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTEN0;
1224 TC_CRITICAL_SECTION_LEAVE();
1225 }
1226
hri_tc_set_CTRLA_CAPTEN1_bit(const void * const hw)1227 static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw)
1228 {
1229 TC_CRITICAL_SECTION_ENTER();
1230 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1231 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTEN1;
1232 TC_CRITICAL_SECTION_LEAVE();
1233 }
1234
hri_tc_get_CTRLA_CAPTEN1_bit(const void * const hw)1235 static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw)
1236 {
1237 uint32_t tmp;
1238 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1239 tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos;
1240 return (bool)tmp;
1241 }
1242
hri_tc_write_CTRLA_CAPTEN1_bit(const void * const hw,bool value)1243 static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value)
1244 {
1245 uint32_t tmp;
1246 TC_CRITICAL_SECTION_ENTER();
1247 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1248 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1249 tmp &= ~TC_CTRLA_CAPTEN1;
1250 tmp |= value << TC_CTRLA_CAPTEN1_Pos;
1251 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1252 TC_CRITICAL_SECTION_LEAVE();
1253 }
1254
hri_tc_clear_CTRLA_CAPTEN1_bit(const void * const hw)1255 static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw)
1256 {
1257 TC_CRITICAL_SECTION_ENTER();
1258 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1259 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTEN1;
1260 TC_CRITICAL_SECTION_LEAVE();
1261 }
1262
hri_tc_toggle_CTRLA_CAPTEN1_bit(const void * const hw)1263 static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw)
1264 {
1265 TC_CRITICAL_SECTION_ENTER();
1266 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1267 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTEN1;
1268 TC_CRITICAL_SECTION_LEAVE();
1269 }
1270
hri_tc_set_CTRLA_COPEN0_bit(const void * const hw)1271 static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw)
1272 {
1273 TC_CRITICAL_SECTION_ENTER();
1274 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1275 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_COPEN0;
1276 TC_CRITICAL_SECTION_LEAVE();
1277 }
1278
hri_tc_get_CTRLA_COPEN0_bit(const void * const hw)1279 static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw)
1280 {
1281 uint32_t tmp;
1282 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1283 tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos;
1284 return (bool)tmp;
1285 }
1286
hri_tc_write_CTRLA_COPEN0_bit(const void * const hw,bool value)1287 static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value)
1288 {
1289 uint32_t tmp;
1290 TC_CRITICAL_SECTION_ENTER();
1291 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1292 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1293 tmp &= ~TC_CTRLA_COPEN0;
1294 tmp |= value << TC_CTRLA_COPEN0_Pos;
1295 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1296 TC_CRITICAL_SECTION_LEAVE();
1297 }
1298
hri_tc_clear_CTRLA_COPEN0_bit(const void * const hw)1299 static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw)
1300 {
1301 TC_CRITICAL_SECTION_ENTER();
1302 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1303 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_COPEN0;
1304 TC_CRITICAL_SECTION_LEAVE();
1305 }
1306
hri_tc_toggle_CTRLA_COPEN0_bit(const void * const hw)1307 static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw)
1308 {
1309 TC_CRITICAL_SECTION_ENTER();
1310 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1311 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_COPEN0;
1312 TC_CRITICAL_SECTION_LEAVE();
1313 }
1314
hri_tc_set_CTRLA_COPEN1_bit(const void * const hw)1315 static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw)
1316 {
1317 TC_CRITICAL_SECTION_ENTER();
1318 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1319 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_COPEN1;
1320 TC_CRITICAL_SECTION_LEAVE();
1321 }
1322
hri_tc_get_CTRLA_COPEN1_bit(const void * const hw)1323 static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw)
1324 {
1325 uint32_t tmp;
1326 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1327 tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos;
1328 return (bool)tmp;
1329 }
1330
hri_tc_write_CTRLA_COPEN1_bit(const void * const hw,bool value)1331 static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value)
1332 {
1333 uint32_t tmp;
1334 TC_CRITICAL_SECTION_ENTER();
1335 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1336 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1337 tmp &= ~TC_CTRLA_COPEN1;
1338 tmp |= value << TC_CTRLA_COPEN1_Pos;
1339 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1340 TC_CRITICAL_SECTION_LEAVE();
1341 }
1342
hri_tc_clear_CTRLA_COPEN1_bit(const void * const hw)1343 static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw)
1344 {
1345 TC_CRITICAL_SECTION_ENTER();
1346 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1347 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_COPEN1;
1348 TC_CRITICAL_SECTION_LEAVE();
1349 }
1350
hri_tc_toggle_CTRLA_COPEN1_bit(const void * const hw)1351 static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw)
1352 {
1353 TC_CRITICAL_SECTION_ENTER();
1354 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1355 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_COPEN1;
1356 TC_CRITICAL_SECTION_LEAVE();
1357 }
1358
hri_tc_set_CTRLA_MODE_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1359 static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1360 {
1361 TC_CRITICAL_SECTION_ENTER();
1362 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1363 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_MODE(mask);
1364 TC_CRITICAL_SECTION_LEAVE();
1365 }
1366
hri_tc_get_CTRLA_MODE_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1367 static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1368 {
1369 uint32_t tmp;
1370 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1371 tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos;
1372 return tmp;
1373 }
1374
hri_tc_write_CTRLA_MODE_bf(const void * const hw,hri_tc_ctrla_reg_t data)1375 static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data)
1376 {
1377 uint32_t tmp;
1378 TC_CRITICAL_SECTION_ENTER();
1379 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1380 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1381 tmp &= ~TC_CTRLA_MODE_Msk;
1382 tmp |= TC_CTRLA_MODE(data);
1383 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1384 TC_CRITICAL_SECTION_LEAVE();
1385 }
1386
hri_tc_clear_CTRLA_MODE_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1387 static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1388 {
1389 TC_CRITICAL_SECTION_ENTER();
1390 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1391 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_MODE(mask);
1392 TC_CRITICAL_SECTION_LEAVE();
1393 }
1394
hri_tc_toggle_CTRLA_MODE_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1395 static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1396 {
1397 TC_CRITICAL_SECTION_ENTER();
1398 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1399 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_MODE(mask);
1400 TC_CRITICAL_SECTION_LEAVE();
1401 }
1402
hri_tc_read_CTRLA_MODE_bf(const void * const hw)1403 static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw)
1404 {
1405 uint32_t tmp;
1406 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1407 tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos;
1408 return tmp;
1409 }
1410
hri_tc_set_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1411 static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1412 {
1413 TC_CRITICAL_SECTION_ENTER();
1414 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1415 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask);
1416 TC_CRITICAL_SECTION_LEAVE();
1417 }
1418
hri_tc_get_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1419 static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1420 {
1421 uint32_t tmp;
1422 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1423 tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos;
1424 return tmp;
1425 }
1426
hri_tc_write_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tc_ctrla_reg_t data)1427 static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data)
1428 {
1429 uint32_t tmp;
1430 TC_CRITICAL_SECTION_ENTER();
1431 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1432 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1433 tmp &= ~TC_CTRLA_PRESCSYNC_Msk;
1434 tmp |= TC_CTRLA_PRESCSYNC(data);
1435 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1436 TC_CRITICAL_SECTION_LEAVE();
1437 }
1438
hri_tc_clear_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1439 static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1440 {
1441 TC_CRITICAL_SECTION_ENTER();
1442 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1443 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask);
1444 TC_CRITICAL_SECTION_LEAVE();
1445 }
1446
hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1447 static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1448 {
1449 TC_CRITICAL_SECTION_ENTER();
1450 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1451 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask);
1452 TC_CRITICAL_SECTION_LEAVE();
1453 }
1454
hri_tc_read_CTRLA_PRESCSYNC_bf(const void * const hw)1455 static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
1456 {
1457 uint32_t tmp;
1458 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1459 tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos;
1460 return tmp;
1461 }
1462
hri_tc_set_CTRLA_PRESCALER_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1463 static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1464 {
1465 TC_CRITICAL_SECTION_ENTER();
1466 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1467 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCALER(mask);
1468 TC_CRITICAL_SECTION_LEAVE();
1469 }
1470
hri_tc_get_CTRLA_PRESCALER_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1471 static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1472 {
1473 uint32_t tmp;
1474 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1475 tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos;
1476 return tmp;
1477 }
1478
hri_tc_write_CTRLA_PRESCALER_bf(const void * const hw,hri_tc_ctrla_reg_t data)1479 static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data)
1480 {
1481 uint32_t tmp;
1482 TC_CRITICAL_SECTION_ENTER();
1483 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1484 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1485 tmp &= ~TC_CTRLA_PRESCALER_Msk;
1486 tmp |= TC_CTRLA_PRESCALER(data);
1487 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp;
1488 TC_CRITICAL_SECTION_LEAVE();
1489 }
1490
hri_tc_clear_CTRLA_PRESCALER_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1491 static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1492 {
1493 TC_CRITICAL_SECTION_ENTER();
1494 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1495 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask);
1496 TC_CRITICAL_SECTION_LEAVE();
1497 }
1498
hri_tc_toggle_CTRLA_PRESCALER_bf(const void * const hw,hri_tc_ctrla_reg_t mask)1499 static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
1500 {
1501 TC_CRITICAL_SECTION_ENTER();
1502 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
1503 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask);
1504 TC_CRITICAL_SECTION_LEAVE();
1505 }
1506
hri_tc_read_CTRLA_PRESCALER_bf(const void * const hw)1507 static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw)
1508 {
1509 uint32_t tmp;
1510 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1511 tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos;
1512 return tmp;
1513 }
1514
hri_tc_set_CTRLA_reg(const void * const hw,hri_tc_ctrla_reg_t mask)1515 static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
1516 {
1517 TC_CRITICAL_SECTION_ENTER();
1518 ((Tc *)hw)->COUNT8.CTRLA.reg |= mask;
1519 TC_CRITICAL_SECTION_LEAVE();
1520 }
1521
hri_tc_get_CTRLA_reg(const void * const hw,hri_tc_ctrla_reg_t mask)1522 static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
1523 {
1524 uint32_t tmp;
1525 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg;
1526 tmp &= mask;
1527 return tmp;
1528 }
1529
hri_tc_write_CTRLA_reg(const void * const hw,hri_tc_ctrla_reg_t data)1530 static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data)
1531 {
1532 TC_CRITICAL_SECTION_ENTER();
1533 ((Tc *)hw)->COUNT8.CTRLA.reg = data;
1534 TC_CRITICAL_SECTION_LEAVE();
1535 }
1536
hri_tc_clear_CTRLA_reg(const void * const hw,hri_tc_ctrla_reg_t mask)1537 static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
1538 {
1539 TC_CRITICAL_SECTION_ENTER();
1540 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~mask;
1541 TC_CRITICAL_SECTION_LEAVE();
1542 }
1543
hri_tc_toggle_CTRLA_reg(const void * const hw,hri_tc_ctrla_reg_t mask)1544 static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
1545 {
1546 TC_CRITICAL_SECTION_ENTER();
1547 ((Tc *)hw)->COUNT8.CTRLA.reg ^= mask;
1548 TC_CRITICAL_SECTION_LEAVE();
1549 }
1550
hri_tc_read_CTRLA_reg(const void * const hw)1551 static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw)
1552 {
1553 return ((Tc *)hw)->COUNT8.CTRLA.reg;
1554 }
1555
hri_tc_set_EVCTRL_TCINV_bit(const void * const hw)1556 static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw)
1557 {
1558 TC_CRITICAL_SECTION_ENTER();
1559 ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCINV;
1560 TC_CRITICAL_SECTION_LEAVE();
1561 }
1562
hri_tc_get_EVCTRL_TCINV_bit(const void * const hw)1563 static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw)
1564 {
1565 uint16_t tmp;
1566 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1567 tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos;
1568 return (bool)tmp;
1569 }
1570
hri_tc_write_EVCTRL_TCINV_bit(const void * const hw,bool value)1571 static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value)
1572 {
1573 uint16_t tmp;
1574 TC_CRITICAL_SECTION_ENTER();
1575 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1576 tmp &= ~TC_EVCTRL_TCINV;
1577 tmp |= value << TC_EVCTRL_TCINV_Pos;
1578 ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
1579 TC_CRITICAL_SECTION_LEAVE();
1580 }
1581
hri_tc_clear_EVCTRL_TCINV_bit(const void * const hw)1582 static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw)
1583 {
1584 TC_CRITICAL_SECTION_ENTER();
1585 ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCINV;
1586 TC_CRITICAL_SECTION_LEAVE();
1587 }
1588
hri_tc_toggle_EVCTRL_TCINV_bit(const void * const hw)1589 static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw)
1590 {
1591 TC_CRITICAL_SECTION_ENTER();
1592 ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCINV;
1593 TC_CRITICAL_SECTION_LEAVE();
1594 }
1595
hri_tc_set_EVCTRL_TCEI_bit(const void * const hw)1596 static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw)
1597 {
1598 TC_CRITICAL_SECTION_ENTER();
1599 ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCEI;
1600 TC_CRITICAL_SECTION_LEAVE();
1601 }
1602
hri_tc_get_EVCTRL_TCEI_bit(const void * const hw)1603 static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw)
1604 {
1605 uint16_t tmp;
1606 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1607 tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos;
1608 return (bool)tmp;
1609 }
1610
hri_tc_write_EVCTRL_TCEI_bit(const void * const hw,bool value)1611 static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value)
1612 {
1613 uint16_t tmp;
1614 TC_CRITICAL_SECTION_ENTER();
1615 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1616 tmp &= ~TC_EVCTRL_TCEI;
1617 tmp |= value << TC_EVCTRL_TCEI_Pos;
1618 ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
1619 TC_CRITICAL_SECTION_LEAVE();
1620 }
1621
hri_tc_clear_EVCTRL_TCEI_bit(const void * const hw)1622 static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw)
1623 {
1624 TC_CRITICAL_SECTION_ENTER();
1625 ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCEI;
1626 TC_CRITICAL_SECTION_LEAVE();
1627 }
1628
hri_tc_toggle_EVCTRL_TCEI_bit(const void * const hw)1629 static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw)
1630 {
1631 TC_CRITICAL_SECTION_ENTER();
1632 ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCEI;
1633 TC_CRITICAL_SECTION_LEAVE();
1634 }
1635
hri_tc_set_EVCTRL_OVFEO_bit(const void * const hw)1636 static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw)
1637 {
1638 TC_CRITICAL_SECTION_ENTER();
1639 ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_OVFEO;
1640 TC_CRITICAL_SECTION_LEAVE();
1641 }
1642
hri_tc_get_EVCTRL_OVFEO_bit(const void * const hw)1643 static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw)
1644 {
1645 uint16_t tmp;
1646 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1647 tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos;
1648 return (bool)tmp;
1649 }
1650
hri_tc_write_EVCTRL_OVFEO_bit(const void * const hw,bool value)1651 static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
1652 {
1653 uint16_t tmp;
1654 TC_CRITICAL_SECTION_ENTER();
1655 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1656 tmp &= ~TC_EVCTRL_OVFEO;
1657 tmp |= value << TC_EVCTRL_OVFEO_Pos;
1658 ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
1659 TC_CRITICAL_SECTION_LEAVE();
1660 }
1661
hri_tc_clear_EVCTRL_OVFEO_bit(const void * const hw)1662 static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw)
1663 {
1664 TC_CRITICAL_SECTION_ENTER();
1665 ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_OVFEO;
1666 TC_CRITICAL_SECTION_LEAVE();
1667 }
1668
hri_tc_toggle_EVCTRL_OVFEO_bit(const void * const hw)1669 static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
1670 {
1671 TC_CRITICAL_SECTION_ENTER();
1672 ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_OVFEO;
1673 TC_CRITICAL_SECTION_LEAVE();
1674 }
1675
hri_tc_set_EVCTRL_MCEO0_bit(const void * const hw)1676 static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw)
1677 {
1678 TC_CRITICAL_SECTION_ENTER();
1679 ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO0;
1680 TC_CRITICAL_SECTION_LEAVE();
1681 }
1682
hri_tc_get_EVCTRL_MCEO0_bit(const void * const hw)1683 static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw)
1684 {
1685 uint16_t tmp;
1686 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1687 tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos;
1688 return (bool)tmp;
1689 }
1690
hri_tc_write_EVCTRL_MCEO0_bit(const void * const hw,bool value)1691 static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
1692 {
1693 uint16_t tmp;
1694 TC_CRITICAL_SECTION_ENTER();
1695 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1696 tmp &= ~TC_EVCTRL_MCEO0;
1697 tmp |= value << TC_EVCTRL_MCEO0_Pos;
1698 ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
1699 TC_CRITICAL_SECTION_LEAVE();
1700 }
1701
hri_tc_clear_EVCTRL_MCEO0_bit(const void * const hw)1702 static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw)
1703 {
1704 TC_CRITICAL_SECTION_ENTER();
1705 ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO0;
1706 TC_CRITICAL_SECTION_LEAVE();
1707 }
1708
hri_tc_toggle_EVCTRL_MCEO0_bit(const void * const hw)1709 static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
1710 {
1711 TC_CRITICAL_SECTION_ENTER();
1712 ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO0;
1713 TC_CRITICAL_SECTION_LEAVE();
1714 }
1715
hri_tc_set_EVCTRL_MCEO1_bit(const void * const hw)1716 static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw)
1717 {
1718 TC_CRITICAL_SECTION_ENTER();
1719 ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO1;
1720 TC_CRITICAL_SECTION_LEAVE();
1721 }
1722
hri_tc_get_EVCTRL_MCEO1_bit(const void * const hw)1723 static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw)
1724 {
1725 uint16_t tmp;
1726 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1727 tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos;
1728 return (bool)tmp;
1729 }
1730
hri_tc_write_EVCTRL_MCEO1_bit(const void * const hw,bool value)1731 static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
1732 {
1733 uint16_t tmp;
1734 TC_CRITICAL_SECTION_ENTER();
1735 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1736 tmp &= ~TC_EVCTRL_MCEO1;
1737 tmp |= value << TC_EVCTRL_MCEO1_Pos;
1738 ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
1739 TC_CRITICAL_SECTION_LEAVE();
1740 }
1741
hri_tc_clear_EVCTRL_MCEO1_bit(const void * const hw)1742 static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw)
1743 {
1744 TC_CRITICAL_SECTION_ENTER();
1745 ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO1;
1746 TC_CRITICAL_SECTION_LEAVE();
1747 }
1748
hri_tc_toggle_EVCTRL_MCEO1_bit(const void * const hw)1749 static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
1750 {
1751 TC_CRITICAL_SECTION_ENTER();
1752 ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO1;
1753 TC_CRITICAL_SECTION_LEAVE();
1754 }
1755
hri_tc_set_EVCTRL_EVACT_bf(const void * const hw,hri_tc_evctrl_reg_t mask)1756 static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
1757 {
1758 TC_CRITICAL_SECTION_ENTER();
1759 ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_EVACT(mask);
1760 TC_CRITICAL_SECTION_LEAVE();
1761 }
1762
hri_tc_get_EVCTRL_EVACT_bf(const void * const hw,hri_tc_evctrl_reg_t mask)1763 static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
1764 {
1765 uint16_t tmp;
1766 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1767 tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos;
1768 return tmp;
1769 }
1770
hri_tc_write_EVCTRL_EVACT_bf(const void * const hw,hri_tc_evctrl_reg_t data)1771 static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data)
1772 {
1773 uint16_t tmp;
1774 TC_CRITICAL_SECTION_ENTER();
1775 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1776 tmp &= ~TC_EVCTRL_EVACT_Msk;
1777 tmp |= TC_EVCTRL_EVACT(data);
1778 ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp;
1779 TC_CRITICAL_SECTION_LEAVE();
1780 }
1781
hri_tc_clear_EVCTRL_EVACT_bf(const void * const hw,hri_tc_evctrl_reg_t mask)1782 static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
1783 {
1784 TC_CRITICAL_SECTION_ENTER();
1785 ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask);
1786 TC_CRITICAL_SECTION_LEAVE();
1787 }
1788
hri_tc_toggle_EVCTRL_EVACT_bf(const void * const hw,hri_tc_evctrl_reg_t mask)1789 static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
1790 {
1791 TC_CRITICAL_SECTION_ENTER();
1792 ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask);
1793 TC_CRITICAL_SECTION_LEAVE();
1794 }
1795
hri_tc_read_EVCTRL_EVACT_bf(const void * const hw)1796 static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw)
1797 {
1798 uint16_t tmp;
1799 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1800 tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos;
1801 return tmp;
1802 }
1803
hri_tc_set_EVCTRL_reg(const void * const hw,hri_tc_evctrl_reg_t mask)1804 static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
1805 {
1806 TC_CRITICAL_SECTION_ENTER();
1807 ((Tc *)hw)->COUNT8.EVCTRL.reg |= mask;
1808 TC_CRITICAL_SECTION_LEAVE();
1809 }
1810
hri_tc_get_EVCTRL_reg(const void * const hw,hri_tc_evctrl_reg_t mask)1811 static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
1812 {
1813 uint16_t tmp;
1814 tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg;
1815 tmp &= mask;
1816 return tmp;
1817 }
1818
hri_tc_write_EVCTRL_reg(const void * const hw,hri_tc_evctrl_reg_t data)1819 static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data)
1820 {
1821 TC_CRITICAL_SECTION_ENTER();
1822 ((Tc *)hw)->COUNT8.EVCTRL.reg = data;
1823 TC_CRITICAL_SECTION_LEAVE();
1824 }
1825
hri_tc_clear_EVCTRL_reg(const void * const hw,hri_tc_evctrl_reg_t mask)1826 static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
1827 {
1828 TC_CRITICAL_SECTION_ENTER();
1829 ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~mask;
1830 TC_CRITICAL_SECTION_LEAVE();
1831 }
1832
hri_tc_toggle_EVCTRL_reg(const void * const hw,hri_tc_evctrl_reg_t mask)1833 static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
1834 {
1835 TC_CRITICAL_SECTION_ENTER();
1836 ((Tc *)hw)->COUNT8.EVCTRL.reg ^= mask;
1837 TC_CRITICAL_SECTION_LEAVE();
1838 }
1839
hri_tc_read_EVCTRL_reg(const void * const hw)1840 static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw)
1841 {
1842 return ((Tc *)hw)->COUNT8.EVCTRL.reg;
1843 }
1844
hri_tc_set_WAVE_WAVEGEN_bf(const void * const hw,hri_tc_wave_reg_t mask)1845 static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
1846 {
1847 TC_CRITICAL_SECTION_ENTER();
1848 ((Tc *)hw)->COUNT8.WAVE.reg |= TC_WAVE_WAVEGEN(mask);
1849 TC_CRITICAL_SECTION_LEAVE();
1850 }
1851
hri_tc_get_WAVE_WAVEGEN_bf(const void * const hw,hri_tc_wave_reg_t mask)1852 static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
1853 {
1854 uint8_t tmp;
1855 tmp = ((Tc *)hw)->COUNT8.WAVE.reg;
1856 tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos;
1857 return tmp;
1858 }
1859
hri_tc_write_WAVE_WAVEGEN_bf(const void * const hw,hri_tc_wave_reg_t data)1860 static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data)
1861 {
1862 uint8_t tmp;
1863 TC_CRITICAL_SECTION_ENTER();
1864 tmp = ((Tc *)hw)->COUNT8.WAVE.reg;
1865 tmp &= ~TC_WAVE_WAVEGEN_Msk;
1866 tmp |= TC_WAVE_WAVEGEN(data);
1867 ((Tc *)hw)->COUNT8.WAVE.reg = tmp;
1868 TC_CRITICAL_SECTION_LEAVE();
1869 }
1870
hri_tc_clear_WAVE_WAVEGEN_bf(const void * const hw,hri_tc_wave_reg_t mask)1871 static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
1872 {
1873 TC_CRITICAL_SECTION_ENTER();
1874 ((Tc *)hw)->COUNT8.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask);
1875 TC_CRITICAL_SECTION_LEAVE();
1876 }
1877
hri_tc_toggle_WAVE_WAVEGEN_bf(const void * const hw,hri_tc_wave_reg_t mask)1878 static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
1879 {
1880 TC_CRITICAL_SECTION_ENTER();
1881 ((Tc *)hw)->COUNT8.WAVE.reg ^= TC_WAVE_WAVEGEN(mask);
1882 TC_CRITICAL_SECTION_LEAVE();
1883 }
1884
hri_tc_read_WAVE_WAVEGEN_bf(const void * const hw)1885 static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw)
1886 {
1887 uint8_t tmp;
1888 tmp = ((Tc *)hw)->COUNT8.WAVE.reg;
1889 tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos;
1890 return tmp;
1891 }
1892
hri_tc_set_WAVE_reg(const void * const hw,hri_tc_wave_reg_t mask)1893 static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
1894 {
1895 TC_CRITICAL_SECTION_ENTER();
1896 ((Tc *)hw)->COUNT8.WAVE.reg |= mask;
1897 TC_CRITICAL_SECTION_LEAVE();
1898 }
1899
hri_tc_get_WAVE_reg(const void * const hw,hri_tc_wave_reg_t mask)1900 static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
1901 {
1902 uint8_t tmp;
1903 tmp = ((Tc *)hw)->COUNT8.WAVE.reg;
1904 tmp &= mask;
1905 return tmp;
1906 }
1907
hri_tc_write_WAVE_reg(const void * const hw,hri_tc_wave_reg_t data)1908 static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data)
1909 {
1910 TC_CRITICAL_SECTION_ENTER();
1911 ((Tc *)hw)->COUNT8.WAVE.reg = data;
1912 TC_CRITICAL_SECTION_LEAVE();
1913 }
1914
hri_tc_clear_WAVE_reg(const void * const hw,hri_tc_wave_reg_t mask)1915 static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
1916 {
1917 TC_CRITICAL_SECTION_ENTER();
1918 ((Tc *)hw)->COUNT8.WAVE.reg &= ~mask;
1919 TC_CRITICAL_SECTION_LEAVE();
1920 }
1921
hri_tc_toggle_WAVE_reg(const void * const hw,hri_tc_wave_reg_t mask)1922 static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
1923 {
1924 TC_CRITICAL_SECTION_ENTER();
1925 ((Tc *)hw)->COUNT8.WAVE.reg ^= mask;
1926 TC_CRITICAL_SECTION_LEAVE();
1927 }
1928
hri_tc_read_WAVE_reg(const void * const hw)1929 static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw)
1930 {
1931 return ((Tc *)hw)->COUNT8.WAVE.reg;
1932 }
1933
hri_tc_set_DRVCTRL_INVEN0_bit(const void * const hw)1934 static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw)
1935 {
1936 TC_CRITICAL_SECTION_ENTER();
1937 ((Tc *)hw)->COUNT8.DRVCTRL.reg |= TC_DRVCTRL_INVEN0;
1938 TC_CRITICAL_SECTION_LEAVE();
1939 }
1940
hri_tc_get_DRVCTRL_INVEN0_bit(const void * const hw)1941 static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw)
1942 {
1943 uint8_t tmp;
1944 tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg;
1945 tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos;
1946 return (bool)tmp;
1947 }
1948
hri_tc_write_DRVCTRL_INVEN0_bit(const void * const hw,bool value)1949 static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
1950 {
1951 uint8_t tmp;
1952 TC_CRITICAL_SECTION_ENTER();
1953 tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg;
1954 tmp &= ~TC_DRVCTRL_INVEN0;
1955 tmp |= value << TC_DRVCTRL_INVEN0_Pos;
1956 ((Tc *)hw)->COUNT8.DRVCTRL.reg = tmp;
1957 TC_CRITICAL_SECTION_LEAVE();
1958 }
1959
hri_tc_clear_DRVCTRL_INVEN0_bit(const void * const hw)1960 static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
1961 {
1962 TC_CRITICAL_SECTION_ENTER();
1963 ((Tc *)hw)->COUNT8.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0;
1964 TC_CRITICAL_SECTION_LEAVE();
1965 }
1966
hri_tc_toggle_DRVCTRL_INVEN0_bit(const void * const hw)1967 static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
1968 {
1969 TC_CRITICAL_SECTION_ENTER();
1970 ((Tc *)hw)->COUNT8.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0;
1971 TC_CRITICAL_SECTION_LEAVE();
1972 }
1973
hri_tc_set_DRVCTRL_INVEN1_bit(const void * const hw)1974 static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw)
1975 {
1976 TC_CRITICAL_SECTION_ENTER();
1977 ((Tc *)hw)->COUNT8.DRVCTRL.reg |= TC_DRVCTRL_INVEN1;
1978 TC_CRITICAL_SECTION_LEAVE();
1979 }
1980
hri_tc_get_DRVCTRL_INVEN1_bit(const void * const hw)1981 static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw)
1982 {
1983 uint8_t tmp;
1984 tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg;
1985 tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos;
1986 return (bool)tmp;
1987 }
1988
hri_tc_write_DRVCTRL_INVEN1_bit(const void * const hw,bool value)1989 static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
1990 {
1991 uint8_t tmp;
1992 TC_CRITICAL_SECTION_ENTER();
1993 tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg;
1994 tmp &= ~TC_DRVCTRL_INVEN1;
1995 tmp |= value << TC_DRVCTRL_INVEN1_Pos;
1996 ((Tc *)hw)->COUNT8.DRVCTRL.reg = tmp;
1997 TC_CRITICAL_SECTION_LEAVE();
1998 }
1999
hri_tc_clear_DRVCTRL_INVEN1_bit(const void * const hw)2000 static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
2001 {
2002 TC_CRITICAL_SECTION_ENTER();
2003 ((Tc *)hw)->COUNT8.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1;
2004 TC_CRITICAL_SECTION_LEAVE();
2005 }
2006
hri_tc_toggle_DRVCTRL_INVEN1_bit(const void * const hw)2007 static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
2008 {
2009 TC_CRITICAL_SECTION_ENTER();
2010 ((Tc *)hw)->COUNT8.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1;
2011 TC_CRITICAL_SECTION_LEAVE();
2012 }
2013
hri_tc_set_DRVCTRL_reg(const void * const hw,hri_tc_drvctrl_reg_t mask)2014 static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
2015 {
2016 TC_CRITICAL_SECTION_ENTER();
2017 ((Tc *)hw)->COUNT8.DRVCTRL.reg |= mask;
2018 TC_CRITICAL_SECTION_LEAVE();
2019 }
2020
hri_tc_get_DRVCTRL_reg(const void * const hw,hri_tc_drvctrl_reg_t mask)2021 static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
2022 {
2023 uint8_t tmp;
2024 tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg;
2025 tmp &= mask;
2026 return tmp;
2027 }
2028
hri_tc_write_DRVCTRL_reg(const void * const hw,hri_tc_drvctrl_reg_t data)2029 static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data)
2030 {
2031 TC_CRITICAL_SECTION_ENTER();
2032 ((Tc *)hw)->COUNT8.DRVCTRL.reg = data;
2033 TC_CRITICAL_SECTION_LEAVE();
2034 }
2035
hri_tc_clear_DRVCTRL_reg(const void * const hw,hri_tc_drvctrl_reg_t mask)2036 static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
2037 {
2038 TC_CRITICAL_SECTION_ENTER();
2039 ((Tc *)hw)->COUNT8.DRVCTRL.reg &= ~mask;
2040 TC_CRITICAL_SECTION_LEAVE();
2041 }
2042
hri_tc_toggle_DRVCTRL_reg(const void * const hw,hri_tc_drvctrl_reg_t mask)2043 static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
2044 {
2045 TC_CRITICAL_SECTION_ENTER();
2046 ((Tc *)hw)->COUNT8.DRVCTRL.reg ^= mask;
2047 TC_CRITICAL_SECTION_LEAVE();
2048 }
2049
hri_tc_read_DRVCTRL_reg(const void * const hw)2050 static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw)
2051 {
2052 return ((Tc *)hw)->COUNT8.DRVCTRL.reg;
2053 }
2054
hri_tc_set_DBGCTRL_DBGRUN_bit(const void * const hw)2055 static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
2056 {
2057 TC_CRITICAL_SECTION_ENTER();
2058 ((Tc *)hw)->COUNT8.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN;
2059 TC_CRITICAL_SECTION_LEAVE();
2060 }
2061
hri_tc_get_DBGCTRL_DBGRUN_bit(const void * const hw)2062 static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
2063 {
2064 uint8_t tmp;
2065 tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg;
2066 tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos;
2067 return (bool)tmp;
2068 }
2069
hri_tc_write_DBGCTRL_DBGRUN_bit(const void * const hw,bool value)2070 static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
2071 {
2072 uint8_t tmp;
2073 TC_CRITICAL_SECTION_ENTER();
2074 tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg;
2075 tmp &= ~TC_DBGCTRL_DBGRUN;
2076 tmp |= value << TC_DBGCTRL_DBGRUN_Pos;
2077 ((Tc *)hw)->COUNT8.DBGCTRL.reg = tmp;
2078 TC_CRITICAL_SECTION_LEAVE();
2079 }
2080
hri_tc_clear_DBGCTRL_DBGRUN_bit(const void * const hw)2081 static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
2082 {
2083 TC_CRITICAL_SECTION_ENTER();
2084 ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN;
2085 TC_CRITICAL_SECTION_LEAVE();
2086 }
2087
hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void * const hw)2088 static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
2089 {
2090 TC_CRITICAL_SECTION_ENTER();
2091 ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN;
2092 TC_CRITICAL_SECTION_LEAVE();
2093 }
2094
hri_tc_set_DBGCTRL_reg(const void * const hw,hri_tc_dbgctrl_reg_t mask)2095 static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
2096 {
2097 TC_CRITICAL_SECTION_ENTER();
2098 ((Tc *)hw)->COUNT8.DBGCTRL.reg |= mask;
2099 TC_CRITICAL_SECTION_LEAVE();
2100 }
2101
hri_tc_get_DBGCTRL_reg(const void * const hw,hri_tc_dbgctrl_reg_t mask)2102 static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
2103 {
2104 uint8_t tmp;
2105 tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg;
2106 tmp &= mask;
2107 return tmp;
2108 }
2109
hri_tc_write_DBGCTRL_reg(const void * const hw,hri_tc_dbgctrl_reg_t data)2110 static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data)
2111 {
2112 TC_CRITICAL_SECTION_ENTER();
2113 ((Tc *)hw)->COUNT8.DBGCTRL.reg = data;
2114 TC_CRITICAL_SECTION_LEAVE();
2115 }
2116
hri_tc_clear_DBGCTRL_reg(const void * const hw,hri_tc_dbgctrl_reg_t mask)2117 static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
2118 {
2119 TC_CRITICAL_SECTION_ENTER();
2120 ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~mask;
2121 TC_CRITICAL_SECTION_LEAVE();
2122 }
2123
hri_tc_toggle_DBGCTRL_reg(const void * const hw,hri_tc_dbgctrl_reg_t mask)2124 static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
2125 {
2126 TC_CRITICAL_SECTION_ENTER();
2127 ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= mask;
2128 TC_CRITICAL_SECTION_LEAVE();
2129 }
2130
hri_tc_read_DBGCTRL_reg(const void * const hw)2131 static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw)
2132 {
2133 return ((Tc *)hw)->COUNT8.DBGCTRL.reg;
2134 }
2135
hri_tccount8_set_COUNT_COUNT_bf(const void * const hw,hri_tc_count8_reg_t mask)2136 static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask)
2137 {
2138 TC_CRITICAL_SECTION_ENTER();
2139 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
2140 ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask);
2141 TC_CRITICAL_SECTION_LEAVE();
2142 }
2143
hri_tccount8_get_COUNT_COUNT_bf(const void * const hw,hri_tc_count8_reg_t mask)2144 static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask)
2145 {
2146 uint8_t tmp;
2147 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
2148 tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
2149 tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos;
2150 return tmp;
2151 }
2152
hri_tccount8_write_COUNT_COUNT_bf(const void * const hw,hri_tc_count8_reg_t data)2153 static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t data)
2154 {
2155 uint8_t tmp;
2156 TC_CRITICAL_SECTION_ENTER();
2157 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
2158 tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
2159 tmp &= ~TC_COUNT8_COUNT_COUNT_Msk;
2160 tmp |= TC_COUNT8_COUNT_COUNT(data);
2161 ((Tc *)hw)->COUNT8.COUNT.reg = tmp;
2162 TC_CRITICAL_SECTION_LEAVE();
2163 }
2164
hri_tccount8_clear_COUNT_COUNT_bf(const void * const hw,hri_tc_count8_reg_t mask)2165 static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask)
2166 {
2167 TC_CRITICAL_SECTION_ENTER();
2168 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
2169 ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask);
2170 TC_CRITICAL_SECTION_LEAVE();
2171 }
2172
hri_tccount8_toggle_COUNT_COUNT_bf(const void * const hw,hri_tc_count8_reg_t mask)2173 static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask)
2174 {
2175 TC_CRITICAL_SECTION_ENTER();
2176 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
2177 ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask);
2178 TC_CRITICAL_SECTION_LEAVE();
2179 }
2180
hri_tccount8_read_COUNT_COUNT_bf(const void * const hw)2181 static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw)
2182 {
2183 uint8_t tmp;
2184 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
2185 tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
2186 tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos;
2187 return tmp;
2188 }
2189
hri_tccount8_set_COUNT_reg(const void * const hw,hri_tc_count8_reg_t mask)2190 static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask)
2191 {
2192 TC_CRITICAL_SECTION_ENTER();
2193 ((Tc *)hw)->COUNT8.COUNT.reg |= mask;
2194 TC_CRITICAL_SECTION_LEAVE();
2195 }
2196
hri_tccount8_get_COUNT_reg(const void * const hw,hri_tc_count8_reg_t mask)2197 static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask)
2198 {
2199 uint8_t tmp;
2200 tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
2201 tmp &= mask;
2202 return tmp;
2203 }
2204
hri_tccount8_write_COUNT_reg(const void * const hw,hri_tc_count8_reg_t data)2205 static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tc_count8_reg_t data)
2206 {
2207 TC_CRITICAL_SECTION_ENTER();
2208 ((Tc *)hw)->COUNT8.COUNT.reg = data;
2209 TC_CRITICAL_SECTION_LEAVE();
2210 }
2211
hri_tccount8_clear_COUNT_reg(const void * const hw,hri_tc_count8_reg_t mask)2212 static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask)
2213 {
2214 TC_CRITICAL_SECTION_ENTER();
2215 ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask;
2216 TC_CRITICAL_SECTION_LEAVE();
2217 }
2218
hri_tccount8_toggle_COUNT_reg(const void * const hw,hri_tc_count8_reg_t mask)2219 static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask)
2220 {
2221 TC_CRITICAL_SECTION_ENTER();
2222 ((Tc *)hw)->COUNT8.COUNT.reg ^= mask;
2223 TC_CRITICAL_SECTION_LEAVE();
2224 }
2225
hri_tccount8_read_COUNT_reg(const void * const hw)2226 static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_reg(const void *const hw)
2227 {
2228 return ((Tc *)hw)->COUNT8.COUNT.reg;
2229 }
2230
hri_tc_set_PER_PER_bf(const void * const hw,hri_tc_per_reg_t mask)2231 static inline void hri_tc_set_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask)
2232 {
2233 TC_CRITICAL_SECTION_ENTER();
2234 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
2235 ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask);
2236 TC_CRITICAL_SECTION_LEAVE();
2237 }
2238
hri_tc_get_PER_PER_bf(const void * const hw,hri_tc_per_reg_t mask)2239 static inline hri_tc_per_reg_t hri_tc_get_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask)
2240 {
2241 uint8_t tmp;
2242 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
2243 tmp = ((Tc *)hw)->COUNT8.PER.reg;
2244 tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos;
2245 return tmp;
2246 }
2247
hri_tc_write_PER_PER_bf(const void * const hw,hri_tc_per_reg_t data)2248 static inline void hri_tc_write_PER_PER_bf(const void *const hw, hri_tc_per_reg_t data)
2249 {
2250 uint8_t tmp;
2251 TC_CRITICAL_SECTION_ENTER();
2252 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
2253 tmp = ((Tc *)hw)->COUNT8.PER.reg;
2254 tmp &= ~TC_COUNT8_PER_PER_Msk;
2255 tmp |= TC_COUNT8_PER_PER(data);
2256 ((Tc *)hw)->COUNT8.PER.reg = tmp;
2257 TC_CRITICAL_SECTION_LEAVE();
2258 }
2259
hri_tc_clear_PER_PER_bf(const void * const hw,hri_tc_per_reg_t mask)2260 static inline void hri_tc_clear_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask)
2261 {
2262 TC_CRITICAL_SECTION_ENTER();
2263 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
2264 ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask);
2265 TC_CRITICAL_SECTION_LEAVE();
2266 }
2267
hri_tc_toggle_PER_PER_bf(const void * const hw,hri_tc_per_reg_t mask)2268 static inline void hri_tc_toggle_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask)
2269 {
2270 TC_CRITICAL_SECTION_ENTER();
2271 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
2272 ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask);
2273 TC_CRITICAL_SECTION_LEAVE();
2274 }
2275
hri_tc_read_PER_PER_bf(const void * const hw)2276 static inline hri_tc_per_reg_t hri_tc_read_PER_PER_bf(const void *const hw)
2277 {
2278 uint8_t tmp;
2279 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
2280 tmp = ((Tc *)hw)->COUNT8.PER.reg;
2281 tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos;
2282 return tmp;
2283 }
2284
hri_tc_set_PER_reg(const void * const hw,hri_tc_per_reg_t mask)2285 static inline void hri_tc_set_PER_reg(const void *const hw, hri_tc_per_reg_t mask)
2286 {
2287 TC_CRITICAL_SECTION_ENTER();
2288 ((Tc *)hw)->COUNT8.PER.reg |= mask;
2289 TC_CRITICAL_SECTION_LEAVE();
2290 }
2291
hri_tc_get_PER_reg(const void * const hw,hri_tc_per_reg_t mask)2292 static inline hri_tc_per_reg_t hri_tc_get_PER_reg(const void *const hw, hri_tc_per_reg_t mask)
2293 {
2294 uint8_t tmp;
2295 tmp = ((Tc *)hw)->COUNT8.PER.reg;
2296 tmp &= mask;
2297 return tmp;
2298 }
2299
hri_tc_write_PER_reg(const void * const hw,hri_tc_per_reg_t data)2300 static inline void hri_tc_write_PER_reg(const void *const hw, hri_tc_per_reg_t data)
2301 {
2302 TC_CRITICAL_SECTION_ENTER();
2303 ((Tc *)hw)->COUNT8.PER.reg = data;
2304 TC_CRITICAL_SECTION_LEAVE();
2305 }
2306
hri_tc_clear_PER_reg(const void * const hw,hri_tc_per_reg_t mask)2307 static inline void hri_tc_clear_PER_reg(const void *const hw, hri_tc_per_reg_t mask)
2308 {
2309 TC_CRITICAL_SECTION_ENTER();
2310 ((Tc *)hw)->COUNT8.PER.reg &= ~mask;
2311 TC_CRITICAL_SECTION_LEAVE();
2312 }
2313
hri_tc_toggle_PER_reg(const void * const hw,hri_tc_per_reg_t mask)2314 static inline void hri_tc_toggle_PER_reg(const void *const hw, hri_tc_per_reg_t mask)
2315 {
2316 TC_CRITICAL_SECTION_ENTER();
2317 ((Tc *)hw)->COUNT8.PER.reg ^= mask;
2318 TC_CRITICAL_SECTION_LEAVE();
2319 }
2320
hri_tc_read_PER_reg(const void * const hw)2321 static inline hri_tc_per_reg_t hri_tc_read_PER_reg(const void *const hw)
2322 {
2323 return ((Tc *)hw)->COUNT8.PER.reg;
2324 }
2325
hri_tccount8_set_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc8_reg_t mask)2326 static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
2327 {
2328 TC_CRITICAL_SECTION_ENTER();
2329 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2330 ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask);
2331 TC_CRITICAL_SECTION_LEAVE();
2332 }
2333
hri_tccount8_get_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc8_reg_t mask)2334 static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
2335 {
2336 uint8_t tmp;
2337 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2338 tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
2339 tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos;
2340 return tmp;
2341 }
2342
hri_tccount8_write_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc8_reg_t data)2343 static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data)
2344 {
2345 uint8_t tmp;
2346 TC_CRITICAL_SECTION_ENTER();
2347 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2348 tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
2349 tmp &= ~TC_COUNT8_CC_CC_Msk;
2350 tmp |= TC_COUNT8_CC_CC(data);
2351 ((Tc *)hw)->COUNT8.CC[index].reg = tmp;
2352 TC_CRITICAL_SECTION_LEAVE();
2353 }
2354
hri_tccount8_clear_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc8_reg_t mask)2355 static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
2356 {
2357 TC_CRITICAL_SECTION_ENTER();
2358 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2359 ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask);
2360 TC_CRITICAL_SECTION_LEAVE();
2361 }
2362
hri_tccount8_toggle_CC_CC_bf(const void * const hw,uint8_t index,hri_tc_cc8_reg_t mask)2363 static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
2364 {
2365 TC_CRITICAL_SECTION_ENTER();
2366 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2367 ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask);
2368 TC_CRITICAL_SECTION_LEAVE();
2369 }
2370
hri_tccount8_read_CC_CC_bf(const void * const hw,uint8_t index)2371 static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index)
2372 {
2373 uint8_t tmp;
2374 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2375 tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
2376 tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos;
2377 return tmp;
2378 }
2379
hri_tccount8_set_CC_reg(const void * const hw,uint8_t index,hri_tc_cc8_reg_t mask)2380 static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
2381 {
2382 TC_CRITICAL_SECTION_ENTER();
2383 ((Tc *)hw)->COUNT8.CC[index].reg |= mask;
2384 TC_CRITICAL_SECTION_LEAVE();
2385 }
2386
hri_tccount8_get_CC_reg(const void * const hw,uint8_t index,hri_tc_cc8_reg_t mask)2387 static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
2388 {
2389 uint8_t tmp;
2390 tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
2391 tmp &= mask;
2392 return tmp;
2393 }
2394
hri_tccount8_write_CC_reg(const void * const hw,uint8_t index,hri_tc_cc8_reg_t data)2395 static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data)
2396 {
2397 TC_CRITICAL_SECTION_ENTER();
2398 ((Tc *)hw)->COUNT8.CC[index].reg = data;
2399 TC_CRITICAL_SECTION_LEAVE();
2400 }
2401
hri_tccount8_clear_CC_reg(const void * const hw,uint8_t index,hri_tc_cc8_reg_t mask)2402 static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
2403 {
2404 TC_CRITICAL_SECTION_ENTER();
2405 ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask;
2406 TC_CRITICAL_SECTION_LEAVE();
2407 }
2408
hri_tccount8_toggle_CC_reg(const void * const hw,uint8_t index,hri_tc_cc8_reg_t mask)2409 static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask)
2410 {
2411 TC_CRITICAL_SECTION_ENTER();
2412 ((Tc *)hw)->COUNT8.CC[index].reg ^= mask;
2413 TC_CRITICAL_SECTION_LEAVE();
2414 }
2415
hri_tccount8_read_CC_reg(const void * const hw,uint8_t index)2416 static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index)
2417 {
2418 return ((Tc *)hw)->COUNT8.CC[index].reg;
2419 }
2420
hri_tc_set_PERBUF_PERBUF_bf(const void * const hw,hri_tc_perbuf_reg_t mask)2421 static inline void hri_tc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask)
2422 {
2423 TC_CRITICAL_SECTION_ENTER();
2424 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2425 ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask);
2426 TC_CRITICAL_SECTION_LEAVE();
2427 }
2428
hri_tc_get_PERBUF_PERBUF_bf(const void * const hw,hri_tc_perbuf_reg_t mask)2429 static inline hri_tc_perbuf_reg_t hri_tc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask)
2430 {
2431 uint8_t tmp;
2432 tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
2433 tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos;
2434 return tmp;
2435 }
2436
hri_tc_write_PERBUF_PERBUF_bf(const void * const hw,hri_tc_perbuf_reg_t data)2437 static inline void hri_tc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t data)
2438 {
2439 uint8_t tmp;
2440 TC_CRITICAL_SECTION_ENTER();
2441 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2442 tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
2443 tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk;
2444 tmp |= TC_COUNT8_PERBUF_PERBUF(data);
2445 ((Tc *)hw)->COUNT8.PERBUF.reg = tmp;
2446 TC_CRITICAL_SECTION_LEAVE();
2447 }
2448
hri_tc_clear_PERBUF_PERBUF_bf(const void * const hw,hri_tc_perbuf_reg_t mask)2449 static inline void hri_tc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask)
2450 {
2451 TC_CRITICAL_SECTION_ENTER();
2452 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2453 ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask);
2454 TC_CRITICAL_SECTION_LEAVE();
2455 }
2456
hri_tc_toggle_PERBUF_PERBUF_bf(const void * const hw,hri_tc_perbuf_reg_t mask)2457 static inline void hri_tc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask)
2458 {
2459 TC_CRITICAL_SECTION_ENTER();
2460 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2461 ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask);
2462 TC_CRITICAL_SECTION_LEAVE();
2463 }
2464
hri_tc_read_PERBUF_PERBUF_bf(const void * const hw)2465 static inline hri_tc_perbuf_reg_t hri_tc_read_PERBUF_PERBUF_bf(const void *const hw)
2466 {
2467 uint8_t tmp;
2468 tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
2469 tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos;
2470 return tmp;
2471 }
2472
hri_tc_set_PERBUF_reg(const void * const hw,hri_tc_perbuf_reg_t mask)2473 static inline void hri_tc_set_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask)
2474 {
2475 TC_CRITICAL_SECTION_ENTER();
2476 ((Tc *)hw)->COUNT8.PERBUF.reg |= mask;
2477 TC_CRITICAL_SECTION_LEAVE();
2478 }
2479
hri_tc_get_PERBUF_reg(const void * const hw,hri_tc_perbuf_reg_t mask)2480 static inline hri_tc_perbuf_reg_t hri_tc_get_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask)
2481 {
2482 uint8_t tmp;
2483 tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
2484 tmp &= mask;
2485 return tmp;
2486 }
2487
hri_tc_write_PERBUF_reg(const void * const hw,hri_tc_perbuf_reg_t data)2488 static inline void hri_tc_write_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t data)
2489 {
2490 TC_CRITICAL_SECTION_ENTER();
2491 ((Tc *)hw)->COUNT8.PERBUF.reg = data;
2492 TC_CRITICAL_SECTION_LEAVE();
2493 }
2494
hri_tc_clear_PERBUF_reg(const void * const hw,hri_tc_perbuf_reg_t mask)2495 static inline void hri_tc_clear_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask)
2496 {
2497 TC_CRITICAL_SECTION_ENTER();
2498 ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask;
2499 TC_CRITICAL_SECTION_LEAVE();
2500 }
2501
hri_tc_toggle_PERBUF_reg(const void * const hw,hri_tc_perbuf_reg_t mask)2502 static inline void hri_tc_toggle_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask)
2503 {
2504 TC_CRITICAL_SECTION_ENTER();
2505 ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask;
2506 TC_CRITICAL_SECTION_LEAVE();
2507 }
2508
hri_tc_read_PERBUF_reg(const void * const hw)2509 static inline hri_tc_perbuf_reg_t hri_tc_read_PERBUF_reg(const void *const hw)
2510 {
2511 return ((Tc *)hw)->COUNT8.PERBUF.reg;
2512 }
2513
hri_tccount8_set_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t mask)2514 static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask)
2515 {
2516 TC_CRITICAL_SECTION_ENTER();
2517 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2518 ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask);
2519 TC_CRITICAL_SECTION_LEAVE();
2520 }
2521
hri_tccount8_get_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t mask)2522 static inline hri_tc_ccbuf8_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
2523 hri_tc_ccbuf8_reg_t mask)
2524 {
2525 uint8_t tmp;
2526 tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
2527 tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos;
2528 return tmp;
2529 }
2530
hri_tccount8_write_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t data)2531 static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t data)
2532 {
2533 uint8_t tmp;
2534 TC_CRITICAL_SECTION_ENTER();
2535 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2536 tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
2537 tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk;
2538 tmp |= TC_COUNT8_CCBUF_CCBUF(data);
2539 ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp;
2540 TC_CRITICAL_SECTION_LEAVE();
2541 }
2542
hri_tccount8_clear_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t mask)2543 static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask)
2544 {
2545 TC_CRITICAL_SECTION_ENTER();
2546 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2547 ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask);
2548 TC_CRITICAL_SECTION_LEAVE();
2549 }
2550
hri_tccount8_toggle_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t mask)2551 static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask)
2552 {
2553 TC_CRITICAL_SECTION_ENTER();
2554 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2555 ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask);
2556 TC_CRITICAL_SECTION_LEAVE();
2557 }
2558
hri_tccount8_read_CCBUF_CCBUF_bf(const void * const hw,uint8_t index)2559 static inline hri_tc_ccbuf8_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
2560 {
2561 uint8_t tmp;
2562 tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
2563 tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos;
2564 return tmp;
2565 }
2566
hri_tccount8_set_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t mask)2567 static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask)
2568 {
2569 TC_CRITICAL_SECTION_ENTER();
2570 ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask;
2571 TC_CRITICAL_SECTION_LEAVE();
2572 }
2573
hri_tccount8_get_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t mask)2574 static inline hri_tc_ccbuf8_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index,
2575 hri_tc_ccbuf8_reg_t mask)
2576 {
2577 uint8_t tmp;
2578 tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
2579 tmp &= mask;
2580 return tmp;
2581 }
2582
hri_tccount8_write_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t data)2583 static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t data)
2584 {
2585 TC_CRITICAL_SECTION_ENTER();
2586 ((Tc *)hw)->COUNT8.CCBUF[index].reg = data;
2587 TC_CRITICAL_SECTION_LEAVE();
2588 }
2589
hri_tccount8_clear_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t mask)2590 static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask)
2591 {
2592 TC_CRITICAL_SECTION_ENTER();
2593 ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask;
2594 TC_CRITICAL_SECTION_LEAVE();
2595 }
2596
hri_tccount8_toggle_CCBUF_reg(const void * const hw,uint8_t index,hri_tc_ccbuf8_reg_t mask)2597 static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask)
2598 {
2599 TC_CRITICAL_SECTION_ENTER();
2600 ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask;
2601 TC_CRITICAL_SECTION_LEAVE();
2602 }
2603
hri_tccount8_read_CCBUF_reg(const void * const hw,uint8_t index)2604 static inline hri_tc_ccbuf8_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index)
2605 {
2606 return ((Tc *)hw)->COUNT8.CCBUF[index].reg;
2607 }
2608
hri_tc_get_SYNCBUSY_SWRST_bit(const void * const hw)2609 static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw)
2610 {
2611 return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos;
2612 }
2613
hri_tc_get_SYNCBUSY_ENABLE_bit(const void * const hw)2614 static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
2615 {
2616 return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos;
2617 }
2618
hri_tc_get_SYNCBUSY_CTRLB_bit(const void * const hw)2619 static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
2620 {
2621 return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos;
2622 }
2623
hri_tc_get_SYNCBUSY_STATUS_bit(const void * const hw)2624 static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw)
2625 {
2626 return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos;
2627 }
2628
hri_tc_get_SYNCBUSY_COUNT_bit(const void * const hw)2629 static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw)
2630 {
2631 return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos;
2632 }
2633
hri_tc_get_SYNCBUSY_PER_bit(const void * const hw)2634 static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw)
2635 {
2636 return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos;
2637 }
2638
hri_tc_get_SYNCBUSY_CC0_bit(const void * const hw)2639 static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw)
2640 {
2641 return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos;
2642 }
2643
hri_tc_get_SYNCBUSY_CC1_bit(const void * const hw)2644 static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw)
2645 {
2646 return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos;
2647 }
2648
hri_tc_get_SYNCBUSY_reg(const void * const hw,hri_tc_syncbusy_reg_t mask)2649 static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask)
2650 {
2651 uint32_t tmp;
2652 tmp = ((Tc *)hw)->COUNT8.SYNCBUSY.reg;
2653 tmp &= mask;
2654 return tmp;
2655 }
2656
hri_tc_read_SYNCBUSY_reg(const void * const hw)2657 static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw)
2658 {
2659 return ((Tc *)hw)->COUNT8.SYNCBUSY.reg;
2660 }
2661
hri_tc_get_STATUS_STOP_bit(const void * const hw)2662 static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw)
2663 {
2664 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2665 return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos;
2666 }
2667
hri_tc_clear_STATUS_STOP_bit(const void * const hw)2668 static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw)
2669 {
2670 TC_CRITICAL_SECTION_ENTER();
2671 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2672 ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_STOP;
2673 TC_CRITICAL_SECTION_LEAVE();
2674 }
2675
hri_tc_get_STATUS_SLAVE_bit(const void * const hw)2676 static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw)
2677 {
2678 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2679 return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos;
2680 }
2681
hri_tc_clear_STATUS_SLAVE_bit(const void * const hw)2682 static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw)
2683 {
2684 TC_CRITICAL_SECTION_ENTER();
2685 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2686 ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_SLAVE;
2687 TC_CRITICAL_SECTION_LEAVE();
2688 }
2689
hri_tc_get_STATUS_PERBUFV_bit(const void * const hw)2690 static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw)
2691 {
2692 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2693 return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos;
2694 }
2695
hri_tc_clear_STATUS_PERBUFV_bit(const void * const hw)2696 static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw)
2697 {
2698 TC_CRITICAL_SECTION_ENTER();
2699 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2700 ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_PERBUFV;
2701 TC_CRITICAL_SECTION_LEAVE();
2702 }
2703
hri_tc_get_STATUS_CCBUFV0_bit(const void * const hw)2704 static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw)
2705 {
2706 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2707 return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos;
2708 }
2709
hri_tc_clear_STATUS_CCBUFV0_bit(const void * const hw)2710 static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw)
2711 {
2712 TC_CRITICAL_SECTION_ENTER();
2713 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2714 ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_CCBUFV0;
2715 TC_CRITICAL_SECTION_LEAVE();
2716 }
2717
hri_tc_get_STATUS_CCBUFV1_bit(const void * const hw)2718 static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw)
2719 {
2720 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2721 return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos;
2722 }
2723
hri_tc_clear_STATUS_CCBUFV1_bit(const void * const hw)2724 static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw)
2725 {
2726 TC_CRITICAL_SECTION_ENTER();
2727 hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
2728 ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_CCBUFV1;
2729 TC_CRITICAL_SECTION_LEAVE();
2730 }
2731
hri_tc_get_STATUS_reg(const void * const hw,hri_tc_status_reg_t mask)2732 static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
2733 {
2734 uint8_t tmp;
2735 tmp = ((Tc *)hw)->COUNT8.STATUS.reg;
2736 tmp &= mask;
2737 return tmp;
2738 }
2739
hri_tc_clear_STATUS_reg(const void * const hw,hri_tc_status_reg_t mask)2740 static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
2741 {
2742 TC_CRITICAL_SECTION_ENTER();
2743 ((Tc *)hw)->COUNT8.STATUS.reg = mask;
2744 TC_CRITICAL_SECTION_LEAVE();
2745 }
2746
hri_tc_read_STATUS_reg(const void * const hw)2747 static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw)
2748 {
2749 return ((Tc *)hw)->COUNT8.STATUS.reg;
2750 }
2751
2752 #ifdef __cplusplus
2753 }
2754 #endif
2755
2756 #endif /* _HRI_TC_L21_H_INCLUDED */
2757 #endif /* _SAML21_TC_COMPONENT_ */
2758
