1 /* Auto-generated config file hpl_sercom_config.h */ 2 #ifndef HPL_SERCOM_CONFIG_H 3 #define HPL_SERCOM_CONFIG_H 4 5 // <<< Use Configuration Wizard in Context Menu >>> 6 7 #include <peripheral_clk_config.h> 8 9 #ifndef CONF_SERCOM_0_USART_ENABLE 10 #define CONF_SERCOM_0_USART_ENABLE 1 11 #endif 12 13 // <h> Basic Configuration 14 15 // <q> Receive buffer enable 16 // <i> Enable input buffer in SERCOM module 17 // <id> usart_rx_enable 18 #ifndef CONF_SERCOM_0_USART_RXEN 19 #define CONF_SERCOM_0_USART_RXEN 1 20 #endif 21 22 // <q> Transmitt buffer enable 23 // <i> Enable output buffer in SERCOM module 24 // <id> usart_tx_enable 25 #ifndef CONF_SERCOM_0_USART_TXEN 26 #define CONF_SERCOM_0_USART_TXEN 1 27 #endif 28 29 // <o> Frame parity 30 // <0x0=>No parity 31 // <0x1=>Even parity 32 // <0x2=>Odd parity 33 // <i> Parity bit mode for USART frame 34 // <id> usart_parity 35 #ifndef CONF_SERCOM_0_USART_PARITY 36 #define CONF_SERCOM_0_USART_PARITY 0x0 37 #endif 38 39 // <o> Character Size 40 // <0x0=>8 bits 41 // <0x1=>9 bits 42 // <0x5=>5 bits 43 // <0x6=>6 bits 44 // <0x7=>7 bits 45 // <i> Data character size in USART frame 46 // <id> usart_character_size 47 #ifndef CONF_SERCOM_0_USART_CHSIZE 48 #define CONF_SERCOM_0_USART_CHSIZE 0x0 49 #endif 50 51 // <o> Stop Bit 52 // <0=>One stop bit 53 // <1=>Two stop bits 54 // <i> Number of stop bits in USART frame 55 // <id> usart_stop_bit 56 #ifndef CONF_SERCOM_0_USART_SBMODE 57 #define CONF_SERCOM_0_USART_SBMODE 0 58 #endif 59 60 // <o> Baud rate <1-3000000> 61 // <i> USART baud rate setting 62 // <id> usart_baud_rate 63 #ifndef CONF_SERCOM_0_USART_BAUD 64 #define CONF_SERCOM_0_USART_BAUD 921600 65 #endif 66 67 // </h> 68 69 // <e> Advanced configuration 70 // <id> usart_advanced 71 #ifndef CONF_SERCOM_0_USART_ADVANCED_CONFIG 72 #define CONF_SERCOM_0_USART_ADVANCED_CONFIG 0 73 #endif 74 75 // <q> Run in stand-by 76 // <i> Keep the module running in standby sleep mode 77 // <id> usart_arch_runstdby 78 #ifndef CONF_SERCOM_0_USART_RUNSTDBY 79 #define CONF_SERCOM_0_USART_RUNSTDBY 0 80 #endif 81 82 // <q> Immediate Buffer Overflow Notification 83 // <i> Controls when the BUFOVF status bit is asserted 84 // <id> usart_arch_ibon 85 #ifndef CONF_SERCOM_0_USART_IBON 86 #define CONF_SERCOM_0_USART_IBON 0 87 #endif 88 89 // <q> Start of Frame Detection Enable 90 // <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) 91 // <id> usart_arch_sfde 92 #ifndef CONF_SERCOM_0_USART_SFDE 93 #define CONF_SERCOM_0_USART_SFDE 0 94 #endif 95 96 // <q> Collision Detection Enable 97 // <i> Collision detection enable 98 // <id> usart_arch_cloden 99 #ifndef CONF_SERCOM_0_USART_CLODEN 100 #define CONF_SERCOM_0_USART_CLODEN 0 101 #endif 102 103 // <o> Operating Mode 104 // <0x0=>USART with external clock 105 // <0x1=>USART with internal clock 106 // <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. 107 // <id> usart_arch_clock_mode 108 #ifndef CONF_SERCOM_0_USART_MODE 109 #define CONF_SERCOM_0_USART_MODE 0x1 110 #endif 111 112 // <o> Sample Rate 113 // <0x0=>16x arithmetic 114 // <0x1=>16x fractional 115 // <0x2=>8x arithmetic 116 // <0x3=>8x fractional 117 // <0x3=>3x 118 // <i> How many over-sampling bits used when samling data state 119 // <id> usart_arch_sampr 120 #ifndef CONF_SERCOM_0_USART_SAMPR 121 #define CONF_SERCOM_0_USART_SAMPR 0x0 122 #endif 123 124 // <o> Sample Adjustment 125 // <0x0=>7-8-9 (3-4-5 8-bit over-sampling) 126 // <0x1=>9-10-11 (4-5-6 8-bit over-sampling) 127 // <0x2=>11-12-13 (5-6-7 8-bit over-sampling) 128 // <0x3=>13-14-15 (6-7-8 8-bit over-sampling) 129 // <i> Adjust which samples to use for data sampling in asynchronous mode 130 // <id> usart_arch_sampa 131 #ifndef CONF_SERCOM_0_USART_SAMPA 132 #define CONF_SERCOM_0_USART_SAMPA 0x0 133 #endif 134 135 // <o> Fractional Part <0-7> 136 // <i> Fractional part of the baud rate if baud rate generator is in fractional mode 137 // <id> usart_arch_fractional 138 #ifndef CONF_SERCOM_0_USART_FRACTIONAL 139 #define CONF_SERCOM_0_USART_FRACTIONAL 0x0 140 #endif 141 142 // <o> Data Order 143 // <0=>MSB is transmitted first 144 // <1=>LSB is transmitted first 145 // <i> Data order of the data bits in the frame 146 // <id> usart_arch_dord 147 #ifndef CONF_SERCOM_0_USART_DORD 148 #define CONF_SERCOM_0_USART_DORD 1 149 #endif 150 151 // Does not do anything in UART mode 152 #define CONF_SERCOM_0_USART_CPOL 0 153 154 // <o> Encoding Format 155 // <0=>No encoding 156 // <1=>IrDA encoded 157 // <id> usart_arch_enc 158 #ifndef CONF_SERCOM_0_USART_ENC 159 #define CONF_SERCOM_0_USART_ENC 0 160 #endif 161 162 // <o> Debug Stop Mode 163 // <i> Behavior of the baud-rate generator when CPU is halted by external debugger. 164 // <0=>Keep running 165 // <1=>Halt 166 // <id> usart_arch_dbgstop 167 #ifndef CONF_SERCOM_0_USART_DEBUG_STOP_MODE 168 #define CONF_SERCOM_0_USART_DEBUG_STOP_MODE 0 169 #endif 170 171 // </e> 172 173 #ifndef CONF_SERCOM_0_USART_CMODE 174 #define CONF_SERCOM_0_USART_CMODE 0 175 #endif 176 177 #ifndef CONF_SERCOM_0_USART_RXPO 178 #define CONF_SERCOM_0_USART_RXPO 1 /* RX is on PIN_PA23 */ 179 #endif 180 181 #ifndef CONF_SERCOM_0_USART_TXPO 182 #define CONF_SERCOM_0_USART_TXPO 0 /* TX is on PIN_PA22 */ 183 #endif 184 185 /* Set correct parity settings in register interface based on PARITY setting */ 186 #if CONF_SERCOM_0_USART_PARITY == 0 187 #define CONF_SERCOM_0_USART_PMODE 0 188 #define CONF_SERCOM_0_USART_FORM 0 189 #else 190 #define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1 191 #define CONF_SERCOM_0_USART_FORM 1 192 #endif 193 194 // Calculate BAUD register value in UART mode 195 #if CONF_SERCOM_0_USART_SAMPR == 0 196 #ifndef CONF_SERCOM_0_USART_BAUD_RATE 197 #define CONF_SERCOM_0_USART_BAUD_RATE \ 198 65536 - ((65536 * 16.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) 199 #endif 200 #ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 201 #define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 202 #endif 203 #elif CONF_SERCOM_0_USART_SAMPR == 1 204 #ifndef CONF_SERCOM_0_USART_BAUD_RATE 205 #define CONF_SERCOM_0_USART_BAUD_RATE \ 206 ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 16)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) 207 #endif 208 #ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 209 #define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 210 #endif 211 #elif CONF_SERCOM_0_USART_SAMPR == 2 212 #ifndef CONF_SERCOM_0_USART_BAUD_RATE 213 #define CONF_SERCOM_0_USART_BAUD_RATE \ 214 65536 - ((65536 * 8.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) 215 #endif 216 #ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 217 #define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 218 #endif 219 #elif CONF_SERCOM_0_USART_SAMPR == 3 220 #ifndef CONF_SERCOM_0_USART_BAUD_RATE 221 #define CONF_SERCOM_0_USART_BAUD_RATE \ 222 ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 8)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) 223 #endif 224 #ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 225 #define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 226 #endif 227 #elif CONF_SERCOM_0_USART_SAMPR == 4 228 #ifndef CONF_SERCOM_0_USART_BAUD_RATE 229 #define CONF_SERCOM_0_USART_BAUD_RATE \ 230 65536 - ((65536 * 3.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) 231 #endif 232 #ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 233 #define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 234 #endif 235 #endif 236 237 #include <peripheral_clk_config.h> 238 239 // Enable configuration of module 240 #ifndef CONF_SERCOM_4_SPI_ENABLE 241 #define CONF_SERCOM_4_SPI_ENABLE 1 242 #endif 243 244 // Set module in SPI Master mode 245 #ifndef CONF_SERCOM_4_SPI_MODE 246 #define CONF_SERCOM_4_SPI_MODE 0x03 247 #endif 248 249 // <h> Basic Configuration 250 251 // <q> Receive buffer enable 252 // <i> Enable receive buffer to receive data from slave (RXEN) 253 // <id> spi_master_rx_enable 254 #ifndef CONF_SERCOM_4_SPI_RXEN 255 #define CONF_SERCOM_4_SPI_RXEN 0x1 256 #endif 257 258 // <o> Character Size 259 // <i> Bit size for all characters sent over the SPI bus (CHSIZE) 260 // <0x0=>8 bits 261 // <0x1=>9 bits 262 // <id> spi_master_character_size 263 #ifndef CONF_SERCOM_4_SPI_CHSIZE 264 #define CONF_SERCOM_4_SPI_CHSIZE 0x0 265 #endif 266 267 // <o> Baud rate <1-12000000> 268 // <i> The SPI data transfer rate 269 // <id> spi_master_baud_rate 270 #ifndef CONF_SERCOM_4_SPI_BAUD 271 #define CONF_SERCOM_4_SPI_BAUD 2000000 272 #endif 273 274 // </h> 275 276 // <e> Advanced Configuration 277 // <id> spi_master_advanced 278 #ifndef CONF_SERCOM_4_SPI_ADVANCED 279 #define CONF_SERCOM_4_SPI_ADVANCED 1 280 #endif 281 282 // <o> Dummy byte <0x00-0x1ff> 283 // <id> spi_master_dummybyte 284 // <i> Dummy byte used when reading data from the slave without sending any data 285 #ifndef CONF_SERCOM_4_SPI_DUMMYBYTE 286 #define CONF_SERCOM_4_SPI_DUMMYBYTE 0x1ff 287 #endif 288 289 // <o> Data Order 290 // <0=>MSB first 291 // <1=>LSB first 292 // <i> I least significant or most significant bit is shifted out first (DORD) 293 // <id> spi_master_arch_dord 294 #ifndef CONF_SERCOM_4_SPI_DORD 295 #define CONF_SERCOM_4_SPI_DORD 0x0 296 #endif 297 298 // <o> Clock Polarity 299 // <0=>SCK is low when idle 300 // <1=>SCK is high when idle 301 // <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) 302 // <id> spi_master_arch_cpol 303 #ifndef CONF_SERCOM_4_SPI_CPOL 304 #define CONF_SERCOM_4_SPI_CPOL 0x0 305 #endif 306 307 // <o> Clock Phase 308 // <0x0=>Sample input on leading edge 309 // <0x1=>Sample input on trailing edge 310 // <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA) 311 // <id> spi_master_arch_cpha 312 #ifndef CONF_SERCOM_4_SPI_CPHA 313 #define CONF_SERCOM_4_SPI_CPHA 0x0 314 #endif 315 316 // <o> Immediate Buffer Overflow Notification 317 // <i> Controls when OVF is asserted (IBON) 318 // <0x0=>In data stream 319 // <0x1=>On buffer overflow 320 // <id> spi_master_arch_ibon 321 #ifndef CONF_SERCOM_4_SPI_IBON 322 #define CONF_SERCOM_4_SPI_IBON 0x0 323 #endif 324 325 // <q> Run in stand-by 326 // <i> Module stays active in stand-by sleep mode. (RUNSTDBY) 327 // <id> spi_master_arch_runstdby 328 #ifndef CONF_SERCOM_4_SPI_RUNSTDBY 329 #define CONF_SERCOM_4_SPI_RUNSTDBY 0x0 330 #endif 331 332 // <o> Debug Stop Mode 333 // <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) 334 // <0=>Keep running 335 // <1=>Halt 336 // <id> spi_master_arch_dbgstop 337 #ifndef CONF_SERCOM_4_SPI_DBGSTOP 338 #define CONF_SERCOM_4_SPI_DBGSTOP 0 339 #endif 340 341 // </e> 342 343 // Address mode disabled in master mode 344 #ifndef CONF_SERCOM_4_SPI_AMODE_EN 345 #define CONF_SERCOM_4_SPI_AMODE_EN 0 346 #endif 347 348 #ifndef CONF_SERCOM_4_SPI_AMODE 349 #define CONF_SERCOM_4_SPI_AMODE 0 350 #endif 351 352 #ifndef CONF_SERCOM_4_SPI_ADDR 353 #define CONF_SERCOM_4_SPI_ADDR 0 354 #endif 355 356 #ifndef CONF_SERCOM_4_SPI_ADDRMASK 357 #define CONF_SERCOM_4_SPI_ADDRMASK 0 358 #endif 359 360 #ifndef CONF_SERCOM_4_SPI_SSDE 361 #define CONF_SERCOM_4_SPI_SSDE 0 362 #endif 363 364 #ifndef CONF_SERCOM_4_SPI_MSSEN 365 #define CONF_SERCOM_4_SPI_MSSEN 0x0 366 #endif 367 368 #ifndef CONF_SERCOM_4_SPI_PLOADEN 369 #define CONF_SERCOM_4_SPI_PLOADEN 0 370 #endif 371 372 // <o> Receive Data Pinout 373 // <0x0=>PAD[0] 374 // <0x1=>PAD[1] 375 // <0x2=>PAD[2] 376 // <0x3=>PAD[3] 377 // <id> spi_master_rxpo 378 #ifndef CONF_SERCOM_4_SPI_RXPO 379 #define CONF_SERCOM_4_SPI_RXPO 0 380 #endif 381 382 // <o> Transmit Data Pinout 383 // <0x0=>PAD[0,1]_DO_SCK 384 // <0x1=>PAD[2,3]_DO_SCK 385 // <0x2=>PAD[3,1]_DO_SCK 386 // <0x3=>PAD[0,3]_DO_SCK 387 // <id> spi_master_txpo 388 #ifndef CONF_SERCOM_4_SPI_TXPO 389 #define CONF_SERCOM_4_SPI_TXPO 1 390 #endif 391 392 // Calculate baud register value from requested baudrate value 393 #ifndef CONF_SERCOM_4_SPI_BAUD_RATE 394 #define CONF_SERCOM_4_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM4_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_4_SPI_BAUD)) - 1 395 #endif 396 397 #include <peripheral_clk_config.h> 398 399 #ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER 400 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) 401 #endif 402 403 #ifndef CONF_SERCOM_1_I2CM_ENABLE 404 #define CONF_SERCOM_1_I2CM_ENABLE 1 405 #endif 406 407 // <h> Basic 408 409 // <o> I2C Bus clock speed (Hz) <1-400000> 410 // <i> I2C Bus clock (SCL) speed measured in Hz 411 // <id> i2c_master_baud_rate 412 #ifndef CONF_SERCOM_1_I2CM_BAUD 413 #define CONF_SERCOM_1_I2CM_BAUD 100000 414 #endif 415 416 // </h> 417 418 // <e> Advanced 419 // <id> i2c_master_advanced 420 #ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 421 #define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0 422 #endif 423 424 // <o> TRise (ns) <0-300> 425 // <i> Determined by the bus impedance, check electric characteristics in the datasheet 426 // <i> Standard Fast Mode: typical 215ns, max 300ns 427 // <i> Fast Mode +: typical 60ns, max 100ns 428 // <i> High Speed Mode: typical 20ns, max 40ns 429 // <id> i2c_master_arch_trise 430 431 #ifndef CONF_SERCOM_1_I2CM_TRISE 432 #define CONF_SERCOM_1_I2CM_TRISE 215 433 #endif 434 435 // <q> Master SCL Low Extended Time-Out (MEXTTOEN) 436 // <i> This enables the master SCL low extend time-out 437 // <id> i2c_master_arch_mexttoen 438 #ifndef CONF_SERCOM_1_I2CM_MEXTTOEN 439 #define CONF_SERCOM_1_I2CM_MEXTTOEN 0 440 #endif 441 442 // <q> Slave SCL Low Extend Time-Out (SEXTTOEN) 443 // <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine 444 // <id> i2c_master_arch_sexttoen 445 #ifndef CONF_SERCOM_1_I2CM_SEXTTOEN 446 #define CONF_SERCOM_1_I2CM_SEXTTOEN 0 447 #endif 448 449 // <q> SCL Low Time-Out (LOWTOUT) 450 // <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold 451 // <id> i2c_master_arch_lowtout 452 #ifndef CONF_SERCOM_1_I2CM_LOWTOUT 453 #define CONF_SERCOM_1_I2CM_LOWTOUT 0 454 #endif 455 456 // <o> Inactive Time-Out (INACTOUT) 457 // <0x0=>Disabled 458 // <0x1=>5-6 SCL cycle time-out(50-60us) 459 // <0x2=>10-11 SCL cycle time-out(100-110us) 460 // <0x3=>20-21 SCL cycle time-out(200-210us) 461 // <i> Defines if inactivity time-out should be enabled, and how long the time-out should be 462 // <id> i2c_master_arch_inactout 463 #ifndef CONF_SERCOM_1_I2CM_INACTOUT 464 #define CONF_SERCOM_1_I2CM_INACTOUT 0x0 465 #endif 466 467 // <o> SDA Hold Time (SDAHOLD) 468 // <0=>Disabled 469 // <1=>50-100ns hold time 470 // <2=>300-600ns hold time 471 // <3=>400-800ns hold time 472 // <i> Defines the SDA hold time with respect to the negative edge of SCL 473 // <id> i2c_master_arch_sdahold 474 #ifndef CONF_SERCOM_1_I2CM_SDAHOLD 475 #define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 476 #endif 477 478 // <q> Run in stand-by 479 // <i> Determine if the module shall run in standby sleep mode 480 // <id> i2c_master_arch_runstdby 481 #ifndef CONF_SERCOM_1_I2CM_RUNSTDBY 482 #define CONF_SERCOM_1_I2CM_RUNSTDBY 0 483 #endif 484 485 // <o> Debug Stop Mode 486 // <i> Behavior of the baud-rate generator when CPU is halted by external debugger. 487 // <0=>Keep running 488 // <1=>Halt 489 // <id> i2c_master_arch_dbgstop 490 #ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 491 #define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 492 #endif 493 494 // </e> 495 496 #ifndef CONF_SERCOM_1_I2CM_SPEED 497 #define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode 498 #endif 499 #if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 500 #warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns 501 #undef CONF_SERCOM_1_I2CM_TRISE 502 #define CONF_SERCOM_1_I2CM_TRISE 215U 503 #endif 504 505 // gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) 506 // BAUD + BAUDLOW = -------------------------------------------------------------------- 507 // i2c_scl_freq 508 // BAUD: register value low [7:0] 509 // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW 510 #define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ 511 (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ 512 - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ 513 / 1000U)) \ 514 * 10U \ 515 + 5U) \ 516 / (CONF_SERCOM_1_I2CM_BAUD * 10U)) 517 #ifndef CONF_SERCOM_1_I2CM_BAUD_RATE 518 #if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) 519 #warning Requested I2C baudrate too low, please check 520 #define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF 521 #elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 522 #warning Requested I2C baudrate too high, please check 523 #define CONF_SERCOM_1_I2CM_BAUD_RATE 1 524 #else 525 #define CONF_SERCOM_1_I2CM_BAUD_RATE \ 526 ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ 527 ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ 528 : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) 529 #endif 530 #endif 531 532 // <<< end of configuration section >>> 533 534 #endif // HPL_SERCOM_CONFIG_H 535
