1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_M33_H 9 #define _HARDWARE_STRUCTS_M33_H 10 11 /** 12 * \file rp2350/m33.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/m33.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/m33.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 #if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV 27 #error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" 28 #endif 29 30 typedef struct { 31 // (Description copied from array index 0 register M33_ITM_STIM0 applies similarly to other array indexes) 32 _REG_(M33_ITM_STIM0_OFFSET) // M33_ITM_STIM0 33 // ITM Stimulus Port Register 0 34 // 0xffffffff [31:0] STIMULUS (0x00000000) Data to write to the Stimulus Port FIFO, for forwarding... 35 io_rw_32 itm_stim[32]; 36 37 uint32_t _pad0[864]; 38 39 _REG_(M33_ITM_TER0_OFFSET) // M33_ITM_TER0 40 // Provide an individual enable bit for each ITM_STIM register 41 // 0xffffffff [31:0] STIMENA (0x00000000) For STIMENA[m] in ITM_TER*n, controls whether... 42 io_rw_32 itm_ter0; 43 44 uint32_t _pad1[15]; 45 46 _REG_(M33_ITM_TPR_OFFSET) // M33_ITM_TPR 47 // Controls which stimulus ports can be accessed by unprivileged code 48 // 0x0000000f [3:0] PRIVMASK (0x0) Bit mask to enable tracing on ITM stimulus ports 49 io_rw_32 itm_tpr; 50 51 uint32_t _pad2[15]; 52 53 _REG_(M33_ITM_TCR_OFFSET) // M33_ITM_TCR 54 // Configures and controls transfers through the ITM interface 55 // 0x00800000 [23] BUSY (0) Indicates whether the ITM is currently processing events 56 // 0x007f0000 [22:16] TRACEBUSID (0x00) Identifier for multi-source trace stream formatting 57 // 0x00000c00 [11:10] GTSFREQ (0x0) Defines how often the ITM generates a global timestamp,... 58 // 0x00000300 [9:8] TSPRESCALE (0x0) Local timestamp prescaler, used with the trace packet... 59 // 0x00000020 [5] STALLENA (0) Stall the PE to guarantee delivery of Data Trace packets 60 // 0x00000010 [4] SWOENA (0) Enables asynchronous clocking of the timestamp counter 61 // 0x00000008 [3] TXENA (0) Enables forwarding of hardware event packet from the DWT... 62 // 0x00000004 [2] SYNCENA (0) Enables Synchronization packet transmission for a... 63 // 0x00000002 [1] TSENA (0) Enables Local timestamp generation 64 // 0x00000001 [0] ITMENA (0) Enables the ITM 65 io_rw_32 itm_tcr; 66 67 uint32_t _pad3[27]; 68 69 _REG_(M33_INT_ATREADY_OFFSET) // M33_INT_ATREADY 70 // Integration Mode: Read ATB Ready 71 // 0x00000002 [1] AFVALID (0) A read of this bit returns the value of AFVALID 72 // 0x00000001 [0] ATREADY (0) A read of this bit returns the value of ATREADY 73 io_ro_32 int_atready; 74 75 uint32_t _pad4; 76 77 _REG_(M33_INT_ATVALID_OFFSET) // M33_INT_ATVALID 78 // Integration Mode: Write ATB Valid 79 // 0x00000002 [1] AFREADY (0) A write to this bit gives the value of AFREADY 80 // 0x00000001 [0] ATREADY (0) A write to this bit gives the value of ATVALID 81 io_rw_32 int_atvalid; 82 83 uint32_t _pad5; 84 85 _REG_(M33_ITM_ITCTRL_OFFSET) // M33_ITM_ITCTRL 86 // Integration Mode Control Register 87 // 0x00000001 [0] IME (0) Integration mode enable bit - The possible values are: ... 88 io_rw_32 itm_itctrl; 89 90 uint32_t _pad6[46]; 91 92 _REG_(M33_ITM_DEVARCH_OFFSET) // M33_ITM_DEVARCH 93 // Provides CoreSight discovery information for the ITM 94 // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component 95 // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present 96 // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component 97 // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component 98 // 0x00000fff [11:0] ARCHPART (0xa01) Defines the architecture of the component 99 io_ro_32 itm_devarch; 100 101 uint32_t _pad7[3]; 102 103 _REG_(M33_ITM_DEVTYPE_OFFSET) // M33_ITM_DEVTYPE 104 // Provides CoreSight discovery information for the ITM 105 // 0x000000f0 [7:4] SUB (0x4) Component sub-type 106 // 0x0000000f [3:0] MAJOR (0x3) Component major type 107 io_ro_32 itm_devtype; 108 109 _REG_(M33_ITM_PIDR4_OFFSET) // M33_ITM_PIDR4 110 // Provides CoreSight discovery information for the ITM 111 // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification 112 // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification 113 io_ro_32 itm_pidr4; 114 115 _REG_(M33_ITM_PIDR5_OFFSET) // M33_ITM_PIDR5 116 // Provides CoreSight discovery information for the ITM 117 // 0x00000000 [31:0] ITM_PIDR5 (0x00000000) 118 io_rw_32 itm_pidr5; 119 120 _REG_(M33_ITM_PIDR6_OFFSET) // M33_ITM_PIDR6 121 // Provides CoreSight discovery information for the ITM 122 // 0x00000000 [31:0] ITM_PIDR6 (0x00000000) 123 io_rw_32 itm_pidr6; 124 125 _REG_(M33_ITM_PIDR7_OFFSET) // M33_ITM_PIDR7 126 // Provides CoreSight discovery information for the ITM 127 // 0x00000000 [31:0] ITM_PIDR7 (0x00000000) 128 io_rw_32 itm_pidr7; 129 130 _REG_(M33_ITM_PIDR0_OFFSET) // M33_ITM_PIDR0 131 // Provides CoreSight discovery information for the ITM 132 // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification 133 io_ro_32 itm_pidr0; 134 135 _REG_(M33_ITM_PIDR1_OFFSET) // M33_ITM_PIDR1 136 // Provides CoreSight discovery information for the ITM 137 // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification 138 // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification 139 io_ro_32 itm_pidr1; 140 141 _REG_(M33_ITM_PIDR2_OFFSET) // M33_ITM_PIDR2 142 // Provides CoreSight discovery information for the ITM 143 // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification 144 // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification 145 // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification 146 io_ro_32 itm_pidr2; 147 148 _REG_(M33_ITM_PIDR3_OFFSET) // M33_ITM_PIDR3 149 // Provides CoreSight discovery information for the ITM 150 // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification 151 // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification 152 io_ro_32 itm_pidr3; 153 154 // (Description copied from array index 0 register M33_ITM_CIDR0 applies similarly to other array indexes) 155 _REG_(M33_ITM_CIDR0_OFFSET) // M33_ITM_CIDR0 156 // Provides CoreSight discovery information for the ITM 157 // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification 158 io_ro_32 itm_cidr[4]; 159 160 _REG_(M33_DWT_CTRL_OFFSET) // M33_DWT_CTRL 161 // Provides configuration and status information for the DWT unit, and used to control features of the unit 162 // 0xf0000000 [31:28] NUMCOMP (0x7) Number of DWT comparators implemented 163 // 0x08000000 [27] NOTRCPKT (0) Indicates whether the implementation does not support trace 164 // 0x04000000 [26] NOEXTTRIG (0) Reserved, RAZ 165 // 0x02000000 [25] NOCYCCNT (1) Indicates whether the implementation does not include a... 166 // 0x01000000 [24] NOPRFCNT (1) Indicates whether the implementation does not include... 167 // 0x00800000 [23] CYCDISS (0) Controls whether the cycle counter is disabled in Secure state 168 // 0x00400000 [22] CYCEVTENA (1) Enables Event Counter packet generation on POSTCNT underflow 169 // 0x00200000 [21] FOLDEVTENA (1) Enables DWT_FOLDCNT counter 170 // 0x00100000 [20] LSUEVTENA (1) Enables DWT_LSUCNT counter 171 // 0x00080000 [19] SLEEPEVTENA (0) Enable DWT_SLEEPCNT counter 172 // 0x00040000 [18] EXCEVTENA (1) Enables DWT_EXCCNT counter 173 // 0x00020000 [17] CPIEVTENA (0) Enables DWT_CPICNT counter 174 // 0x00010000 [16] EXTTRCENA (0) Enables generation of Exception Trace packets 175 // 0x00001000 [12] PCSAMPLENA (1) Enables use of POSTCNT counter as a timer for Periodic... 176 // 0x00000c00 [11:10] SYNCTAP (0x2) Selects the position of the synchronization packet... 177 // 0x00000200 [9] CYCTAP (0) Selects the position of the POSTCNT tap on the CYCCNT counter 178 // 0x000001e0 [8:5] POSTINIT (0x1) Initial value for the POSTCNT counter 179 // 0x0000001e [4:1] POSTPRESET (0x2) Reload value for the POSTCNT counter 180 // 0x00000001 [0] CYCCNTENA (0) Enables CYCCNT 181 io_rw_32 dwt_ctrl; 182 183 _REG_(M33_DWT_CYCCNT_OFFSET) // M33_DWT_CYCCNT 184 // Shows or sets the value of the processor cycle counter, CYCCNT 185 // 0xffffffff [31:0] CYCCNT (0x00000000) Increments one on each processor clock cycle when DWT_CTRL 186 io_rw_32 dwt_cyccnt; 187 188 uint32_t _pad8; 189 190 _REG_(M33_DWT_EXCCNT_OFFSET) // M33_DWT_EXCCNT 191 // Counts the total cycles spent in exception processing 192 // 0x000000ff [7:0] EXCCNT (0x00) Counts one on each cycle when all of the following are... 193 io_rw_32 dwt_exccnt; 194 195 uint32_t _pad9; 196 197 _REG_(M33_DWT_LSUCNT_OFFSET) // M33_DWT_LSUCNT 198 // Increments on the additional cycles required to execute all load or store instructions 199 // 0x000000ff [7:0] LSUCNT (0x00) Counts one on each cycle when all of the following are... 200 io_rw_32 dwt_lsucnt; 201 202 _REG_(M33_DWT_FOLDCNT_OFFSET) // M33_DWT_FOLDCNT 203 // Increments on the additional cycles required to execute all load or store instructions 204 // 0x000000ff [7:0] FOLDCNT (0x00) Counts on each cycle when all of the following are true:... 205 io_rw_32 dwt_foldcnt; 206 207 uint32_t _pad10; 208 209 _REG_(M33_DWT_COMP0_OFFSET) // M33_DWT_COMP0 210 // Provides a reference value for use by watchpoint comparator 0 211 // 0xffffffff [31:0] DWT_COMP0 (0x00000000) 212 io_rw_32 dwt_comp0; 213 214 uint32_t _pad11; 215 216 _REG_(M33_DWT_FUNCTION0_OFFSET) // M33_DWT_FUNCTION0 217 // Controls the operation of watchpoint comparator 0 218 // 0xf8000000 [31:27] ID (0x0b) Identifies the capabilities for MATCH for comparator *n 219 // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches 220 // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... 221 // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match 222 // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator 223 io_rw_32 dwt_function0; 224 225 uint32_t _pad12; 226 227 _REG_(M33_DWT_COMP1_OFFSET) // M33_DWT_COMP1 228 // Provides a reference value for use by watchpoint comparator 1 229 // 0xffffffff [31:0] DWT_COMP1 (0x00000000) 230 io_rw_32 dwt_comp1; 231 232 uint32_t _pad13; 233 234 _REG_(M33_DWT_FUNCTION1_OFFSET) // M33_DWT_FUNCTION1 235 // Controls the operation of watchpoint comparator 1 236 // 0xf8000000 [31:27] ID (0x11) Identifies the capabilities for MATCH for comparator *n 237 // 0x01000000 [24] MATCHED (1) Set to 1 when the comparator matches 238 // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... 239 // 0x00000030 [5:4] ACTION (0x2) Defines the action on a match 240 // 0x0000000f [3:0] MATCH (0x8) Controls the type of match generated by this comparator 241 io_rw_32 dwt_function1; 242 243 uint32_t _pad14; 244 245 _REG_(M33_DWT_COMP2_OFFSET) // M33_DWT_COMP2 246 // Provides a reference value for use by watchpoint comparator 2 247 // 0xffffffff [31:0] DWT_COMP2 (0x00000000) 248 io_rw_32 dwt_comp2; 249 250 uint32_t _pad15; 251 252 _REG_(M33_DWT_FUNCTION2_OFFSET) // M33_DWT_FUNCTION2 253 // Controls the operation of watchpoint comparator 2 254 // 0xf8000000 [31:27] ID (0x0a) Identifies the capabilities for MATCH for comparator *n 255 // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches 256 // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... 257 // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match 258 // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator 259 io_rw_32 dwt_function2; 260 261 uint32_t _pad16; 262 263 _REG_(M33_DWT_COMP3_OFFSET) // M33_DWT_COMP3 264 // Provides a reference value for use by watchpoint comparator 3 265 // 0xffffffff [31:0] DWT_COMP3 (0x00000000) 266 io_rw_32 dwt_comp3; 267 268 uint32_t _pad17; 269 270 _REG_(M33_DWT_FUNCTION3_OFFSET) // M33_DWT_FUNCTION3 271 // Controls the operation of watchpoint comparator 3 272 // 0xf8000000 [31:27] ID (0x04) Identifies the capabilities for MATCH for comparator *n 273 // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches 274 // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... 275 // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match 276 // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator 277 io_rw_32 dwt_function3; 278 279 uint32_t _pad18[984]; 280 281 _REG_(M33_DWT_DEVARCH_OFFSET) // M33_DWT_DEVARCH 282 // Provides CoreSight discovery information for the DWT 283 // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component 284 // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present 285 // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component 286 // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component 287 // 0x00000fff [11:0] ARCHPART (0xa02) Defines the architecture of the component 288 io_ro_32 dwt_devarch; 289 290 uint32_t _pad19[3]; 291 292 _REG_(M33_DWT_DEVTYPE_OFFSET) // M33_DWT_DEVTYPE 293 // Provides CoreSight discovery information for the DWT 294 // 0x000000f0 [7:4] SUB (0x0) Component sub-type 295 // 0x0000000f [3:0] MAJOR (0x0) Component major type 296 io_ro_32 dwt_devtype; 297 298 _REG_(M33_DWT_PIDR4_OFFSET) // M33_DWT_PIDR4 299 // Provides CoreSight discovery information for the DWT 300 // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification 301 // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification 302 io_ro_32 dwt_pidr4; 303 304 _REG_(M33_DWT_PIDR5_OFFSET) // M33_DWT_PIDR5 305 // Provides CoreSight discovery information for the DWT 306 // 0x00000000 [31:0] DWT_PIDR5 (0x00000000) 307 io_rw_32 dwt_pidr5; 308 309 _REG_(M33_DWT_PIDR6_OFFSET) // M33_DWT_PIDR6 310 // Provides CoreSight discovery information for the DWT 311 // 0x00000000 [31:0] DWT_PIDR6 (0x00000000) 312 io_rw_32 dwt_pidr6; 313 314 _REG_(M33_DWT_PIDR7_OFFSET) // M33_DWT_PIDR7 315 // Provides CoreSight discovery information for the DWT 316 // 0x00000000 [31:0] DWT_PIDR7 (0x00000000) 317 io_rw_32 dwt_pidr7; 318 319 _REG_(M33_DWT_PIDR0_OFFSET) // M33_DWT_PIDR0 320 // Provides CoreSight discovery information for the DWT 321 // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification 322 io_ro_32 dwt_pidr0; 323 324 _REG_(M33_DWT_PIDR1_OFFSET) // M33_DWT_PIDR1 325 // Provides CoreSight discovery information for the DWT 326 // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification 327 // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification 328 io_ro_32 dwt_pidr1; 329 330 _REG_(M33_DWT_PIDR2_OFFSET) // M33_DWT_PIDR2 331 // Provides CoreSight discovery information for the DWT 332 // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification 333 // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification 334 // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification 335 io_ro_32 dwt_pidr2; 336 337 _REG_(M33_DWT_PIDR3_OFFSET) // M33_DWT_PIDR3 338 // Provides CoreSight discovery information for the DWT 339 // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification 340 // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification 341 io_ro_32 dwt_pidr3; 342 343 // (Description copied from array index 0 register M33_DWT_CIDR0 applies similarly to other array indexes) 344 _REG_(M33_DWT_CIDR0_OFFSET) // M33_DWT_CIDR0 345 // Provides CoreSight discovery information for the DWT 346 // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification 347 io_ro_32 dwt_cidr[4]; 348 349 _REG_(M33_FP_CTRL_OFFSET) // M33_FP_CTRL 350 // Provides FPB implementation information, and the global enable for the FPB unit 351 // 0xf0000000 [31:28] REV (0x6) Flash Patch and Breakpoint Unit architecture revision 352 // 0x00007000 [14:12] NUM_CODE_14_12_ (0x5) Indicates the number of implemented instruction address... 353 // 0x00000f00 [11:8] NUM_LIT (0x5) Indicates the number of implemented literal address comparators 354 // 0x000000f0 [7:4] NUM_CODE_7_4_ (0x8) Indicates the number of implemented instruction address... 355 // 0x00000002 [1] KEY (0) Writes to the FP_CTRL are ignored unless KEY is... 356 // 0x00000001 [0] ENABLE (0) Enables the FPB 357 io_rw_32 fp_ctrl; 358 359 _REG_(M33_FP_REMAP_OFFSET) // M33_FP_REMAP 360 // Indicates whether the implementation supports Flash Patch remap and, if it does, holds the... 361 // 0x20000000 [29] RMPSPT (0) Indicates whether the FPB unit supports the Flash Patch... 362 // 0x1fffffe0 [28:5] REMAP (0x000000) Holds the bits[28:5] of the Flash Patch remap address 363 io_ro_32 fp_remap; 364 365 // (Description copied from array index 0 register M33_FP_COMP0 applies similarly to other array indexes) 366 _REG_(M33_FP_COMP0_OFFSET) // M33_FP_COMP0 367 // Holds an address for comparison 368 // 0x00000001 [0] BE (0) Selects between flashpatch and breakpoint functionality 369 io_rw_32 fp_comp[8]; 370 371 uint32_t _pad20[997]; 372 373 _REG_(M33_FP_DEVARCH_OFFSET) // M33_FP_DEVARCH 374 // Provides CoreSight discovery information for the FPB 375 // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component 376 // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present 377 // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component 378 // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component 379 // 0x00000fff [11:0] ARCHPART (0xa03) Defines the architecture of the component 380 io_ro_32 fp_devarch; 381 382 uint32_t _pad21[3]; 383 384 _REG_(M33_FP_DEVTYPE_OFFSET) // M33_FP_DEVTYPE 385 // Provides CoreSight discovery information for the FPB 386 // 0x000000f0 [7:4] SUB (0x0) Component sub-type 387 // 0x0000000f [3:0] MAJOR (0x0) Component major type 388 io_ro_32 fp_devtype; 389 390 _REG_(M33_FP_PIDR4_OFFSET) // M33_FP_PIDR4 391 // Provides CoreSight discovery information for the FP 392 // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification 393 // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification 394 io_ro_32 fp_pidr4; 395 396 _REG_(M33_FP_PIDR5_OFFSET) // M33_FP_PIDR5 397 // Provides CoreSight discovery information for the FP 398 // 0x00000000 [31:0] FP_PIDR5 (0x00000000) 399 io_rw_32 fp_pidr5; 400 401 _REG_(M33_FP_PIDR6_OFFSET) // M33_FP_PIDR6 402 // Provides CoreSight discovery information for the FP 403 // 0x00000000 [31:0] FP_PIDR6 (0x00000000) 404 io_rw_32 fp_pidr6; 405 406 _REG_(M33_FP_PIDR7_OFFSET) // M33_FP_PIDR7 407 // Provides CoreSight discovery information for the FP 408 // 0x00000000 [31:0] FP_PIDR7 (0x00000000) 409 io_rw_32 fp_pidr7; 410 411 _REG_(M33_FP_PIDR0_OFFSET) // M33_FP_PIDR0 412 // Provides CoreSight discovery information for the FP 413 // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification 414 io_ro_32 fp_pidr0; 415 416 _REG_(M33_FP_PIDR1_OFFSET) // M33_FP_PIDR1 417 // Provides CoreSight discovery information for the FP 418 // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification 419 // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification 420 io_ro_32 fp_pidr1; 421 422 _REG_(M33_FP_PIDR2_OFFSET) // M33_FP_PIDR2 423 // Provides CoreSight discovery information for the FP 424 // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification 425 // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification 426 // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification 427 io_ro_32 fp_pidr2; 428 429 _REG_(M33_FP_PIDR3_OFFSET) // M33_FP_PIDR3 430 // Provides CoreSight discovery information for the FP 431 // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification 432 // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification 433 io_ro_32 fp_pidr3; 434 435 // (Description copied from array index 0 register M33_FP_CIDR0 applies similarly to other array indexes) 436 _REG_(M33_FP_CIDR0_OFFSET) // M33_FP_CIDR0 437 // Provides CoreSight discovery information for the FP 438 // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification 439 io_ro_32 fp_cidr[4]; 440 441 uint32_t _pad22[11265]; 442 443 _REG_(M33_ICTR_OFFSET) // M33_ICTR 444 // Provides information about the interrupt controller 445 // 0x0000000f [3:0] INTLINESNUM (0x1) Indicates the number of the highest implemented register... 446 io_ro_32 ictr; 447 448 _REG_(M33_ACTLR_OFFSET) // M33_ACTLR 449 // Provides IMPLEMENTATION DEFINED configuration and control options 450 // 0x20000000 [29] EXTEXCLALL (0) External Exclusives Allowed with no MPU 451 // 0x00001000 [12] DISITMATBFLUSH (0) Disable ATB Flush 452 // 0x00000400 [10] FPEXCODIS (0) Disable FPU exception outputs 453 // 0x00000200 [9] DISOOFP (0) Disable out-of-order FP instruction completion 454 // 0x00000004 [2] DISFOLD (0) Disable dual-issue 455 // 0x00000001 [0] DISMCYCINT (0) Disable dual-issue 456 io_rw_32 actlr; 457 458 uint32_t _pad23; 459 460 _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR 461 // SysTick Control and Status Register 462 // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read 463 // 0x00000004 [2] CLKSOURCE (0) SysTick clock source 464 // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + 465 // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + 466 io_rw_32 syst_csr; 467 468 _REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR 469 // SysTick Reload Value Register 470 // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... 471 io_rw_32 syst_rvr; 472 473 _REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR 474 // SysTick Current Value Register 475 // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter 476 io_rw_32 syst_cvr; 477 478 _REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB 479 // SysTick Calibration Value Register 480 // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... 481 // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... 482 // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... 483 io_ro_32 syst_calib; 484 485 uint32_t _pad24[56]; 486 487 // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) 488 _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 489 // Enables or reads the enabled state of each group of 32 interrupts 490 // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... 491 io_rw_32 nvic_iser[2]; 492 493 uint32_t _pad25[30]; 494 495 // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) 496 _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 497 // Clears or reads the enabled state of each group of 32 interrupts 498 // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... 499 io_rw_32 nvic_icer[2]; 500 501 uint32_t _pad26[30]; 502 503 // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) 504 _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 505 // Enables or reads the pending state of each group of 32 interrupts 506 // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... 507 io_rw_32 nvic_ispr[2]; 508 509 uint32_t _pad27[30]; 510 511 // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) 512 _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 513 // Clears or reads the pending state of each group of 32 interrupts 514 // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... 515 io_rw_32 nvic_icpr[2]; 516 517 uint32_t _pad28[30]; 518 519 // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) 520 _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 521 // For each group of 32 interrupts, shows the active state of each interrupt 522 // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... 523 io_rw_32 nvic_iabr[2]; 524 525 uint32_t _pad29[30]; 526 527 // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) 528 _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 529 // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state 530 // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... 531 io_rw_32 nvic_itns[2]; 532 533 uint32_t _pad30[30]; 534 535 // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) 536 _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 537 // Sets or reads interrupt priorities 538 // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... 539 // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... 540 // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... 541 // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... 542 io_rw_32 nvic_ipr[16]; 543 544 uint32_t _pad31[560]; 545 546 _REG_(M33_CPUID_OFFSET) // M33_CPUID 547 // Provides identification information for the PE, including an implementer code for the device and... 548 // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... 549 // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number 550 // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE 551 // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device 552 // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device 553 io_ro_32 cpuid; 554 555 _REG_(M33_ICSR_OFFSET) // M33_ICSR 556 // Controls and provides status information for NMI, PendSV, SysTick and interrupts 557 // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending 558 // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared 559 // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending 560 // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS 561 // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending 562 // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS 563 // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... 564 // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... 565 // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... 566 // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... 567 // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... 568 // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception 569 io_rw_32 icsr; 570 571 _REG_(M33_VTOR_OFFSET) // M33_VTOR 572 // Vector Table Offset Register 573 // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field 574 io_rw_32 vtor; 575 576 _REG_(M33_AIRCR_OFFSET) // M33_AIRCR 577 // Application Interrupt and Reset Control Register 578 // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + 579 // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + 580 // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions 581 // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable 582 // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field 583 // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only 584 // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... 585 // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... 586 io_rw_32 aircr; 587 588 _REG_(M33_SCR_OFFSET) // M33_SCR 589 // System Control Register 590 // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + 591 // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + 592 // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... 593 // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... 594 io_rw_32 scr; 595 596 _REG_(M33_CCR_OFFSET) // M33_CCR 597 // Sets or returns configuration and control data 598 // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS 599 // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... 600 // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS 601 // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... 602 // 0x00000200 [9] RES1 (1) Reserved, RES1 603 // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... 604 // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... 605 // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses 606 // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... 607 // 0x00000001 [0] RES1_1 (1) Reserved, RES1 608 io_rw_32 ccr; 609 610 // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) 611 _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 612 // Sets or returns priority for system handlers 4 - 7 613 // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault 614 // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault 615 // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault 616 // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault 617 io_rw_32 shpr[3]; 618 619 _REG_(M33_SHCSR_OFFSET) // M33_SHCSR 620 // Provides access to the active and pending status of system exceptions 621 // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS 622 // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception 623 // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled 624 // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS 625 // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled 626 // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS 627 // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS 628 // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception 629 // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS 630 // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... 631 // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS 632 // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS 633 // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception 634 // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS 635 // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception 636 // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception 637 // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS 638 // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... 639 // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception 640 // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS 641 io_rw_32 shcsr; 642 643 _REG_(M33_CFSR_OFFSET) // M33_CFSR 644 // Contains the three Configurable Fault Status Registers 645 // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... 646 // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... 647 // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... 648 // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... 649 // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... 650 // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR 651 // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... 652 // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register 653 // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... 654 // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... 655 // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... 656 // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred 657 // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred 658 // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... 659 // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions 660 io_rw_32 cfsr; 661 662 _REG_(M33_HFSR_OFFSET) // M33_HFSR 663 // Shows the cause of any HardFaults 664 // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred 665 // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... 666 // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... 667 io_rw_32 hfsr; 668 669 _REG_(M33_DFSR_OFFSET) // M33_DFSR 670 // Shows which debug event occurred 671 // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... 672 // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... 673 // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... 674 // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... 675 // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... 676 io_rw_32 dfsr; 677 678 _REG_(M33_MMFAR_OFFSET) // M33_MMFAR 679 // Shows the address of the memory location that caused an MPU fault 680 // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... 681 io_rw_32 mmfar; 682 683 _REG_(M33_BFAR_OFFSET) // M33_BFAR 684 // Shows the address associated with a precise data access BusFault 685 // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... 686 io_rw_32 bfar; 687 688 uint32_t _pad32; 689 690 // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) 691 _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 692 // Gives top-level information about the instruction set supported by the PE 693 // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support 694 // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support 695 io_ro_32 id_pfr[2]; 696 697 _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 698 // Provides top level information about the debug system 699 // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture 700 io_ro_32 id_dfr0; 701 702 _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 703 // Provides information about the IMPLEMENTATION DEFINED features of the PE 704 // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning 705 // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning 706 // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning 707 // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning 708 io_ro_32 id_afr0; 709 710 // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) 711 _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 712 // Provides information about the implemented memory model and memory management support 713 // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers 714 // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) 715 // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented 716 // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented 717 // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... 718 io_ro_32 id_mmfr[4]; 719 720 // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) 721 _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 722 // Provides information about the instruction set implemented by the PE 723 // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions 724 // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions 725 // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions 726 // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions 727 // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions 728 // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions 729 io_ro_32 id_isar[6]; 730 731 uint32_t _pad33; 732 733 _REG_(M33_CTR_OFFSET) // M33_CTR 734 // Provides information about the architecture of the caches 735 // 0x80000000 [31] RES1 (1) Reserved, RES1 736 // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... 737 // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... 738 // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... 739 // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 740 // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... 741 io_ro_32 ctr; 742 743 uint32_t _pad34[2]; 744 745 _REG_(M33_CPACR_OFFSET) // M33_CPACR 746 // Specifies the access privileges for coprocessors and the FP Extension 747 // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored 748 // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality 749 // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 750 // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 751 // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 752 // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 753 // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 754 // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 755 // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 756 // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 757 io_rw_32 cpacr; 758 759 _REG_(M33_NSACR_OFFSET) // M33_NSACR 760 // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 761 // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension 762 // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension 763 // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 764 // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 765 // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 766 // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 767 // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 768 // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 769 // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 770 // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 771 io_rw_32 nsacr; 772 773 _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE 774 // The MPU Type Register indicates how many regions the MPU `FTSSS supports 775 // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU 776 // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data... 777 io_ro_32 mpu_type; 778 779 _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL 780 // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled... 781 // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for... 782 // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less... 783 // 0x00000001 [0] ENABLE (0) Enables the MPU 784 io_rw_32 mpu_ctrl; 785 786 _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR 787 // Selects the region currently accessed by MPU_RBAR and MPU_RLAR 788 // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR 789 io_rw_32 mpu_rnr; 790 791 _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR 792 // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS 793 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... 794 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory 795 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region 796 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region 797 io_rw_32 mpu_rbar; 798 799 _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR 800 // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS 801 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... 802 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... 803 // 0x00000001 [0] EN (0) Region enable 804 io_rw_32 mpu_rlar; 805 806 _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1 807 // Provides indirect read and write access to the base address of the MPU region selected by... 808 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... 809 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory 810 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region 811 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region 812 io_rw_32 mpu_rbar_a1; 813 814 _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1 815 // Provides indirect read and write access to the limit address of the currently selected MPU... 816 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... 817 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... 818 // 0x00000001 [0] EN (0) Region enable 819 io_rw_32 mpu_rlar_a1; 820 821 _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2 822 // Provides indirect read and write access to the base address of the MPU region selected by... 823 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... 824 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory 825 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region 826 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region 827 io_rw_32 mpu_rbar_a2; 828 829 _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2 830 // Provides indirect read and write access to the limit address of the currently selected MPU... 831 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... 832 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... 833 // 0x00000001 [0] EN (0) Region enable 834 io_rw_32 mpu_rlar_a2; 835 836 _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3 837 // Provides indirect read and write access to the base address of the MPU region selected by... 838 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... 839 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory 840 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region 841 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region 842 io_rw_32 mpu_rbar_a3; 843 844 _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3 845 // Provides indirect read and write access to the limit address of the currently selected MPU... 846 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... 847 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... 848 // 0x00000001 [0] EN (0) Region enable 849 io_rw_32 mpu_rlar_a3; 850 851 uint32_t _pad35; 852 853 // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) 854 _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 855 // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values 856 // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3 857 // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2 858 // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1 859 // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 860 io_rw_32 mpu_mair[2]; 861 862 uint32_t _pad36[2]; 863 864 _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL 865 // Allows enabling of the Security Attribution Unit 866 // 0x00000002 [1] ALLNS (0) When SAU_CTRL 867 // 0x00000001 [0] ENABLE (0) Enables the SAU 868 io_rw_32 sau_ctrl; 869 870 _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE 871 // Indicates the number of regions implemented by the Security Attribution Unit 872 // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions 873 io_ro_32 sau_type; 874 875 _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR 876 // Selects the region currently accessed by SAU_RBAR and SAU_RLAR 877 // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR 878 io_rw_32 sau_rnr; 879 880 _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR 881 // Provides indirect read and write access to the base address of the currently selected SAU region 882 // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region 883 io_rw_32 sau_rbar; 884 885 _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR 886 // Provides indirect read and write access to the limit address of the currently selected SAU region 887 // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected... 888 // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to... 889 // 0x00000001 [0] ENABLE (0) SAU region enable 890 io_rw_32 sau_rlar; 891 892 _REG_(M33_SFSR_OFFSET) // M33_SFSR 893 // Provides information about any security related faults 894 // 0x00000080 [7] LSERR (0) Sticky flag indicating that an error occurred during... 895 // 0x00000040 [6] SFARVALID (0) This bit is set when the SFAR register contains a valid value 896 // 0x00000020 [5] LSPERR (0) Stick flag indicating that an SAU or IDAU violation... 897 // 0x00000010 [4] INVTRAN (0) Sticky flag indicating that an exception was raised due... 898 // 0x00000008 [3] AUVIOL (0) Sticky flag indicating that an attempt was made to... 899 // 0x00000004 [2] INVER (0) This can be caused by EXC_RETURN 900 // 0x00000002 [1] INVIS (0) This bit is set if the integrity signature in an... 901 // 0x00000001 [0] INVEP (0) This bit is set if a function call from the Non-secure... 902 io_rw_32 sfsr; 903 904 _REG_(M33_SFAR_OFFSET) // M33_SFAR 905 // Shows the address of the memory location that caused a Security violation 906 // 0xffffffff [31:0] ADDRESS (0x00000000) The address of an access that caused a attribution unit violation 907 io_rw_32 sfar; 908 909 uint32_t _pad37; 910 911 _REG_(M33_DHCSR_OFFSET) // M33_DHCSR 912 // Controls halting debug 913 // 0x04000000 [26] S_RESTART_ST (0) Indicates the PE has processed a request to clear DHCSR 914 // 0x02000000 [25] S_RESET_ST (0) Indicates whether the PE has been reset since the last... 915 // 0x01000000 [24] S_RETIRE_ST (0) Set to 1 every time the PE retires one of more instructions 916 // 0x00100000 [20] S_SDE (0) Indicates whether Secure invasive debug is allowed 917 // 0x00080000 [19] S_LOCKUP (0) Indicates whether the PE is in Lockup state 918 // 0x00040000 [18] S_SLEEP (0) Indicates whether the PE is sleeping 919 // 0x00020000 [17] S_HALT (0) Indicates whether the PE is in Debug state 920 // 0x00010000 [16] S_REGRDY (0) Handshake flag to transfers through the DCRDR 921 // 0x00000020 [5] C_SNAPSTALL (0) Allow imprecise entry to Debug state 922 // 0x00000008 [3] C_MASKINTS (0) When debug is enabled, the debugger can write to this... 923 // 0x00000004 [2] C_STEP (0) Enable single instruction step 924 // 0x00000002 [1] C_HALT (0) PE enter Debug state halt request 925 // 0x00000001 [0] C_DEBUGEN (0) Enable Halting debug 926 io_rw_32 dhcsr; 927 928 _REG_(M33_DCRSR_OFFSET) // M33_DCRSR 929 // With the DCRDR, provides debug access to the general-purpose registers, special-purpose... 930 // 0x00010000 [16] REGWNR (0) Specifies the access type for the transfer 931 // 0x0000007f [6:0] REGSEL (0x00) Specifies the general-purpose register, special-purpose... 932 io_rw_32 dcrsr; 933 934 _REG_(M33_DCRDR_OFFSET) // M33_DCRDR 935 // With the DCRSR, provides debug access to the general-purpose registers, special-purpose... 936 // 0xffffffff [31:0] DBGTMP (0x00000000) Provides debug access for reading and writing the... 937 io_rw_32 dcrdr; 938 939 _REG_(M33_DEMCR_OFFSET) // M33_DEMCR 940 // Manages vector catch behavior and DebugMonitor handling when debugging 941 // 0x01000000 [24] TRCENA (0) Global enable for all DWT and ITM features 942 // 0x00100000 [20] SDME (0) Indicates whether the DebugMonitor targets the Secure or... 943 // 0x00080000 [19] MON_REQ (0) DebugMonitor semaphore bit 944 // 0x00040000 [18] MON_STEP (0) Enable DebugMonitor stepping 945 // 0x00020000 [17] MON_PEND (0) Sets or clears the pending state of the DebugMonitor exception 946 // 0x00010000 [16] MON_EN (0) Enable the DebugMonitor exception 947 // 0x00000800 [11] VC_SFERR (0) SecureFault exception halting debug vector catch enable 948 // 0x00000400 [10] VC_HARDERR (0) HardFault exception halting debug vector catch enable 949 // 0x00000200 [9] VC_INTERR (0) Enable halting debug vector catch for faults during... 950 // 0x00000100 [8] VC_BUSERR (0) BusFault exception halting debug vector catch enable 951 // 0x00000080 [7] VC_STATERR (0) Enable halting debug trap on a UsageFault exception... 952 // 0x00000040 [6] VC_CHKERR (0) Enable halting debug trap on a UsageFault exception... 953 // 0x00000020 [5] VC_NOCPERR (0) Enable halting debug trap on a UsageFault caused by an... 954 // 0x00000010 [4] VC_MMERR (0) Enable halting debug trap on a MemManage exception 955 // 0x00000001 [0] VC_CORERESET (0) Enable Reset Vector Catch 956 io_rw_32 demcr; 957 958 uint32_t _pad38[2]; 959 960 _REG_(M33_DSCSR_OFFSET) // M33_DSCSR 961 // Provides control and status information for Secure debug 962 // 0x00020000 [17] CDSKEY (0) Writes to the CDS bit are ignored unless CDSKEY is... 963 // 0x00010000 [16] CDS (0) This field indicates the current Security state of the processor 964 // 0x00000002 [1] SBRSEL (0) If SBRSELEN is 1 this bit selects whether the Non-secure... 965 // 0x00000001 [0] SBRSELEN (0) Controls whether the SBRSEL field or the current... 966 io_rw_32 dscsr; 967 968 uint32_t _pad39[61]; 969 970 _REG_(M33_STIR_OFFSET) // M33_STIR 971 // Provides a mechanism for software to generate an interrupt 972 // 0x000001ff [8:0] INTID (0x000) Indicates the interrupt to be pended 973 io_rw_32 stir; 974 975 uint32_t _pad40[12]; 976 977 _REG_(M33_FPCCR_OFFSET) // M33_FPCCR 978 // Holds control data for the Floating-point extension 979 // 0x80000000 [31] ASPEN (0) When this bit is set to 1, execution of a floating-point... 980 // 0x40000000 [30] LSPEN (0) Enables lazy context save of floating-point state 981 // 0x20000000 [29] LSPENS (1) This bit controls whether the LSPEN bit is writeable... 982 // 0x10000000 [28] CLRONRET (0) Clear floating-point caller saved registers on exception return 983 // 0x08000000 [27] CLRONRETS (0) This bit controls whether the CLRONRET bit is writeable... 984 // 0x04000000 [26] TS (0) Treat floating-point registers as Secure enable 985 // 0x00000400 [10] UFRDY (1) Indicates whether the software executing when the PE... 986 // 0x00000200 [9] SPLIMVIOL (0) This bit is banked between the Security states and... 987 // 0x00000100 [8] MONRDY (0) Indicates whether the software executing when the PE... 988 // 0x00000080 [7] SFRDY (0) Indicates whether the software executing when the PE... 989 // 0x00000040 [6] BFRDY (1) Indicates whether the software executing when the PE... 990 // 0x00000020 [5] MMRDY (1) Indicates whether the software executing when the PE... 991 // 0x00000010 [4] HFRDY (1) Indicates whether the software executing when the PE... 992 // 0x00000008 [3] THREAD (0) Indicates the PE mode when it allocated the... 993 // 0x00000004 [2] S (0) Security status of the floating-point context 994 // 0x00000002 [1] USER (1) Indicates the privilege level of the software executing... 995 // 0x00000001 [0] LSPACT (0) Indicates whether lazy preservation of the... 996 io_rw_32 fpccr; 997 998 _REG_(M33_FPCAR_OFFSET) // M33_FPCAR 999 // Holds the location of the unpopulated floating-point register space allocated on an exception stack frame 1000 // 0xfffffff8 [31:3] ADDRESS (0x00000000) The location of the unpopulated floating-point register... 1001 io_rw_32 fpcar; 1002 1003 _REG_(M33_FPDSCR_OFFSET) // M33_FPDSCR 1004 // Holds the default values for the floating-point status control data that the PE assigns to the... 1005 // 0x04000000 [26] AHP (0) Default value for FPSCR 1006 // 0x02000000 [25] DN (0) Default value for FPSCR 1007 // 0x01000000 [24] FZ (0) Default value for FPSCR 1008 // 0x00c00000 [23:22] RMODE (0x0) Default value for FPSCR 1009 io_rw_32 fpdscr; 1010 1011 // (Description copied from array index 0 register M33_MVFR0 applies similarly to other array indexes) 1012 _REG_(M33_MVFR0_OFFSET) // M33_MVFR0 1013 // Describes the features provided by the Floating-point Extension 1014 // 0xf0000000 [31:28] FPROUND (0x6) Indicates the rounding modes supported by the FP Extension 1015 // 0x00f00000 [23:20] FPSQRT (0x5) Indicates the support for FP square root operations 1016 // 0x000f0000 [19:16] FPDIVIDE (0x4) Indicates the support for FP divide operations 1017 // 0x00000f00 [11:8] FPDP (0x6) Indicates support for FP double-precision operations 1018 // 0x000000f0 [7:4] FPSP (0x0) Indicates support for FP single-precision operations 1019 // 0x0000000f [3:0] SIMDREG (0x1) Indicates size of FP register file 1020 io_ro_32 mvfr[3]; 1021 1022 uint32_t _pad41[28]; 1023 1024 _REG_(M33_DDEVARCH_OFFSET) // M33_DDEVARCH 1025 // Provides CoreSight discovery information for the SCS 1026 // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component 1027 // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present 1028 // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component 1029 // 0x0000f000 [15:12] ARCHVER (0x2) Defines the architecture version of the component 1030 // 0x00000fff [11:0] ARCHPART (0xa04) Defines the architecture of the component 1031 io_ro_32 ddevarch; 1032 1033 uint32_t _pad42[3]; 1034 1035 _REG_(M33_DDEVTYPE_OFFSET) // M33_DDEVTYPE 1036 // Provides CoreSight discovery information for the SCS 1037 // 0x000000f0 [7:4] SUB (0x0) Component sub-type 1038 // 0x0000000f [3:0] MAJOR (0x0) CoreSight major type 1039 io_ro_32 ddevtype; 1040 1041 _REG_(M33_DPIDR4_OFFSET) // M33_DPIDR4 1042 // Provides CoreSight discovery information for the SCS 1043 // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification 1044 // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification 1045 io_ro_32 dpidr4; 1046 1047 _REG_(M33_DPIDR5_OFFSET) // M33_DPIDR5 1048 // Provides CoreSight discovery information for the SCS 1049 // 0x00000000 [31:0] DPIDR5 (0x00000000) 1050 io_rw_32 dpidr5; 1051 1052 _REG_(M33_DPIDR6_OFFSET) // M33_DPIDR6 1053 // Provides CoreSight discovery information for the SCS 1054 // 0x00000000 [31:0] DPIDR6 (0x00000000) 1055 io_rw_32 dpidr6; 1056 1057 _REG_(M33_DPIDR7_OFFSET) // M33_DPIDR7 1058 // Provides CoreSight discovery information for the SCS 1059 // 0x00000000 [31:0] DPIDR7 (0x00000000) 1060 io_rw_32 dpidr7; 1061 1062 _REG_(M33_DPIDR0_OFFSET) // M33_DPIDR0 1063 // Provides CoreSight discovery information for the SCS 1064 // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification 1065 io_ro_32 dpidr0; 1066 1067 _REG_(M33_DPIDR1_OFFSET) // M33_DPIDR1 1068 // Provides CoreSight discovery information for the SCS 1069 // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification 1070 // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification 1071 io_ro_32 dpidr1; 1072 1073 _REG_(M33_DPIDR2_OFFSET) // M33_DPIDR2 1074 // Provides CoreSight discovery information for the SCS 1075 // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification 1076 // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification 1077 // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification 1078 io_ro_32 dpidr2; 1079 1080 _REG_(M33_DPIDR3_OFFSET) // M33_DPIDR3 1081 // Provides CoreSight discovery information for the SCS 1082 // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification 1083 // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification 1084 io_ro_32 dpidr3; 1085 1086 // (Description copied from array index 0 register M33_DCIDR0 applies similarly to other array indexes) 1087 _REG_(M33_DCIDR0_OFFSET) // M33_DCIDR0 1088 // Provides CoreSight discovery information for the SCS 1089 // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification 1090 io_ro_32 dcidr[4]; 1091 1092 uint32_t _pad43[51201]; 1093 1094 _REG_(M33_TRCPRGCTLR_OFFSET) // M33_TRCPRGCTLR 1095 // Programming Control Register 1096 // 0x00000001 [0] EN (0) Trace Unit Enable 1097 io_rw_32 trcprgctlr; 1098 1099 uint32_t _pad44; 1100 1101 _REG_(M33_TRCSTATR_OFFSET) // M33_TRCSTATR 1102 // The TRCSTATR indicates the ETM-Teal status 1103 // 0x00000002 [1] PMSTABLE (0) Indicates whether the ETM-Teal registers are stable and... 1104 // 0x00000001 [0] IDLE (0) Indicates that the trace unit is inactive 1105 io_ro_32 trcstatr; 1106 1107 _REG_(M33_TRCCONFIGR_OFFSET) // M33_TRCCONFIGR 1108 // The TRCCONFIGR sets the basic tracing options for the trace unit 1109 // 0x00001000 [12] RS (0) Return stack enable 1110 // 0x00000800 [11] TS (0) Global timestamp tracing 1111 // 0x000007e0 [10:5] COND (0x00) Conditional instruction tracing 1112 // 0x00000010 [4] CCI (0) Cycle counting in instruction trace 1113 // 0x00000008 [3] BB (0) Branch broadcast mode 1114 io_rw_32 trcconfigr; 1115 1116 uint32_t _pad45[3]; 1117 1118 _REG_(M33_TRCEVENTCTL0R_OFFSET) // M33_TRCEVENTCTL0R 1119 // The TRCEVENTCTL0R controls the tracing of events in the trace stream 1120 // 0x00008000 [15] TYPE1 (0) Selects the resource type for event 1 1121 // 0x00000700 [10:8] SEL1 (0x0) Selects the resource number, based on the value of... 1122 // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 1123 // 0x00000007 [2:0] SEL0 (0x0) Selects the resource number, based on the value of... 1124 io_rw_32 trceventctl0r; 1125 1126 _REG_(M33_TRCEVENTCTL1R_OFFSET) // M33_TRCEVENTCTL1R 1127 // The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave 1128 // 0x00001000 [12] LPOVERRIDE (0) Low power state behavior override 1129 // 0x00000800 [11] ATB (0) ATB enabled 1130 // 0x00000002 [1] INSTEN1 (0) One bit per event, to enable generation of an event... 1131 // 0x00000001 [0] INSTEN0 (0) One bit per event, to enable generation of an event... 1132 io_rw_32 trceventctl1r; 1133 1134 uint32_t _pad46; 1135 1136 _REG_(M33_TRCSTALLCTLR_OFFSET) // M33_TRCSTALLCTLR 1137 // The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the... 1138 // 0x00000400 [10] INSTPRIORITY (0) Reserved, RES0 1139 // 0x00000100 [8] ISTALL (0) Stall processor based on instruction trace buffer space 1140 // 0x0000000c [3:2] LEVEL (0x0) Threshold at which stalling becomes active 1141 io_rw_32 trcstallctlr; 1142 1143 _REG_(M33_TRCTSCTLR_OFFSET) // M33_TRCTSCTLR 1144 // The TRCTSCTLR controls the insertion of global timestamps into the trace stream 1145 // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 1146 // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... 1147 io_rw_32 trctsctlr; 1148 1149 _REG_(M33_TRCSYNCPR_OFFSET) // M33_TRCSYNCPR 1150 // The TRCSYNCPR specifies the period of trace synchronization of the trace streams 1151 // 0x0000001f [4:0] PERIOD (0x0a) Defines the number of bytes of trace between trace... 1152 io_ro_32 trcsyncpr; 1153 1154 _REG_(M33_TRCCCCTLR_OFFSET) // M33_TRCCCCTLR 1155 // The TRCCCCTLR sets the threshold value for instruction trace cycle counting 1156 // 0x00000fff [11:0] THRESHOLD (0x000) Instruction trace cycle count threshold 1157 io_rw_32 trcccctlr; 1158 1159 uint32_t _pad47[17]; 1160 1161 _REG_(M33_TRCVICTLR_OFFSET) // M33_TRCVICTLR 1162 // The TRCVICTLR controls instruction trace filtering 1163 // 0x00080000 [19] EXLEVEL_S3 (0) In Secure state, each bit controls whether instruction... 1164 // 0x00010000 [16] EXLEVEL_S0 (0) In Secure state, each bit controls whether instruction... 1165 // 0x00000800 [11] TRCERR (0) Selects whether a system error exception must always be traced 1166 // 0x00000400 [10] TRCRESET (0) Selects whether a reset exception must always be traced 1167 // 0x00000200 [9] SSSTATUS (0) Indicates the current status of the start/stop logic 1168 // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 1169 // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... 1170 io_rw_32 trcvictlr; 1171 1172 uint32_t _pad48[47]; 1173 1174 _REG_(M33_TRCCNTRLDVR0_OFFSET) // M33_TRCCNTRLDVR0 1175 // The TRCCNTRLDVR defines the reload value for the reduced function counter 1176 // 0x0000ffff [15:0] VALUE (0x0000) Defines the reload value for the counter 1177 io_rw_32 trccntrldvr0; 1178 1179 uint32_t _pad49[15]; 1180 1181 _REG_(M33_TRCIDR8_OFFSET) // M33_TRCIDR8 1182 // TRCIDR8 1183 // 0xffffffff [31:0] MAXSPEC (0x00000000) reads as `ImpDef 1184 io_ro_32 trcidr8; 1185 1186 _REG_(M33_TRCIDR9_OFFSET) // M33_TRCIDR9 1187 // TRCIDR9 1188 // 0xffffffff [31:0] NUMP0KEY (0x00000000) reads as `ImpDef 1189 io_ro_32 trcidr9; 1190 1191 _REG_(M33_TRCIDR10_OFFSET) // M33_TRCIDR10 1192 // TRCIDR10 1193 // 0xffffffff [31:0] NUMP1KEY (0x00000000) reads as `ImpDef 1194 io_ro_32 trcidr10; 1195 1196 _REG_(M33_TRCIDR11_OFFSET) // M33_TRCIDR11 1197 // TRCIDR11 1198 // 0xffffffff [31:0] NUMP1SPC (0x00000000) reads as `ImpDef 1199 io_ro_32 trcidr11; 1200 1201 _REG_(M33_TRCIDR12_OFFSET) // M33_TRCIDR12 1202 // TRCIDR12 1203 // 0xffffffff [31:0] NUMCONDKEY (0x00000001) reads as `ImpDef 1204 io_ro_32 trcidr12; 1205 1206 _REG_(M33_TRCIDR13_OFFSET) // M33_TRCIDR13 1207 // TRCIDR13 1208 // 0xffffffff [31:0] NUMCONDSPC (0x00000000) reads as `ImpDef 1209 io_ro_32 trcidr13; 1210 1211 uint32_t _pad50[10]; 1212 1213 _REG_(M33_TRCIMSPEC_OFFSET) // M33_TRCIMSPEC 1214 // The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any... 1215 // 0x0000000f [3:0] SUPPORT (0x0) Reserved, RES0 1216 io_ro_32 trcimspec; 1217 1218 uint32_t _pad51[7]; 1219 1220 _REG_(M33_TRCIDR0_OFFSET) // M33_TRCIDR0 1221 // TRCIDR0 1222 // 0x20000000 [29] COMMOPT (1) reads as `ImpDef 1223 // 0x1f000000 [28:24] TSSIZE (0x08) reads as `ImpDef 1224 // 0x00020000 [17] TRCEXDATA (0) reads as `ImpDef 1225 // 0x00018000 [16:15] QSUPP (0x0) reads as `ImpDef 1226 // 0x00004000 [14] QFILT (0) reads as `ImpDef 1227 // 0x00003000 [13:12] CONDTYPE (0x0) reads as `ImpDef 1228 // 0x00000c00 [11:10] NUMEVENT (0x1) reads as `ImpDef 1229 // 0x00000200 [9] RETSTACK (1) reads as `ImpDef 1230 // 0x00000080 [7] TRCCCI (1) reads as `ImpDef 1231 // 0x00000040 [6] TRCCOND (1) reads as `ImpDef 1232 // 0x00000020 [5] TRCBB (1) reads as `ImpDef 1233 // 0x00000018 [4:3] TRCDATA (0x0) reads as `ImpDef 1234 // 0x00000006 [2:1] INSTP0 (0x0) reads as `ImpDef 1235 // 0x00000001 [0] RES1 (1) Reserved, RES1 1236 io_ro_32 trcidr0; 1237 1238 _REG_(M33_TRCIDR1_OFFSET) // M33_TRCIDR1 1239 // TRCIDR1 1240 // 0xff000000 [31:24] DESIGNER (0x41) reads as `ImpDef 1241 // 0x0000f000 [15:12] RES1 (0xf) Reserved, RES1 1242 // 0x00000f00 [11:8] TRCARCHMAJ (0x4) reads as 0b0100 1243 // 0x000000f0 [7:4] TRCARCHMIN (0x2) reads as 0b0000 1244 // 0x0000000f [3:0] REVISION (0x1) reads as `ImpDef 1245 io_ro_32 trcidr1; 1246 1247 _REG_(M33_TRCIDR2_OFFSET) // M33_TRCIDR2 1248 // TRCIDR2 1249 // 0x1e000000 [28:25] CCSIZE (0x0) reads as `ImpDef 1250 // 0x01f00000 [24:20] DVSIZE (0x00) reads as `ImpDef 1251 // 0x000f8000 [19:15] DASIZE (0x00) reads as `ImpDef 1252 // 0x00007c00 [14:10] VMIDSIZE (0x00) reads as `ImpDef 1253 // 0x000003e0 [9:5] CIDSIZE (0x00) reads as `ImpDef 1254 // 0x0000001f [4:0] IASIZE (0x04) reads as `ImpDef 1255 io_ro_32 trcidr2; 1256 1257 _REG_(M33_TRCIDR3_OFFSET) // M33_TRCIDR3 1258 // TRCIDR3 1259 // 0x80000000 [31] NOOVERFLOW (0) reads as `ImpDef 1260 // 0x70000000 [30:28] NUMPROC (0x0) reads as `ImpDef 1261 // 0x08000000 [27] SYSSTALL (1) reads as `ImpDef 1262 // 0x04000000 [26] STALLCTL (1) reads as `ImpDef 1263 // 0x02000000 [25] SYNCPR (1) reads as `ImpDef 1264 // 0x01000000 [24] TRCERR (1) reads as `ImpDef 1265 // 0x00f00000 [23:20] EXLEVEL_NS (0x0) reads as `ImpDef 1266 // 0x000f0000 [19:16] EXLEVEL_S (0x9) reads as `ImpDef 1267 // 0x00000fff [11:0] CCITMIN (0x004) reads as `ImpDef 1268 io_ro_32 trcidr3; 1269 1270 _REG_(M33_TRCIDR4_OFFSET) // M33_TRCIDR4 1271 // TRCIDR4 1272 // 0xf0000000 [31:28] NUMVMIDC (0x0) reads as `ImpDef 1273 // 0x0f000000 [27:24] NUMCIDC (0x0) reads as `ImpDef 1274 // 0x00f00000 [23:20] NUMSSCC (0x1) reads as `ImpDef 1275 // 0x000f0000 [19:16] NUMRSPAIR (0x1) reads as `ImpDef 1276 // 0x0000f000 [15:12] NUMPC (0x4) reads as `ImpDef 1277 // 0x00000100 [8] SUPPDAC (0) reads as `ImpDef 1278 // 0x000000f0 [7:4] NUMDVC (0x0) reads as `ImpDef 1279 // 0x0000000f [3:0] NUMACPAIRS (0x0) reads as `ImpDef 1280 io_ro_32 trcidr4; 1281 1282 _REG_(M33_TRCIDR5_OFFSET) // M33_TRCIDR5 1283 // TRCIDR5 1284 // 0x80000000 [31] REDFUNCNTR (1) reads as `ImpDef 1285 // 0x70000000 [30:28] NUMCNTR (0x1) reads as `ImpDef 1286 // 0x0e000000 [27:25] NUMSEQSTATE (0x0) reads as `ImpDef 1287 // 0x00800000 [23] LPOVERRIDE (1) reads as `ImpDef 1288 // 0x00400000 [22] ATBTRIG (1) reads as `ImpDef 1289 // 0x003f0000 [21:16] TRACEIDSIZE (0x07) reads as 0x07 1290 // 0x00000e00 [11:9] NUMEXTINSEL (0x0) reads as `ImpDef 1291 // 0x000001ff [8:0] NUMEXTIN (0x004) reads as `ImpDef 1292 io_ro_32 trcidr5; 1293 1294 _REG_(M33_TRCIDR6_OFFSET) // M33_TRCIDR6 1295 // TRCIDR6 1296 // 0x00000000 [31:0] TRCIDR6 (0x00000000) 1297 io_rw_32 trcidr6; 1298 1299 _REG_(M33_TRCIDR7_OFFSET) // M33_TRCIDR7 1300 // TRCIDR7 1301 // 0x00000000 [31:0] TRCIDR7 (0x00000000) 1302 io_rw_32 trcidr7; 1303 1304 uint32_t _pad52[2]; 1305 1306 // (Description copied from array index 0 register M33_TRCRSCTLR2 applies similarly to other array indexes) 1307 _REG_(M33_TRCRSCTLR2_OFFSET) // M33_TRCRSCTLR2 1308 // The TRCRSCTLR controls the trace resources 1309 // 0x00200000 [21] PAIRINV (0) Inverts the result of a combined pair of resources 1310 // 0x00100000 [20] INV (0) Inverts the selected resources 1311 // 0x00070000 [18:16] GROUP (0x0) Selects a group of resource 1312 // 0x000000ff [7:0] SELECT (0x00) Selects one or more resources from the wanted group 1313 io_rw_32 trcrsctlr[2]; 1314 1315 uint32_t _pad53[36]; 1316 1317 _REG_(M33_TRCSSCSR_OFFSET) // M33_TRCSSCSR 1318 // Controls the corresponding single-shot comparator resource 1319 // 0x80000000 [31] STATUS (0) Single-shot status bit 1320 // 0x00000008 [3] PC (0) Reserved, RES1 1321 // 0x00000004 [2] DV (0) Reserved, RES0 1322 // 0x00000002 [1] DA (0) Reserved, RES0 1323 // 0x00000001 [0] INST (0) Reserved, RES0 1324 io_rw_32 trcsscsr; 1325 1326 uint32_t _pad54[7]; 1327 1328 _REG_(M33_TRCSSPCICR_OFFSET) // M33_TRCSSPCICR 1329 // Selects the PE comparator inputs for Single-shot control 1330 // 0x0000000f [3:0] PC (0x0) Selects one or more PE comparator inputs for Single-shot control 1331 io_rw_32 trcsspcicr; 1332 1333 uint32_t _pad55[19]; 1334 1335 _REG_(M33_TRCPDCR_OFFSET) // M33_TRCPDCR 1336 // Requests the system to provide power to the trace unit 1337 // 0x00000008 [3] PU (0) Powerup request bit: 1338 io_rw_32 trcpdcr; 1339 1340 _REG_(M33_TRCPDSR_OFFSET) // M33_TRCPDSR 1341 // Returns the following information about the trace unit: - OS Lock status 1342 // 0x00000020 [5] OSLK (0) OS Lock status bit: 1343 // 0x00000002 [1] STICKYPD (1) Sticky powerdown status bit 1344 // 0x00000001 [0] POWER (1) Power status bit: 1345 io_ro_32 trcpdsr; 1346 1347 uint32_t _pad56[755]; 1348 1349 _REG_(M33_TRCITATBIDR_OFFSET) // M33_TRCITATBIDR 1350 // Trace Integration ATB Identification Register 1351 // 0x0000007f [6:0] ID (0x00) Trace ID 1352 io_rw_32 trcitatbidr; 1353 1354 uint32_t _pad57[3]; 1355 1356 _REG_(M33_TRCITIATBINR_OFFSET) // M33_TRCITIATBINR 1357 // Trace Integration Instruction ATB In Register 1358 // 0x00000002 [1] AFVALIDM (0) Integration Mode instruction AFVALIDM in 1359 // 0x00000001 [0] ATREADYM (0) Integration Mode instruction ATREADYM in 1360 io_rw_32 trcitiatbinr; 1361 1362 uint32_t _pad58; 1363 1364 _REG_(M33_TRCITIATBOUTR_OFFSET) // M33_TRCITIATBOUTR 1365 // Trace Integration Instruction ATB Out Register 1366 // 0x00000002 [1] AFREADY (0) Integration Mode instruction AFREADY out 1367 // 0x00000001 [0] ATVALID (0) Integration Mode instruction ATVALID out 1368 io_rw_32 trcitiatboutr; 1369 1370 uint32_t _pad59[40]; 1371 1372 _REG_(M33_TRCCLAIMSET_OFFSET) // M33_TRCCLAIMSET 1373 // Claim Tag Set Register 1374 // 0x00000008 [3] SET3 (1) When a write to one of these bits occurs, with the value: 1375 // 0x00000004 [2] SET2 (1) When a write to one of these bits occurs, with the value: 1376 // 0x00000002 [1] SET1 (1) When a write to one of these bits occurs, with the value: 1377 // 0x00000001 [0] SET0 (1) When a write to one of these bits occurs, with the value: 1378 io_rw_32 trcclaimset; 1379 1380 _REG_(M33_TRCCLAIMCLR_OFFSET) // M33_TRCCLAIMCLR 1381 // Claim Tag Clear Register 1382 // 0x00000008 [3] CLR3 (0) When a write to one of these bits occurs, with the value: 1383 // 0x00000004 [2] CLR2 (0) When a write to one of these bits occurs, with the value: 1384 // 0x00000002 [1] CLR1 (0) When a write to one of these bits occurs, with the value: 1385 // 0x00000001 [0] CLR0 (0) When a write to one of these bits occurs, with the value: 1386 io_rw_32 trcclaimclr; 1387 1388 uint32_t _pad60[4]; 1389 1390 _REG_(M33_TRCAUTHSTATUS_OFFSET) // M33_TRCAUTHSTATUS 1391 // Returns the level of tracing that the trace unit can support 1392 // 0x000000c0 [7:6] SNID (0x0) Indicates whether the system enables the trace unit to... 1393 // 0x00000030 [5:4] SID (0x0) Indicates whether the trace unit supports Secure invasive debug: 1394 // 0x0000000c [3:2] NSNID (0x0) Indicates whether the system enables the trace unit to... 1395 // 0x00000003 [1:0] NSID (0x0) Indicates whether the trace unit supports Non-secure... 1396 io_ro_32 trcauthstatus; 1397 1398 _REG_(M33_TRCDEVARCH_OFFSET) // M33_TRCDEVARCH 1399 // TRCDEVARCH 1400 // 0xffe00000 [31:21] ARCHITECT (0x23b) reads as 0b01000111011 1401 // 0x00100000 [20] PRESENT (1) reads as 0b1 1402 // 0x000f0000 [19:16] REVISION (0x2) reads as 0b0000 1403 // 0x0000ffff [15:0] ARCHID (0x4a13) reads as 0b0100101000010011 1404 io_ro_32 trcdevarch; 1405 1406 uint32_t _pad61[2]; 1407 1408 _REG_(M33_TRCDEVID_OFFSET) // M33_TRCDEVID 1409 // TRCDEVID 1410 // 0x00000000 [31:0] TRCDEVID (0x00000000) 1411 io_rw_32 trcdevid; 1412 1413 _REG_(M33_TRCDEVTYPE_OFFSET) // M33_TRCDEVTYPE 1414 // TRCDEVTYPE 1415 // 0x000000f0 [7:4] SUB (0x1) reads as 0b0001 1416 // 0x0000000f [3:0] MAJOR (0x3) reads as 0b0011 1417 io_ro_32 trcdevtype; 1418 1419 _REG_(M33_TRCPIDR4_OFFSET) // M33_TRCPIDR4 1420 // TRCPIDR4 1421 // 0x000000f0 [7:4] SIZE (0x0) reads as `ImpDef 1422 // 0x0000000f [3:0] DES_2 (0x4) reads as `ImpDef 1423 io_ro_32 trcpidr4; 1424 1425 _REG_(M33_TRCPIDR5_OFFSET) // M33_TRCPIDR5 1426 // TRCPIDR5 1427 // 0x00000000 [31:0] TRCPIDR5 (0x00000000) 1428 io_rw_32 trcpidr5; 1429 1430 _REG_(M33_TRCPIDR6_OFFSET) // M33_TRCPIDR6 1431 // TRCPIDR6 1432 // 0x00000000 [31:0] TRCPIDR6 (0x00000000) 1433 io_rw_32 trcpidr6; 1434 1435 _REG_(M33_TRCPIDR7_OFFSET) // M33_TRCPIDR7 1436 // TRCPIDR7 1437 // 0x00000000 [31:0] TRCPIDR7 (0x00000000) 1438 io_rw_32 trcpidr7; 1439 1440 _REG_(M33_TRCPIDR0_OFFSET) // M33_TRCPIDR0 1441 // TRCPIDR0 1442 // 0x000000ff [7:0] PART_0 (0x21) reads as `ImpDef 1443 io_ro_32 trcpidr0; 1444 1445 _REG_(M33_TRCPIDR1_OFFSET) // M33_TRCPIDR1 1446 // TRCPIDR1 1447 // 0x000000f0 [7:4] DES_0 (0xb) reads as `ImpDef 1448 // 0x0000000f [3:0] PART_0 (0xd) reads as `ImpDef 1449 io_ro_32 trcpidr1; 1450 1451 _REG_(M33_TRCPIDR2_OFFSET) // M33_TRCPIDR2 1452 // TRCPIDR2 1453 // 0x000000f0 [7:4] REVISION (0x2) reads as `ImpDef 1454 // 0x00000008 [3] JEDEC (1) reads as 0b1 1455 // 0x00000007 [2:0] DES_0 (0x3) reads as `ImpDef 1456 io_ro_32 trcpidr2; 1457 1458 _REG_(M33_TRCPIDR3_OFFSET) // M33_TRCPIDR3 1459 // TRCPIDR3 1460 // 0x000000f0 [7:4] REVAND (0x0) reads as `ImpDef 1461 // 0x0000000f [3:0] CMOD (0x0) reads as `ImpDef 1462 io_ro_32 trcpidr3; 1463 1464 // (Description copied from array index 0 register M33_TRCCIDR0 applies similarly to other array indexes) 1465 _REG_(M33_TRCCIDR0_OFFSET) // M33_TRCCIDR0 1466 // TRCCIDR0 1467 // 0x000000ff [7:0] PRMBL_0 (0x0d) reads as 0b00001101 1468 io_ro_32 trccidr[4]; 1469 1470 _REG_(M33_CTICONTROL_OFFSET) // M33_CTICONTROL 1471 // CTI Control Register 1472 // 0x00000001 [0] GLBEN (0) Enables or disables the CTI 1473 io_rw_32 cticontrol; 1474 1475 uint32_t _pad62[3]; 1476 1477 _REG_(M33_CTIINTACK_OFFSET) // M33_CTIINTACK 1478 // CTI Interrupt Acknowledge Register 1479 // 0x000000ff [7:0] INTACK (0x00) Acknowledges the corresponding ctitrigout output 1480 io_rw_32 ctiintack; 1481 1482 _REG_(M33_CTIAPPSET_OFFSET) // M33_CTIAPPSET 1483 // CTI Application Trigger Set Register 1484 // 0x0000000f [3:0] APPSET (0x0) Setting a bit HIGH generates a channel event for the... 1485 io_rw_32 ctiappset; 1486 1487 _REG_(M33_CTIAPPCLEAR_OFFSET) // M33_CTIAPPCLEAR 1488 // CTI Application Trigger Clear Register 1489 // 0x0000000f [3:0] APPCLEAR (0x0) Sets the corresponding bits in the CTIAPPSET to 0 1490 io_rw_32 ctiappclear; 1491 1492 _REG_(M33_CTIAPPPULSE_OFFSET) // M33_CTIAPPPULSE 1493 // CTI Application Pulse Register 1494 // 0x0000000f [3:0] APPULSE (0x0) Setting a bit HIGH generates a channel event pulse for... 1495 io_rw_32 ctiapppulse; 1496 1497 // (Description copied from array index 0 register M33_CTIINEN0 applies similarly to other array indexes) 1498 _REG_(M33_CTIINEN0_OFFSET) // M33_CTIINEN0 1499 // CTI Trigger to Channel Enable Registers 1500 // 0x0000000f [3:0] TRIGINEN (0x0) Enables a cross trigger event to the corresponding... 1501 io_rw_32 ctiinen[8]; 1502 1503 uint32_t _pad63[24]; 1504 1505 // (Description copied from array index 0 register M33_CTIOUTEN0 applies similarly to other array indexes) 1506 _REG_(M33_CTIOUTEN0_OFFSET) // M33_CTIOUTEN0 1507 // CTI Trigger to Channel Enable Registers 1508 // 0x0000000f [3:0] TRIGOUTEN (0x0) Enables a cross trigger event to ctitrigout when the... 1509 io_rw_32 ctiouten[8]; 1510 1511 uint32_t _pad64[28]; 1512 1513 _REG_(M33_CTITRIGINSTATUS_OFFSET) // M33_CTITRIGINSTATUS 1514 // CTI Trigger to Channel Enable Registers 1515 // 0x000000ff [7:0] TRIGINSTATUS (0x00) Shows the status of the ctitrigin inputs 1516 io_ro_32 ctitriginstatus; 1517 1518 _REG_(M33_CTITRIGOUTSTATUS_OFFSET) // M33_CTITRIGOUTSTATUS 1519 // CTI Trigger In Status Register 1520 // 0x000000ff [7:0] TRIGOUTSTATUS (0x00) Shows the status of the ctitrigout outputs 1521 io_ro_32 ctitrigoutstatus; 1522 1523 _REG_(M33_CTICHINSTATUS_OFFSET) // M33_CTICHINSTATUS 1524 // CTI Channel In Status Register 1525 // 0x0000000f [3:0] CTICHOUTSTATUS (0x0) Shows the status of the ctichout outputs 1526 io_ro_32 ctichinstatus; 1527 1528 uint32_t _pad65; 1529 1530 _REG_(M33_CTIGATE_OFFSET) // M33_CTIGATE 1531 // Enable CTI Channel Gate register 1532 // 0x00000008 [3] CTIGATEEN3 (1) Enable ctichout3 1533 // 0x00000004 [2] CTIGATEEN2 (1) Enable ctichout2 1534 // 0x00000002 [1] CTIGATEEN1 (1) Enable ctichout1 1535 // 0x00000001 [0] CTIGATEEN0 (1) Enable ctichout0 1536 io_rw_32 ctigate; 1537 1538 _REG_(M33_ASICCTL_OFFSET) // M33_ASICCTL 1539 // External Multiplexer Control register 1540 // 0x00000000 [31:0] ASICCTL (0x00000000) 1541 io_rw_32 asicctl; 1542 1543 uint32_t _pad66[871]; 1544 1545 _REG_(M33_ITCHOUT_OFFSET) // M33_ITCHOUT 1546 // Integration Test Channel Output register 1547 // 0x0000000f [3:0] CTCHOUT (0x0) Sets the value of the ctichout outputs 1548 io_rw_32 itchout; 1549 1550 _REG_(M33_ITTRIGOUT_OFFSET) // M33_ITTRIGOUT 1551 // Integration Test Trigger Output register 1552 // 0x000000ff [7:0] CTTRIGOUT (0x00) Sets the value of the ctitrigout outputs 1553 io_rw_32 ittrigout; 1554 1555 uint32_t _pad67[2]; 1556 1557 _REG_(M33_ITCHIN_OFFSET) // M33_ITCHIN 1558 // Integration Test Channel Input register 1559 // 0x0000000f [3:0] CTCHIN (0x0) Reads the value of the ctichin inputs 1560 io_ro_32 itchin; 1561 1562 uint32_t _pad68[2]; 1563 1564 _REG_(M33_ITCTRL_OFFSET) // M33_ITCTRL 1565 // Integration Mode Control register 1566 // 0x00000001 [0] IME (0) Integration Mode Enable 1567 io_rw_32 itctrl; 1568 1569 uint32_t _pad69[46]; 1570 1571 _REG_(M33_DEVARCH_OFFSET) // M33_DEVARCH 1572 // Device Architecture register 1573 // 0xffe00000 [31:21] ARCHITECT (0x23b) Indicates the component architect 1574 // 0x00100000 [20] PRESENT (1) Indicates whether the DEVARCH register is present 1575 // 0x000f0000 [19:16] REVISION (0x0) Indicates the architecture revision 1576 // 0x0000ffff [15:0] ARCHID (0x1a14) Indicates the component 1577 io_ro_32 devarch; 1578 1579 uint32_t _pad70[2]; 1580 1581 _REG_(M33_DEVID_OFFSET) // M33_DEVID 1582 // Device Configuration register 1583 // 0x000f0000 [19:16] NUMCH (0x4) Number of ECT channels available 1584 // 0x0000ff00 [15:8] NUMTRIG (0x08) Number of ECT triggers available 1585 // 0x0000001f [4:0] EXTMUXNUM (0x00) Indicates the number of multiplexers available on... 1586 io_ro_32 devid; 1587 1588 _REG_(M33_DEVTYPE_OFFSET) // M33_DEVTYPE 1589 // Device Type Identifier register 1590 // 0x000000f0 [7:4] SUB (0x1) Sub-classification of the type of the debug component as... 1591 // 0x0000000f [3:0] MAJOR (0x4) Major classification of the type of the debug component... 1592 io_ro_32 devtype; 1593 1594 _REG_(M33_PIDR4_OFFSET) // M33_PIDR4 1595 // CoreSight Peripheral ID4 1596 // 0x000000f0 [7:4] SIZE (0x0) Always 0b0000 1597 // 0x0000000f [3:0] DES_2 (0x4) Together, PIDR1 1598 io_ro_32 pidr4; 1599 1600 _REG_(M33_PIDR5_OFFSET) // M33_PIDR5 1601 // CoreSight Peripheral ID5 1602 // 0x00000000 [31:0] PIDR5 (0x00000000) 1603 io_rw_32 pidr5; 1604 1605 _REG_(M33_PIDR6_OFFSET) // M33_PIDR6 1606 // CoreSight Peripheral ID6 1607 // 0x00000000 [31:0] PIDR6 (0x00000000) 1608 io_rw_32 pidr6; 1609 1610 _REG_(M33_PIDR7_OFFSET) // M33_PIDR7 1611 // CoreSight Peripheral ID7 1612 // 0x00000000 [31:0] PIDR7 (0x00000000) 1613 io_rw_32 pidr7; 1614 1615 _REG_(M33_PIDR0_OFFSET) // M33_PIDR0 1616 // CoreSight Peripheral ID0 1617 // 0x000000ff [7:0] PART_0 (0x21) Bits[7:0] of the 12-bit part number of the component 1618 io_ro_32 pidr0; 1619 1620 _REG_(M33_PIDR1_OFFSET) // M33_PIDR1 1621 // CoreSight Peripheral ID1 1622 // 0x000000f0 [7:4] DES_0 (0xb) Together, PIDR1 1623 // 0x0000000f [3:0] PART_1 (0xd) Bits[11:8] of the 12-bit part number of the component 1624 io_ro_32 pidr1; 1625 1626 _REG_(M33_PIDR2_OFFSET) // M33_PIDR2 1627 // CoreSight Peripheral ID2 1628 // 0x000000f0 [7:4] REVISION (0x0) This device is at r1p0 1629 // 0x00000008 [3] JEDEC (1) Always 1 1630 // 0x00000007 [2:0] DES_1 (0x3) Together, PIDR1 1631 io_ro_32 pidr2; 1632 1633 _REG_(M33_PIDR3_OFFSET) // M33_PIDR3 1634 // CoreSight Peripheral ID3 1635 // 0x000000f0 [7:4] REVAND (0x0) Indicates minor errata fixes specific to the revision of... 1636 // 0x0000000f [3:0] CMOD (0x0) Customer Modified 1637 io_ro_32 pidr3; 1638 1639 // (Description copied from array index 0 register M33_CIDR0 applies similarly to other array indexes) 1640 _REG_(M33_CIDR0_OFFSET) // M33_CIDR0 1641 // CoreSight Component ID0 1642 // 0x000000ff [7:0] PRMBL_0 (0x0d) Preamble[0] 1643 io_ro_32 cidr[4]; 1644 } m33_hw_t; 1645 1646 #define m33_hw ((m33_hw_t *)PPB_BASE) 1647 #define m33_ns_hw ((m33_hw_t *)PPB_NONSEC_BASE) 1648 static_assert(sizeof (m33_hw_t) == 0x43000, ""); 1649 1650 #endif // _HARDWARE_STRUCTS_M33_H 1651 1652
