1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /* 4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _HARDWARE_STRUCTS_ADC_H 10 #define _HARDWARE_STRUCTS_ADC_H 11 12 #include "hardware/address_mapped.h" 13 #include "hardware/regs/adc.h" 14 15 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc 16 // 17 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 18 // _REG_(x) will link to the corresponding register in hardware/regs/adc.h. 19 // 20 // Bit-field descriptions are of the form: 21 // BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION 22 23 typedef struct { 24 _REG_(ADC_CS_OFFSET) // ADC_CS 25 // ADC Control and Status 26 // 0x001f0000 [20:16] : RROBIN (0): Round-robin sampling 27 // 0x00007000 [14:12] : AINSEL (0): Select analog mux input 28 // 0x00000400 [10] : ERR_STICKY (0): Some past ADC conversion encountered an error 29 // 0x00000200 [9] : ERR (0): The most recent ADC conversion encountered an error; result is undefined or noisy 30 // 0x00000100 [8] : READY (0): 1 if the ADC is ready to start a new conversion 31 // 0x00000008 [3] : START_MANY (0): Continuously perform conversions whilst this bit is 1 32 // 0x00000004 [2] : START_ONCE (0): Start a single conversion 33 // 0x00000002 [1] : TS_EN (0): Power on temperature sensor 34 // 0x00000001 [0] : EN (0): Power on ADC and enable its clock 35 io_rw_32 cs; 36 37 _REG_(ADC_RESULT_OFFSET) // ADC_RESULT 38 // Result of most recent ADC conversion 39 // 0x00000fff [11:0] : RESULT (0) 40 io_ro_32 result; 41 42 _REG_(ADC_FCS_OFFSET) // ADC_FCS 43 // FIFO control and status 44 // 0x0f000000 [27:24] : THRESH (0): DREQ/IRQ asserted when level >= threshold 45 // 0x000f0000 [19:16] : LEVEL (0): The number of conversion results currently waiting in the FIFO 46 // 0x00000800 [11] : OVER (0): 1 if the FIFO has been overflowed 47 // 0x00000400 [10] : UNDER (0): 1 if the FIFO has been underflowed 48 // 0x00000200 [9] : FULL (0) 49 // 0x00000100 [8] : EMPTY (0) 50 // 0x00000008 [3] : DREQ_EN (0): If 1: assert DMA requests when FIFO contains data 51 // 0x00000004 [2] : ERR (0): If 1: conversion error bit appears in the FIFO alongside the result 52 // 0x00000002 [1] : SHIFT (0): If 1: FIFO results are right-shifted to be one byte in size 53 // 0x00000001 [0] : EN (0): If 1: write result to the FIFO after each conversion 54 io_rw_32 fcs; 55 56 _REG_(ADC_FIFO_OFFSET) // ADC_FIFO 57 // Conversion result FIFO 58 // 0x00008000 [15] : ERR (0): 1 if this particular sample experienced a conversion error 59 // 0x00000fff [11:0] : VAL (0) 60 io_ro_32 fifo; 61 62 _REG_(ADC_DIV_OFFSET) // ADC_DIV 63 // Clock divider 64 // 0x00ffff00 [23:8] : INT (0): Integer part of clock divisor 65 // 0x000000ff [7:0] : FRAC (0): Fractional part of clock divisor 66 io_rw_32 div; 67 68 _REG_(ADC_INTR_OFFSET) // ADC_INTR 69 // Raw Interrupts 70 // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level 71 io_ro_32 intr; 72 73 _REG_(ADC_INTE_OFFSET) // ADC_INTE 74 // Interrupt Enable 75 // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level 76 io_rw_32 inte; 77 78 _REG_(ADC_INTF_OFFSET) // ADC_INTF 79 // Interrupt Force 80 // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level 81 io_rw_32 intf; 82 83 _REG_(ADC_INTS_OFFSET) // ADC_INTS 84 // Interrupt status after masking & forcing 85 // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level 86 io_ro_32 ints; 87 } adc_hw_t; 88 89 #define adc_hw ((adc_hw_t *)ADC_BASE) 90 91 #endif 92
