1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : XIP 8 // Version : 1 9 // Bus type : ahb 10 // Description : QSPI flash execute-in-place block 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_XIP_DEFINED 13 #define HARDWARE_REGS_XIP_DEFINED 14 // ============================================================================= 15 // Register : XIP_CTRL 16 // Description : Cache control 17 #define XIP_CTRL_OFFSET _u(0x00000000) 18 #define XIP_CTRL_BITS _u(0x0000000b) 19 #define XIP_CTRL_RESET _u(0x00000003) 20 // ----------------------------------------------------------------------------- 21 // Field : XIP_CTRL_POWER_DOWN 22 // Description : When 1, the cache memories are powered down. They retain state, 23 // but can not be accessed. This reduces static power dissipation. 24 // Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache 25 // cannot 26 // be enabled when powered down. 27 // Cache-as-SRAM accesses will produce a bus error response when 28 // the cache is powered down. 29 #define XIP_CTRL_POWER_DOWN_RESET _u(0x0) 30 #define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008) 31 #define XIP_CTRL_POWER_DOWN_MSB _u(3) 32 #define XIP_CTRL_POWER_DOWN_LSB _u(3) 33 #define XIP_CTRL_POWER_DOWN_ACCESS "RW" 34 // ----------------------------------------------------------------------------- 35 // Field : XIP_CTRL_ERR_BADWRITE 36 // Description : When 1, writes to any alias other than 0x0 (caching, 37 // allocating) 38 // will produce a bus fault. When 0, these writes are silently 39 // ignored. 40 // In either case, writes to the 0x0 alias will deallocate on tag 41 // match, 42 // as usual. 43 #define XIP_CTRL_ERR_BADWRITE_RESET _u(0x1) 44 #define XIP_CTRL_ERR_BADWRITE_BITS _u(0x00000002) 45 #define XIP_CTRL_ERR_BADWRITE_MSB _u(1) 46 #define XIP_CTRL_ERR_BADWRITE_LSB _u(1) 47 #define XIP_CTRL_ERR_BADWRITE_ACCESS "RW" 48 // ----------------------------------------------------------------------------- 49 // Field : XIP_CTRL_EN 50 // Description : When 1, enable the cache. When the cache is disabled, all XIP 51 // accesses 52 // will go straight to the flash, without querying the cache. When 53 // enabled, 54 // cacheable XIP accesses will query the cache, and the flash will 55 // not be accessed if the tag matches and the valid bit is set. 56 // 57 // If the cache is enabled, cache-as-SRAM accesses have no effect 58 // on the 59 // cache data RAM, and will produce a bus error response. 60 #define XIP_CTRL_EN_RESET _u(0x1) 61 #define XIP_CTRL_EN_BITS _u(0x00000001) 62 #define XIP_CTRL_EN_MSB _u(0) 63 #define XIP_CTRL_EN_LSB _u(0) 64 #define XIP_CTRL_EN_ACCESS "RW" 65 // ============================================================================= 66 // Register : XIP_FLUSH 67 // Description : Cache Flush control 68 // Write 1 to flush the cache. This clears the tag memory, but 69 // the data memory retains its contents. (This means cache-as-SRAM 70 // contents is not affected by flush or reset.) 71 // Reading will hold the bus (stall the processor) until the flush 72 // completes. Alternatively STAT can be polled until completion. 73 #define XIP_FLUSH_OFFSET _u(0x00000004) 74 #define XIP_FLUSH_BITS _u(0x00000001) 75 #define XIP_FLUSH_RESET _u(0x00000000) 76 #define XIP_FLUSH_MSB _u(0) 77 #define XIP_FLUSH_LSB _u(0) 78 #define XIP_FLUSH_ACCESS "SC" 79 // ============================================================================= 80 // Register : XIP_STAT 81 // Description : Cache Status 82 #define XIP_STAT_OFFSET _u(0x00000008) 83 #define XIP_STAT_BITS _u(0x00000007) 84 #define XIP_STAT_RESET _u(0x00000002) 85 // ----------------------------------------------------------------------------- 86 // Field : XIP_STAT_FIFO_FULL 87 // Description : When 1, indicates the XIP streaming FIFO is completely full. 88 // The streaming FIFO is 2 entries deep, so the full and empty 89 // flag allow its level to be ascertained. 90 #define XIP_STAT_FIFO_FULL_RESET _u(0x0) 91 #define XIP_STAT_FIFO_FULL_BITS _u(0x00000004) 92 #define XIP_STAT_FIFO_FULL_MSB _u(2) 93 #define XIP_STAT_FIFO_FULL_LSB _u(2) 94 #define XIP_STAT_FIFO_FULL_ACCESS "RO" 95 // ----------------------------------------------------------------------------- 96 // Field : XIP_STAT_FIFO_EMPTY 97 // Description : When 1, indicates the XIP streaming FIFO is completely empty. 98 #define XIP_STAT_FIFO_EMPTY_RESET _u(0x1) 99 #define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002) 100 #define XIP_STAT_FIFO_EMPTY_MSB _u(1) 101 #define XIP_STAT_FIFO_EMPTY_LSB _u(1) 102 #define XIP_STAT_FIFO_EMPTY_ACCESS "RO" 103 // ----------------------------------------------------------------------------- 104 // Field : XIP_STAT_FLUSH_READY 105 // Description : Reads as 0 while a cache flush is in progress, and 1 otherwise. 106 // The cache is flushed whenever the XIP block is reset, and also 107 // when requested via the FLUSH register. 108 #define XIP_STAT_FLUSH_READY_RESET _u(0x0) 109 #define XIP_STAT_FLUSH_READY_BITS _u(0x00000001) 110 #define XIP_STAT_FLUSH_READY_MSB _u(0) 111 #define XIP_STAT_FLUSH_READY_LSB _u(0) 112 #define XIP_STAT_FLUSH_READY_ACCESS "RO" 113 // ============================================================================= 114 // Register : XIP_CTR_HIT 115 // Description : Cache Hit counter 116 // A 32 bit saturating counter that increments upon each cache 117 // hit, 118 // i.e. when an XIP access is serviced directly from cached data. 119 // Write any value to clear. 120 #define XIP_CTR_HIT_OFFSET _u(0x0000000c) 121 #define XIP_CTR_HIT_BITS _u(0xffffffff) 122 #define XIP_CTR_HIT_RESET _u(0x00000000) 123 #define XIP_CTR_HIT_MSB _u(31) 124 #define XIP_CTR_HIT_LSB _u(0) 125 #define XIP_CTR_HIT_ACCESS "WC" 126 // ============================================================================= 127 // Register : XIP_CTR_ACC 128 // Description : Cache Access counter 129 // A 32 bit saturating counter that increments upon each XIP 130 // access, 131 // whether the cache is hit or not. This includes noncacheable 132 // accesses. 133 // Write any value to clear. 134 #define XIP_CTR_ACC_OFFSET _u(0x00000010) 135 #define XIP_CTR_ACC_BITS _u(0xffffffff) 136 #define XIP_CTR_ACC_RESET _u(0x00000000) 137 #define XIP_CTR_ACC_MSB _u(31) 138 #define XIP_CTR_ACC_LSB _u(0) 139 #define XIP_CTR_ACC_ACCESS "WC" 140 // ============================================================================= 141 // Register : XIP_STREAM_ADDR 142 // Description : FIFO stream address 143 // The address of the next word to be streamed from flash to the 144 // streaming FIFO. 145 // Increments automatically after each flash access. 146 // Write the initial access address here before starting a 147 // streaming read. 148 #define XIP_STREAM_ADDR_OFFSET _u(0x00000014) 149 #define XIP_STREAM_ADDR_BITS _u(0xfffffffc) 150 #define XIP_STREAM_ADDR_RESET _u(0x00000000) 151 #define XIP_STREAM_ADDR_MSB _u(31) 152 #define XIP_STREAM_ADDR_LSB _u(2) 153 #define XIP_STREAM_ADDR_ACCESS "RW" 154 // ============================================================================= 155 // Register : XIP_STREAM_CTR 156 // Description : FIFO stream control 157 // Write a nonzero value to start a streaming read. This will then 158 // progress in the background, using flash idle cycles to transfer 159 // a linear data block from flash to the streaming FIFO. 160 // Decrements automatically (1 at a time) as the stream 161 // progresses, and halts on reaching 0. 162 // Write 0 to halt an in-progress stream, and discard any 163 // in-flight 164 // read, so that a new stream can immediately be started (after 165 // draining the FIFO and reinitialising STREAM_ADDR) 166 #define XIP_STREAM_CTR_OFFSET _u(0x00000018) 167 #define XIP_STREAM_CTR_BITS _u(0x003fffff) 168 #define XIP_STREAM_CTR_RESET _u(0x00000000) 169 #define XIP_STREAM_CTR_MSB _u(21) 170 #define XIP_STREAM_CTR_LSB _u(0) 171 #define XIP_STREAM_CTR_ACCESS "RW" 172 // ============================================================================= 173 // Register : XIP_STREAM_FIFO 174 // Description : FIFO stream data 175 // Streamed data is buffered here, for retrieval by the system 176 // DMA. 177 // This FIFO can also be accessed via the XIP_AUX slave, to avoid 178 // exposing 179 // the DMA to bus stalls caused by other XIP traffic. 180 #define XIP_STREAM_FIFO_OFFSET _u(0x0000001c) 181 #define XIP_STREAM_FIFO_BITS _u(0xffffffff) 182 #define XIP_STREAM_FIFO_RESET _u(0x00000000) 183 #define XIP_STREAM_FIFO_MSB _u(31) 184 #define XIP_STREAM_FIFO_LSB _u(0) 185 #define XIP_STREAM_FIFO_ACCESS "RF" 186 // ============================================================================= 187 #endif // HARDWARE_REGS_XIP_DEFINED 188
