1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : VREG_AND_CHIP_RESET
10 // Version        : 1
11 // Bus type       : apb
12 // Description    : control and status for on-chip voltage regulator and chip
13 //                  level reset subsystem
14 // =============================================================================
15 #ifndef _HARDWARE_REGS_VREG_AND_CHIP_RESET_H
16 #define _HARDWARE_REGS_VREG_AND_CHIP_RESET_H
17 // =============================================================================
18 // Register    : VREG_AND_CHIP_RESET_VREG
19 // Description : Voltage regulator control and status
20 #define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000)
21 #define VREG_AND_CHIP_RESET_VREG_BITS   _u(0x000010f3)
22 #define VREG_AND_CHIP_RESET_VREG_RESET  _u(0x000000b1)
23 // -----------------------------------------------------------------------------
24 // Field       : VREG_AND_CHIP_RESET_VREG_ROK
25 // Description : regulation status
26 //               0=not in regulation, 1=in regulation
27 #define VREG_AND_CHIP_RESET_VREG_ROK_RESET  _u(0x0)
28 #define VREG_AND_CHIP_RESET_VREG_ROK_BITS   _u(0x00001000)
29 #define VREG_AND_CHIP_RESET_VREG_ROK_MSB    _u(12)
30 #define VREG_AND_CHIP_RESET_VREG_ROK_LSB    _u(12)
31 #define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO"
32 // -----------------------------------------------------------------------------
33 // Field       : VREG_AND_CHIP_RESET_VREG_VSEL
34 // Description : output voltage select
35 //               0000 to 0101 - 0.80V
36 //               0110         - 0.85V
37 //               0111         - 0.90V
38 //               1000         - 0.95V
39 //               1001         - 1.00V
40 //               1010         - 1.05V
41 //               1011         - 1.10V (default)
42 //               1100         - 1.15V
43 //               1101         - 1.20V
44 //               1110         - 1.25V
45 //               1111         - 1.30V
46 #define VREG_AND_CHIP_RESET_VREG_VSEL_RESET  _u(0xb)
47 #define VREG_AND_CHIP_RESET_VREG_VSEL_BITS   _u(0x000000f0)
48 #define VREG_AND_CHIP_RESET_VREG_VSEL_MSB    _u(7)
49 #define VREG_AND_CHIP_RESET_VREG_VSEL_LSB    _u(4)
50 #define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW"
51 // -----------------------------------------------------------------------------
52 // Field       : VREG_AND_CHIP_RESET_VREG_HIZ
53 // Description : high impedance mode select
54 //               0=not in high impedance mode, 1=in high impedance mode
55 #define VREG_AND_CHIP_RESET_VREG_HIZ_RESET  _u(0x0)
56 #define VREG_AND_CHIP_RESET_VREG_HIZ_BITS   _u(0x00000002)
57 #define VREG_AND_CHIP_RESET_VREG_HIZ_MSB    _u(1)
58 #define VREG_AND_CHIP_RESET_VREG_HIZ_LSB    _u(1)
59 #define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW"
60 // -----------------------------------------------------------------------------
61 // Field       : VREG_AND_CHIP_RESET_VREG_EN
62 // Description : enable
63 //               0=not enabled, 1=enabled
64 #define VREG_AND_CHIP_RESET_VREG_EN_RESET  _u(0x1)
65 #define VREG_AND_CHIP_RESET_VREG_EN_BITS   _u(0x00000001)
66 #define VREG_AND_CHIP_RESET_VREG_EN_MSB    _u(0)
67 #define VREG_AND_CHIP_RESET_VREG_EN_LSB    _u(0)
68 #define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW"
69 // =============================================================================
70 // Register    : VREG_AND_CHIP_RESET_BOD
71 // Description : brown-out detection control
72 #define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004)
73 #define VREG_AND_CHIP_RESET_BOD_BITS   _u(0x000000f1)
74 #define VREG_AND_CHIP_RESET_BOD_RESET  _u(0x00000091)
75 // -----------------------------------------------------------------------------
76 // Field       : VREG_AND_CHIP_RESET_BOD_VSEL
77 // Description : threshold select
78 //               0000 - 0.473V
79 //               0001 - 0.516V
80 //               0010 - 0.559V
81 //               0011 - 0.602V
82 //               0100 - 0.645V
83 //               0101 - 0.688V
84 //               0110 - 0.731V
85 //               0111 - 0.774V
86 //               1000 - 0.817V
87 //               1001 - 0.860V (default)
88 //               1010 - 0.903V
89 //               1011 - 0.946V
90 //               1100 - 0.989V
91 //               1101 - 1.032V
92 //               1110 - 1.075V
93 //               1111 - 1.118V
94 #define VREG_AND_CHIP_RESET_BOD_VSEL_RESET  _u(0x9)
95 #define VREG_AND_CHIP_RESET_BOD_VSEL_BITS   _u(0x000000f0)
96 #define VREG_AND_CHIP_RESET_BOD_VSEL_MSB    _u(7)
97 #define VREG_AND_CHIP_RESET_BOD_VSEL_LSB    _u(4)
98 #define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW"
99 // -----------------------------------------------------------------------------
100 // Field       : VREG_AND_CHIP_RESET_BOD_EN
101 // Description : enable
102 //               0=not enabled, 1=enabled
103 #define VREG_AND_CHIP_RESET_BOD_EN_RESET  _u(0x1)
104 #define VREG_AND_CHIP_RESET_BOD_EN_BITS   _u(0x00000001)
105 #define VREG_AND_CHIP_RESET_BOD_EN_MSB    _u(0)
106 #define VREG_AND_CHIP_RESET_BOD_EN_LSB    _u(0)
107 #define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW"
108 // =============================================================================
109 // Register    : VREG_AND_CHIP_RESET_CHIP_RESET
110 // Description : Chip reset control and status
111 #define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008)
112 #define VREG_AND_CHIP_RESET_CHIP_RESET_BITS   _u(0x01110100)
113 #define VREG_AND_CHIP_RESET_CHIP_RESET_RESET  _u(0x00000000)
114 // -----------------------------------------------------------------------------
115 // Field       : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG
116 // Description : This is set by psm_restart from the debugger.
117 //               Its purpose is to branch bootcode to a safe mode when the
118 //               debugger has issued a psm_restart in order to recover from a
119 //               boot lock-up.
120 //               In the safe mode the debugger can repair the boot code, clear
121 //               this flag then reboot the processor.
122 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET  _u(0x0)
123 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS   _u(0x01000000)
124 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB    _u(24)
125 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB    _u(24)
126 #define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC"
127 // -----------------------------------------------------------------------------
128 // Field       : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART
129 // Description : Last reset was from the debug port
130 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET  _u(0x0)
131 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS   _u(0x00100000)
132 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB    _u(20)
133 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB    _u(20)
134 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO"
135 // -----------------------------------------------------------------------------
136 // Field       : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN
137 // Description : Last reset was from the RUN pin
138 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET  _u(0x0)
139 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS   _u(0x00010000)
140 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB    _u(16)
141 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB    _u(16)
142 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO"
143 // -----------------------------------------------------------------------------
144 // Field       : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR
145 // Description : Last reset was from the power-on reset or brown-out detection
146 //               blocks
147 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET  _u(0x0)
148 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS   _u(0x00000100)
149 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB    _u(8)
150 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB    _u(8)
151 #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
152 // =============================================================================
153 #endif // _HARDWARE_REGS_VREG_AND_CHIP_RESET_H
154 
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