1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef _HAL_PINCTRL_PLATFORM_H_ 7 #define _HAL_PINCTRL_PLATFORM_H_ 8 9 #include "fsl_common.h" 10 11 /*! @file */ 12 13 /******************************************************************************* 14 * Definitions 15 *! 16 * @name Pin function ID 17 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister 18 *inputDaisy configRegister\> 19 * 20 * @{ 21 */ 22 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDI__JTAG_MUX_TDI 0x443C0000, 0x00, 0x443C0610, 0x00, 0x443C0204 23 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDI__MQS2_LEFT 0x443C0000, 0x01, 0x00000000, 0x00, 0x443C0204 24 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDI__NETC_TMR_1588_ALARM1 0x443C0000, 0x02, 0x00000000, 0x00, 0x443C0204 25 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDI__CAN2_TX 0x443C0000, 0x03, 0x00000000, 0x00, 0x443C0204 26 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x443C0000, 0x04, 0x00000000, 0x00, 0x443C0204 27 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDI__GPIO3_IO_BIT28 0x443C0000, 0x05, 0x00000000, 0x00, 0x443C0204 28 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDI__LPUART5_RX 0x443C0000, 0x06, 0x443C0570, 0x00, 0x443C0204 29 30 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x443C0004, 0x00, 0x443C0614, 0x00, 0x443C0208 31 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TMS_SWDIO__CAN4_TX 0x443C0004, 0x02, 0x00000000, 0x00, 0x443C0208 32 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 \ 33 0x443C0004, 0x04, 0x00000000, 0x00, 0x443C0208 34 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TMS_SWDIO__GPIO3_IO_BIT29 0x443C0004, 0x05, 0x00000000, 0x00, 0x443C0208 35 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x443C0004, 0x06, 0x00000000, 0x00, 0x443C0208 36 37 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x443C0008, 0x00, 0x443C060C, 0x00, 0x443C020C 38 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TCLK_SWCLK__CAN4_RX 0x443C0008, 0x02, 0x443C044C, 0x00, 0x443C020C 39 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO_BIT30 \ 40 0x443C0008, 0x04, 0x443C0460, 0x00, 0x443C020C 41 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TCLK_SWCLK__GPIO3_IO_BIT30 0x443C0008, 0x05, 0x00000000, 0x00, 0x443C020C 42 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x443C0008, 0x06, 0x443C056C, 0x00, 0x443C020C 43 44 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x443C000C, 0x00, 0x00000000, 0x00, 0x443C0210 45 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x443C000C, 0x01, 0x00000000, 0x00, 0x443C0210 46 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDO_TRACESWO__NETC_TMR_1588_ALARM2 \ 47 0x443C000C, 0x02, 0x00000000, 0x00, 0x443C0210 48 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x443C000C, 0x03, 0x443C0444, 0x00, 0x443C0210 49 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO_BIT31 \ 50 0x443C000C, 0x04, 0x443C0464, 0x00, 0x443C0210 51 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDO_TRACESWO__GPIO3_IO_BIT31 0x443C000C, 0x05, 0x00000000, 0x00, 0x443C0210 52 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x443C000C, 0x06, 0x443C0574, 0x00, 0x443C0210 53 54 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x443C0010, 0x00, 0x00000000, 0x00, 0x443C0214 55 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO00__LPI2C3_SDA 0x443C0010, 0x01, 0x443C0504, 0x00, 0x443C0214 56 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO00__LPSPI6_PCS0 0x443C0010, 0x04, 0x00000000, 0x00, 0x443C0214 57 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO00__LPUART5_TX 0x443C0010, 0x05, 0x443C0574, 0x01, 0x443C0214 58 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO00__LPI2C5_SDA 0x443C0010, 0x06, 0x443C0514, 0x00, 0x443C0214 59 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO00__FLEXIO1_FLEXIO_BIT0 0x443C0010, 0x07, 0x443C0468, 0x00, 0x443C0214 60 61 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO01__GPIO2_IO_BIT1 0x443C0014, 0x00, 0x00000000, 0x00, 0x443C0218 62 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO01__LPI2C3_SCL 0x443C0014, 0x01, 0x443C0500, 0x00, 0x443C0218 63 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO01__LPSPI6_SIN 0x443C0014, 0x04, 0x00000000, 0x00, 0x443C0218 64 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO01__LPUART5_RX 0x443C0014, 0x05, 0x443C0570, 0x01, 0x443C0218 65 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO01__LPI2C5_SCL 0x443C0014, 0x06, 0x443C0510, 0x00, 0x443C0218 66 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO01__FLEXIO1_FLEXIO_BIT1 0x443C0014, 0x07, 0x443C046C, 0x00, 0x443C0218 67 68 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO02__GPIO2_IO_BIT2 0x443C0018, 0x00, 0x00000000, 0x00, 0x443C021C 69 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO02__LPI2C4_SDA 0x443C0018, 0x01, 0x443C050C, 0x00, 0x443C021C 70 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO02__LPSPI6_SOUT 0x443C0018, 0x04, 0x00000000, 0x00, 0x443C021C 71 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO02__LPUART5_CTS_B 0x443C0018, 0x05, 0x443C056C, 0x01, 0x443C021C 72 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO02__LPI2C6_SDA 0x443C0018, 0x06, 0x443C051C, 0x00, 0x443C021C 73 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO02__FLEXIO1_FLEXIO_BIT2 0x443C0018, 0x07, 0x443C0470, 0x00, 0x443C021C 74 75 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO03__GPIO2_IO_BIT3 0x443C001C, 0x00, 0x00000000, 0x00, 0x443C0220 76 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO03__LPI2C4_SCL 0x443C001C, 0x01, 0x443C0508, 0x00, 0x443C0220 77 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO03__LPSPI6_SCK 0x443C001C, 0x04, 0x00000000, 0x00, 0x443C0220 78 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO03__LPUART5_RTS_B 0x443C001C, 0x05, 0x00000000, 0x00, 0x443C0220 79 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO03__LPI2C6_SCL 0x443C001C, 0x06, 0x443C0518, 0x00, 0x443C0220 80 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO03__FLEXIO1_FLEXIO_BIT3 0x443C001C, 0x07, 0x443C0474, 0x00, 0x443C0220 81 82 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x443C0020, 0x00, 0x00000000, 0x00, 0x443C0224 83 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO04__TPM3_CH0 0x443C0020, 0x01, 0x00000000, 0x00, 0x443C0224 84 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO04__PDM_CLK 0x443C0020, 0x02, 0x00000000, 0x00, 0x443C0224 85 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO04__CAN4_TX 0x443C0020, 0x03, 0x00000000, 0x00, 0x443C0224 86 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO04__LPSPI7_PCS0 0x443C0020, 0x04, 0x00000000, 0x00, 0x443C0224 87 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO04__LPUART6_TX 0x443C0020, 0x05, 0x443C0580, 0x01, 0x443C0224 88 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO04__LPI2C6_SDA 0x443C0020, 0x06, 0x443C051C, 0x01, 0x443C0224 89 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO04__FLEXIO1_FLEXIO_BIT4 0x443C0020, 0x07, 0x443C0478, 0x00, 0x443C0224 90 91 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO05__GPIO2_IO_BIT5 0x443C0024, 0x00, 0x00000000, 0x00, 0x443C0228 92 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO05__TPM4_CH0 0x443C0024, 0x01, 0x00000000, 0x00, 0x443C0228 93 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO05__PDM_BIT_STREAM_BIT0 0x443C0024, 0x02, 0x443C040C, 0x01, 0x443C0228 94 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO05__CAN4_RX 0x443C0024, 0x03, 0x443C044C, 0x01, 0x443C0228 95 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO05__LPSPI7_SIN 0x443C0024, 0x04, 0x00000000, 0x00, 0x443C0228 96 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO05__LPUART6_RX 0x443C0024, 0x05, 0x443C057C, 0x01, 0x443C0228 97 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO05__LPI2C6_SCL 0x443C0024, 0x06, 0x443C0518, 0x01, 0x443C0228 98 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO05__FLEXIO1_FLEXIO_BIT5 0x443C0024, 0x07, 0x443C047C, 0x00, 0x443C0228 99 100 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x443C0028, 0x00, 0x00000000, 0x00, 0x443C022C 101 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO06__TPM5_CH0 0x443C0028, 0x01, 0x00000000, 0x00, 0x443C022C 102 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO06__PDM_BIT_STREAM_BIT1 0x443C0028, 0x02, 0x443C0410, 0x01, 0x443C022C 103 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO06__LPSPI7_SOUT 0x443C0028, 0x04, 0x00000000, 0x00, 0x443C022C 104 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO06__LPUART6_CTS_B 0x443C0028, 0x05, 0x443C0578, 0x01, 0x443C022C 105 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO06__LPI2C7_SDA 0x443C0028, 0x06, 0x443C0524, 0x00, 0x443C022C 106 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO06__FLEXIO1_FLEXIO_BIT6 0x443C0028, 0x07, 0x443C0480, 0x00, 0x443C022C 107 108 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x443C002C, 0x00, 0x00000000, 0x00, 0x443C0230 109 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO07__LPSPI3_PCS1 0x443C002C, 0x01, 0x00000000, 0x00, 0x443C0230 110 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO07__LPSPI7_SCK 0x443C002C, 0x04, 0x00000000, 0x00, 0x443C0230 111 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO07__LPUART6_RTS_B 0x443C002C, 0x05, 0x00000000, 0x00, 0x443C0230 112 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO07__LPI2C7_SCL 0x443C002C, 0x06, 0x443C0520, 0x00, 0x443C0230 113 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO07__FLEXIO1_FLEXIO_BIT7 0x443C002C, 0x07, 0x443C0484, 0x00, 0x443C0230 114 115 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x443C0030, 0x00, 0x00000000, 0x00, 0x443C0234 116 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO08__LPSPI3_PCS0 0x443C0030, 0x01, 0x00000000, 0x00, 0x443C0234 117 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO08__TPM6_CH0 0x443C0030, 0x04, 0x00000000, 0x00, 0x443C0234 118 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO08__LPUART7_TX 0x443C0030, 0x05, 0x443C0588, 0x01, 0x443C0234 119 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO08__LPI2C7_SDA 0x443C0030, 0x06, 0x443C0524, 0x01, 0x443C0234 120 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO08__FLEXIO1_FLEXIO_BIT8 0x443C0030, 0x07, 0x443C0488, 0x00, 0x443C0234 121 122 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x443C0034, 0x00, 0x00000000, 0x00, 0x443C0238 123 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO09__LPSPI3_SIN 0x443C0034, 0x01, 0x00000000, 0x00, 0x443C0238 124 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO09__TPM3_EXTCLK 0x443C0034, 0x04, 0x00000000, 0x00, 0x443C0238 125 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO09__LPUART7_RX 0x443C0034, 0x05, 0x443C0584, 0x01, 0x443C0238 126 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO09__LPI2C7_SCL 0x443C0034, 0x06, 0x443C0520, 0x01, 0x443C0238 127 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO09__FLEXIO1_FLEXIO_BIT9 0x443C0034, 0x07, 0x443C048C, 0x00, 0x443C0238 128 129 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x443C0038, 0x00, 0x00000000, 0x00, 0x443C023C 130 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO10__LPSPI3_SOUT 0x443C0038, 0x01, 0x00000000, 0x00, 0x443C023C 131 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO10__TPM4_EXTCLK 0x443C0038, 0x04, 0x00000000, 0x00, 0x443C023C 132 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO10__LPUART7_CTS_B 0x443C0038, 0x05, 0x00000000, 0x00, 0x443C023C 133 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO10__LPI2C8_SDA 0x443C0038, 0x06, 0x443C052C, 0x00, 0x443C023C 134 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO10__FLEXIO1_FLEXIO_BIT10 0x443C0038, 0x07, 0x443C0490, 0x00, 0x443C023C 135 136 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x443C003C, 0x00, 0x00000000, 0x00, 0x443C0240 137 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO11__LPSPI3_SCK 0x443C003C, 0x01, 0x00000000, 0x00, 0x443C0240 138 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO11__TPM5_EXTCLK 0x443C003C, 0x04, 0x00000000, 0x00, 0x443C0240 139 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO11__LPUART7_RTS_B 0x443C003C, 0x05, 0x00000000, 0x00, 0x443C0240 140 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO11__LPI2C8_SCL 0x443C003C, 0x06, 0x443C0528, 0x00, 0x443C0240 141 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO11__FLEXIO1_FLEXIO_BIT11 0x443C003C, 0x07, 0x443C0494, 0x00, 0x443C0240 142 143 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x443C0040, 0x00, 0x00000000, 0x00, 0x443C0244 144 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO12__TPM3_CH2 0x443C0040, 0x01, 0x00000000, 0x00, 0x443C0244 145 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO12__PDM_BIT_STREAM_BIT2 0x443C0040, 0x02, 0x443C0414, 0x00, 0x443C0244 146 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO12__FLEXIO1_FLEXIO_BIT12 0x443C0040, 0x03, 0x443C0498, 0x00, 0x443C0244 147 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO12__LPSPI8_PCS0 0x443C0040, 0x04, 0x00000000, 0x00, 0x443C0244 148 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO12__LPUART8_TX 0x443C0040, 0x05, 0x00000000, 0x00, 0x443C0244 149 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO12__LPI2C8_SDA 0x443C0040, 0x06, 0x443C052C, 0x01, 0x443C0244 150 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO12__SAI3_RX_SYNC 0x443C0040, 0x07, 0x443C0590, 0x00, 0x443C0244 151 152 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x443C0044, 0x00, 0x00000000, 0x00, 0x443C0248 153 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO13__TPM4_CH2 0x443C0044, 0x01, 0x00000000, 0x00, 0x443C0248 154 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO13__PDM_BIT_STREAM_BIT3 0x443C0044, 0x02, 0x443C0418, 0x00, 0x443C0248 155 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO13__LPSPI8_SIN 0x443C0044, 0x04, 0x00000000, 0x00, 0x443C0248 156 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO13__LPUART8_RX 0x443C0044, 0x05, 0x00000000, 0x00, 0x443C0248 157 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO13__LPI2C8_SCL 0x443C0044, 0x06, 0x443C0528, 0x01, 0x443C0248 158 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO13__FLEXIO1_FLEXIO_BIT13 0x443C0044, 0x07, 0x443C049C, 0x00, 0x443C0248 159 160 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x443C0048, 0x00, 0x00000000, 0x00, 0x443C024C 161 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO14__LPUART3_TX 0x443C0048, 0x01, 0x443C055C, 0x01, 0x443C024C 162 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO14__LPSPI8_SOUT 0x443C0048, 0x04, 0x00000000, 0x00, 0x443C024C 163 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO14__LPUART8_CTS_B 0x443C0048, 0x05, 0x00000000, 0x00, 0x443C024C 164 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO14__LPUART4_TX 0x443C0048, 0x06, 0x443C0568, 0x01, 0x443C024C 165 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO14__FLEXIO1_FLEXIO_BIT14 0x443C0048, 0x07, 0x443C04A0, 0x00, 0x443C024C 166 167 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO15__GPIO2_IO_BIT15 0x443C004C, 0x00, 0x00000000, 0x00, 0x443C0250 168 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO15__LPUART3_RX 0x443C004C, 0x01, 0x443C0558, 0x01, 0x443C0250 169 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO15__LPSPI8_SCK 0x443C004C, 0x04, 0x00000000, 0x00, 0x443C0250 170 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO15__LPUART8_RTS_B 0x443C004C, 0x05, 0x00000000, 0x00, 0x443C0250 171 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO15__LPUART4_RX 0x443C004C, 0x06, 0x443C0564, 0x01, 0x443C0250 172 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO15__FLEXIO1_FLEXIO_BIT15 0x443C004C, 0x07, 0x443C04A4, 0x00, 0x443C0250 173 174 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x443C0050, 0x00, 0x00000000, 0x00, 0x443C0254 175 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO16__SAI3_TX_BCLK 0x443C0050, 0x01, 0x00000000, 0x00, 0x443C0254 176 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO16__PDM_BIT_STREAM_BIT2 0x443C0050, 0x02, 0x443C0414, 0x01, 0x443C0254 177 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO16__LPUART3_CTS_B 0x443C0050, 0x04, 0x443C0554, 0x01, 0x443C0254 178 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO16__LPSPI4_PCS2 0x443C0050, 0x05, 0x443C0538, 0x01, 0x443C0254 179 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO16__LPUART4_CTS_B 0x443C0050, 0x06, 0x443C0560, 0x01, 0x443C0254 180 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO16__FLEXIO1_FLEXIO_BIT16 0x443C0050, 0x07, 0x443C04A8, 0x00, 0x443C0254 181 182 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO17__GPIO2_IO_BIT17 0x443C0054, 0x00, 0x00000000, 0x00, 0x443C0258 183 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO17__SAI3_MCLK 0x443C0054, 0x01, 0x00000000, 0x00, 0x443C0258 184 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO17__LPUART3_RTS_B 0x443C0054, 0x04, 0x00000000, 0x00, 0x443C0258 185 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO17__LPSPI4_PCS1 0x443C0054, 0x05, 0x443C0534, 0x01, 0x443C0258 186 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO17__LPUART4_RTS_B 0x443C0054, 0x06, 0x00000000, 0x00, 0x443C0258 187 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO17__FLEXIO1_FLEXIO_BIT17 0x443C0054, 0x07, 0x443C04AC, 0x00, 0x443C0258 188 189 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x443C0058, 0x00, 0x00000000, 0x00, 0x443C025C 190 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO18__SAI3_RX_BCLK 0x443C0058, 0x01, 0x443C058C, 0x00, 0x443C025C 191 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO18__LPSPI5_PCS0 0x443C0058, 0x04, 0x00000000, 0x00, 0x443C025C 192 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO18__LPSPI4_PCS0 0x443C0058, 0x05, 0x443C0530, 0x01, 0x443C025C 193 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO18__TPM5_CH2 0x443C0058, 0x06, 0x00000000, 0x00, 0x443C025C 194 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO18__FLEXIO1_FLEXIO_BIT18 0x443C0058, 0x07, 0x443C04B0, 0x00, 0x443C025C 195 196 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x443C005C, 0x00, 0x00000000, 0x00, 0x443C0260 197 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO19__SAI3_RX_SYNC 0x443C005C, 0x01, 0x443C0590, 0x01, 0x443C0260 198 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO19__PDM_BIT_STREAM_BIT3 0x443C005C, 0x02, 0x443C0418, 0x01, 0x443C0260 199 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO19__FLEXIO1_FLEXIO_BIT19 0x443C005C, 0x03, 0x443C04B4, 0x00, 0x443C0260 200 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO19__LPSPI5_SIN 0x443C005C, 0x04, 0x00000000, 0x00, 0x443C0260 201 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO19__LPSPI4_SIN 0x443C005C, 0x05, 0x443C0540, 0x01, 0x443C0260 202 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO19__TPM6_CH2 0x443C005C, 0x06, 0x00000000, 0x00, 0x443C0260 203 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x443C005C, 0x07, 0x00000000, 0x00, 0x443C0260 204 205 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x443C0060, 0x00, 0x00000000, 0x00, 0x443C0264 206 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x443C0060, 0x01, 0x00000000, 0x00, 0x443C0264 207 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO20__PDM_BIT_STREAM_BIT0 0x443C0060, 0x02, 0x443C040C, 0x02, 0x443C0264 208 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO20__LPSPI5_SOUT 0x443C0060, 0x04, 0x00000000, 0x00, 0x443C0264 209 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO20__LPSPI4_SOUT 0x443C0060, 0x05, 0x443C0544, 0x01, 0x443C0264 210 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO20__TPM3_CH1 0x443C0060, 0x06, 0x00000000, 0x00, 0x443C0264 211 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO20__FLEXIO1_FLEXIO_BIT20 0x443C0060, 0x07, 0x443C04B8, 0x00, 0x443C0264 212 213 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x443C0064, 0x00, 0x00000000, 0x00, 0x443C0268 214 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x443C0064, 0x01, 0x00000000, 0x00, 0x443C0268 215 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO21__PDM_CLK 0x443C0064, 0x02, 0x00000000, 0x00, 0x443C0268 216 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO21__FLEXIO1_FLEXIO_BIT21 0x443C0064, 0x03, 0x443C04BC, 0x00, 0x443C0268 217 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO21__LPSPI5_SCK 0x443C0064, 0x04, 0x00000000, 0x00, 0x443C0268 218 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO21__LPSPI4_SCK 0x443C0064, 0x05, 0x443C053C, 0x01, 0x443C0268 219 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO21__TPM4_CH1 0x443C0064, 0x06, 0x00000000, 0x00, 0x443C0268 220 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO21__SAI3_RX_BCLK 0x443C0064, 0x07, 0x443C058C, 0x01, 0x443C0268 221 222 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x443C0068, 0x00, 0x00000000, 0x00, 0x443C026C 223 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO22__USDHC3_CLK 0x443C0068, 0x01, 0x443C05C8, 0x00, 0x443C026C 224 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO22__SPDIF_IN 0x443C0068, 0x02, 0x443C0454, 0x02, 0x443C026C 225 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO22__CAN5_TX 0x443C0068, 0x03, 0x00000000, 0x00, 0x443C026C 226 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO22__TPM5_CH1 0x443C0068, 0x04, 0x00000000, 0x00, 0x443C026C 227 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO22__TPM6_EXTCLK 0x443C0068, 0x05, 0x00000000, 0x00, 0x443C026C 228 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO22__LPI2C5_SDA 0x443C0068, 0x06, 0x443C0514, 0x01, 0x443C026C 229 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO22__FLEXIO1_FLEXIO_BIT22 0x443C0068, 0x07, 0x443C04C0, 0x00, 0x443C026C 230 231 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x443C006C, 0x00, 0x00000000, 0x00, 0x443C0270 232 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO23__USDHC3_CMD 0x443C006C, 0x01, 0x443C05CC, 0x00, 0x443C0270 233 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO23__SPDIF_OUT 0x443C006C, 0x02, 0x00000000, 0x00, 0x443C0270 234 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO23__CAN5_RX 0x443C006C, 0x03, 0x443C0450, 0x00, 0x443C0270 235 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO23__TPM6_CH1 0x443C006C, 0x04, 0x00000000, 0x00, 0x443C0270 236 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO23__LPI2C5_SCL 0x443C006C, 0x06, 0x443C0510, 0x01, 0x443C0270 237 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO23__FLEXIO1_FLEXIO_BIT23 0x443C006C, 0x07, 0x443C04C4, 0x00, 0x443C0270 238 239 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x443C0070, 0x00, 0x00000000, 0x00, 0x443C0274 240 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO24__USDHC3_DATA0 0x443C0070, 0x01, 0x443C05D0, 0x00, 0x443C0274 241 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO24__TPM3_CH3 0x443C0070, 0x04, 0x00000000, 0x00, 0x443C0274 242 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO24__JTAG_MUX_TDO 0x443C0070, 0x05, 0x00000000, 0x00, 0x443C0274 243 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO24__LPSPI6_PCS1 0x443C0070, 0x06, 0x00000000, 0x00, 0x443C0274 244 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO24__FLEXIO1_FLEXIO_BIT24 0x443C0070, 0x07, 0x443C04C8, 0x00, 0x443C0274 245 246 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO25__GPIO2_IO_BIT25 0x443C0074, 0x00, 0x00000000, 0x00, 0x443C0278 247 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO25__USDHC3_DATA1 0x443C0074, 0x01, 0x443C05D4, 0x00, 0x443C0278 248 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO25__CAN2_TX 0x443C0074, 0x02, 0x00000000, 0x00, 0x443C0278 249 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO25__TPM4_CH3 0x443C0074, 0x04, 0x00000000, 0x00, 0x443C0278 250 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO25__JTAG_MUX_TCK 0x443C0074, 0x05, 0x443C060C, 0x01, 0x443C0278 251 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO25__LPSPI7_PCS1 0x443C0074, 0x06, 0x00000000, 0x00, 0x443C0278 252 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO25__FLEXIO1_FLEXIO_BIT25 0x443C0074, 0x07, 0x443C04CC, 0x00, 0x443C0278 253 254 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO26__GPIO2_IO_BIT26 0x443C0078, 0x00, 0x00000000, 0x00, 0x443C027C 255 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO26__USDHC3_DATA2 0x443C0078, 0x01, 0x443C05D8, 0x00, 0x443C027C 256 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO26__PDM_BIT_STREAM_BIT1 0x443C0078, 0x02, 0x443C0410, 0x02, 0x443C027C 257 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO26__FLEXIO1_FLEXIO_BIT26 0x443C0078, 0x03, 0x443C0458, 0x01, 0x443C027C 258 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO26__TPM5_CH3 0x443C0078, 0x04, 0x00000000, 0x00, 0x443C027C 259 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO26__JTAG_MUX_TDI 0x443C0078, 0x05, 0x443C0610, 0x01, 0x443C027C 260 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO26__LPSPI8_PCS1 0x443C0078, 0x06, 0x00000000, 0x00, 0x443C027C 261 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO26__SAI3_TX_SYNC 0x443C0078, 0x07, 0x00000000, 0x00, 0x443C027C 262 263 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x443C007C, 0x00, 0x00000000, 0x00, 0x443C0280 264 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO27__USDHC3_DATA3 0x443C007C, 0x01, 0x443C05DC, 0x00, 0x443C0280 265 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO27__CAN2_RX 0x443C007C, 0x02, 0x443C0444, 0x02, 0x443C0280 266 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO27__TPM6_CH3 0x443C007C, 0x04, 0x00000000, 0x00, 0x443C0280 267 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO27__JTAG_MUX_TMS 0x443C007C, 0x05, 0x443C0614, 0x01, 0x443C0280 268 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO27__LPSPI5_PCS1 0x443C007C, 0x06, 0x00000000, 0x00, 0x443C0280 269 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO27__FLEXIO1_FLEXIO_BIT27 0x443C007C, 0x07, 0x443C045C, 0x01, 0x443C0280 270 271 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x443C0080, 0x00, 0x00000000, 0x00, 0x443C0284 272 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO28__LPI2C3_SDA 0x443C0080, 0x01, 0x443C0504, 0x01, 0x443C0284 273 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO28__CAN3_TX 0x443C0080, 0x02, 0x00000000, 0x00, 0x443C0284 274 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO28__FLEXIO1_FLEXIO_BIT28 0x443C0080, 0x07, 0x00000000, 0x00, 0x443C0284 275 276 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x443C0084, 0x00, 0x00000000, 0x00, 0x443C0288 277 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO29__LPI2C3_SCL 0x443C0084, 0x01, 0x443C0500, 0x01, 0x443C0288 278 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO29__CAN3_RX 0x443C0084, 0x02, 0x443C0448, 0x01, 0x443C0288 279 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO29__FLEXIO1_FLEXIO_BIT29 0x443C0084, 0x07, 0x00000000, 0x00, 0x443C0288 280 281 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x443C0088, 0x00, 0x00000000, 0x00, 0x443C028C 282 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO30__LPI2C4_SDA 0x443C0088, 0x01, 0x443C050C, 0x01, 0x443C028C 283 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO30__CAN5_TX 0x443C0088, 0x02, 0x00000000, 0x00, 0x443C028C 284 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO30__FLEXIO1_FLEXIO_BIT30 0x443C0088, 0x07, 0x443C0460, 0x01, 0x443C028C 285 286 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x443C008C, 0x00, 0x00000000, 0x00, 0x443C0290 287 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO31__LPI2C4_SCL 0x443C008C, 0x01, 0x443C0508, 0x01, 0x443C0290 288 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO31__CAN5_RX 0x443C008C, 0x02, 0x443C0450, 0x01, 0x443C0290 289 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO31__FLEXIO1_FLEXIO_BIT31 0x443C008C, 0x07, 0x443C0464, 0x01, 0x443C0290 290 291 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x443C0090, 0x00, 0x00000000, 0x00, 0x443C0294 292 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO32__PCIE1_CLKREQ_B 0x443C0090, 0x01, 0x00000000, 0x00, 0x443C0294 293 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO32__LPUART6_TX 0x443C0090, 0x02, 0x443C0580, 0x00, 0x443C0294 294 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO32__LPSPI4_PCS2 0x443C0090, 0x04, 0x443C0538, 0x00, 0x443C0294 295 296 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x443C0094, 0x00, 0x00000000, 0x00, 0x443C0298 297 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO33__LPUART6_RX 0x443C0094, 0x02, 0x443C057C, 0x00, 0x443C0298 298 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO33__LPSPI4_PCS1 0x443C0094, 0x04, 0x443C0534, 0x00, 0x443C0298 299 300 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x443C0098, 0x00, 0x00000000, 0x00, 0x443C029C 301 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO34__LPUART6_CTS_B 0x443C0098, 0x02, 0x443C0578, 0x00, 0x443C029C 302 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO34__LPSPI4_PCS0 0x443C0098, 0x04, 0x443C0530, 0x00, 0x443C029C 303 304 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x443C009C, 0x00, 0x00000000, 0x00, 0x443C02A0 305 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO35__PCIE2_CLKREQ_B 0x443C009C, 0x01, 0x00000000, 0x00, 0x443C02A0 306 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO35__LPUART6_RTS_B 0x443C009C, 0x02, 0x00000000, 0x00, 0x443C02A0 307 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO35__LPSPI4_SIN 0x443C009C, 0x04, 0x443C0540, 0x00, 0x443C02A0 308 309 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO36__LPSPI4_SOUT 0x443C00A0, 0x04, 0x443C0544, 0x00, 0x443C02A4 310 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x443C00A0, 0x00, 0x00000000, 0x00, 0x443C02A4 311 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO36__LPUART7_TX 0x443C00A0, 0x02, 0x443C0588, 0x00, 0x443C02A4 312 313 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x443C00A4, 0x00, 0x00000000, 0x00, 0x443C02A8 314 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO37__LPUART7_RX 0x443C00A4, 0x02, 0x443C0584, 0x00, 0x443C02A8 315 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_GPIO_IO37__LPSPI4_SCK 0x443C00A4, 0x04, 0x443C053C, 0x00, 0x443C02A8 316 317 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO1__CLKO_1 0x443C00A8, 0x00, 0x00000000, 0x00, 0x443C02AC 318 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO1__NETC_TMR_1588_TRIG1 0x443C00A8, 0x01, 0x443C0434, 0x00, 0x443C02AC 319 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO1__FLEXIO1_FLEXIO_BIT26 0x443C00A8, 0x04, 0x443C0458, 0x00, 0x443C02AC 320 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO1__GPIO3_IO_BIT26 0x443C00A8, 0x05, 0x00000000, 0x00, 0x443C02AC 321 322 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x443C00AC, 0x05, 0x00000000, 0x00, 0x443C02B0 323 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO2__CLKO_2 0x443C00AC, 0x00, 0x00000000, 0x00, 0x443C02B0 324 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO2__NETC_TMR_1588_PP1 0x443C00AC, 0x01, 0x00000000, 0x00, 0x443C02B0 325 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO2__FLEXIO1_FLEXIO_BIT27 0x443C00AC, 0x04, 0x443C045C, 0x00, 0x443C02B0 326 327 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO3__CLKO_3 0x443C00B0, 0x00, 0x00000000, 0x00, 0x443C02B4 328 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO3__NETC_TMR_1588_TRIG2 0x443C00B0, 0x01, 0x443C0438, 0x00, 0x443C02B4 329 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO3__CAN3_TX 0x443C00B0, 0x02, 0x00000000, 0x00, 0x443C02B4 330 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO3__FLEXIO2_FLEXIO_BIT28 0x443C00B0, 0x04, 0x00000000, 0x00, 0x443C02B4 331 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x443C00B0, 0x05, 0x00000000, 0x00, 0x443C02B4 332 333 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO4__CLKO_4 0x443C00B4, 0x00, 0x00000000, 0x00, 0x443C02B8 334 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO4__NETC_TMR_1588_PP2 0x443C00B4, 0x01, 0x00000000, 0x00, 0x443C02B8 335 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO4__CAN3_RX 0x443C00B4, 0x02, 0x443C0448, 0x00, 0x443C02B8 336 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO4__FLEXIO2_FLEXIO_BIT29 0x443C00B4, 0x04, 0x00000000, 0x00, 0x443C02B8 337 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x443C00B4, 0x05, 0x00000000, 0x00, 0x443C02B8 338 339 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDC__NETC_MDC 0x443C00B8, 0x00, 0x443C0424, 0x00, 0x443C02BC 340 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDC__LPUART3_DCD_B 0x443C00B8, 0x01, 0x00000000, 0x00, 0x443C02BC 341 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDC__I3C2_SCL 0x443C00B8, 0x02, 0x443C04F8, 0x00, 0x443C02BC 342 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDC__USB1_OTG_ID 0x443C00B8, 0x03, 0x00000000, 0x00, 0x443C02BC 343 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDC__FLEXIO2_FLEXIO_BIT0 0x443C00B8, 0x04, 0x00000000, 0x00, 0x443C02BC 344 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x443C00B8, 0x05, 0x00000000, 0x00, 0x443C02BC 345 346 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDIO__NETC_MDIO 0x443C00BC, 0x00, 0x443C0428, 0x00, 0x443C02C0 347 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDIO__LPUART3_RIN_B 0x443C00BC, 0x01, 0x00000000, 0x00, 0x443C02C0 348 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDIO__I3C2_SDA 0x443C00BC, 0x02, 0x443C04FC, 0x00, 0x443C02C0 349 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDIO__USB1_OTG_PWR 0x443C00BC, 0x03, 0x00000000, 0x00, 0x443C02C0 350 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDIO__FLEXIO2_FLEXIO_BIT1 0x443C00BC, 0x04, 0x00000000, 0x00, 0x443C02C0 351 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x443C00BC, 0x05, 0x00000000, 0x00, 0x443C02C0 352 353 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD3__ETH0_RGMII_TD3 0x443C00C0, 0x00, 0x00000000, 0x00, 0x443C02C4 354 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD3__CAN2_TX 0x443C00C0, 0x02, 0x00000000, 0x00, 0x443C02C4 355 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD3__USB2_OTG_ID 0x443C00C0, 0x03, 0x00000000, 0x00, 0x443C02C4 356 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD3__FLEXIO2_FLEXIO_BIT2 0x443C00C0, 0x04, 0x00000000, 0x00, 0x443C02C4 357 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD3__GPIO4_IO_BIT2 0x443C00C0, 0x05, 0x00000000, 0x00, 0x443C02C4 358 359 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD2__ETH0_RGMII_TD2 0x443C00C4, 0x00, 0x00000000, 0x00, 0x443C02C8 360 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD2__ETH0_RMII_REF50_CLK 0x443C00C4, 0x01, 0x00000000, 0x00, 0x443C02C8 361 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD2__CAN2_RX 0x443C00C4, 0x02, 0x443C0444, 0x01, 0x443C02C8 362 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD2__USB2_OTG_OC 0x443C00C4, 0x03, 0x00000000, 0x00, 0x443C02C8 363 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD2__FLEXIO2_FLEXIO_BIT3 0x443C00C4, 0x04, 0x00000000, 0x00, 0x443C02C8 364 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD2__GPIO4_IO_BIT3 0x443C00C4, 0x05, 0x00000000, 0x00, 0x443C02C8 365 366 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD1__ETH0_RGMII_TD1 0x443C00C8, 0x00, 0x00000000, 0x00, 0x443C02CC 367 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD1__LPUART3_RTS_B 0x443C00C8, 0x01, 0x00000000, 0x00, 0x443C02CC 368 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD1__I3C2_PUR 0x443C00C8, 0x02, 0x00000000, 0x00, 0x443C02CC 369 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD1__USB1_OTG_OC 0x443C00C8, 0x03, 0x00000000, 0x00, 0x443C02CC 370 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD1__FLEXIO2_FLEXIO_BIT4 0x443C00C8, 0x04, 0x00000000, 0x00, 0x443C02CC 371 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD1__GPIO4_IO_BIT4 0x443C00C8, 0x05, 0x00000000, 0x00, 0x443C02CC 372 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD1__I3C2_PUR_B 0x443C00C8, 0x06, 0x00000000, 0x00, 0x443C02CC 373 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD1__ETH0_RMII_TXD1 0x443C00C8, 0x07, 0x00000000, 0x00, 0x443C02CC 374 375 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD0__ETH0_RGMII_TD0 0x443C00CC, 0x00, 0x00000000, 0x00, 0x443C02D0 376 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD0__LPUART3_TX 0x443C00CC, 0x01, 0x443C055C, 0x00, 0x443C02D0 377 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD0__ETH0_RMII_TXD0 0x443C00CC, 0x02, 0x00000000, 0x00, 0x443C02D0 378 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD0__FLEXIO2_FLEXIO_BIT5 0x443C00CC, 0x04, 0x00000000, 0x00, 0x443C02D0 379 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TD0__GPIO4_IO_BIT5 0x443C00CC, 0x05, 0x00000000, 0x00, 0x443C02D0 380 381 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TX_CTL__ETH0_RGMII_TX_CTL 0x443C00D0, 0x00, 0x00000000, 0x00, 0x443C02D4 382 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x443C00D0, 0x01, 0x00000000, 0x00, 0x443C02D4 383 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TX_CTL__ETH0_RMII_TX_EN 0x443C00D0, 0x02, 0x00000000, 0x00, 0x443C02D4 384 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO_BIT6 0x443C00D0, 0x04, 0x00000000, 0x00, 0x443C02D4 385 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6 0x443C00D0, 0x05, 0x00000000, 0x00, 0x443C02D4 386 387 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TXC__ETH0_RGMII_TX_CLK 0x443C00D4, 0x00, 0x00000000, 0x00, 0x443C02D8 388 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TXC__ENET_CLK_ROOT 0x443C00D4, 0x01, 0x00000000, 0x00, 0x443C02D8 389 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TXC__FLEXIO2_FLEXIO_BIT7 0x443C00D4, 0x04, 0x00000000, 0x00, 0x443C02D8 390 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_TXC__GPIO4_IO_BIT7 0x443C00D4, 0x05, 0x00000000, 0x00, 0x443C02D8 391 392 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RX_CTL__ETH0_RGMII_RX_CTL 0x443C00D8, 0x00, 0x00000000, 0x00, 0x443C02DC 393 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x443C00D8, 0x01, 0x00000000, 0x00, 0x443C02DC 394 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RX_CTL__ETH0_RMII_CRS_DV 0x443C00D8, 0x02, 0x00000000, 0x00, 0x443C02DC 395 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RX_CTL__USB2_OTG_PWR 0x443C00D8, 0x03, 0x00000000, 0x00, 0x443C02DC 396 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO_BIT8 0x443C00D8, 0x04, 0x00000000, 0x00, 0x443C02DC 397 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8 0x443C00D8, 0x05, 0x00000000, 0x00, 0x443C02DC 398 399 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RXC__ETH0_RGMII_RX_CLK 0x443C00DC, 0x00, 0x00000000, 0x00, 0x443C02E0 400 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RXC__ETH0_RMII_RX_ER 0x443C00DC, 0x01, 0x443C042C, 0x00, 0x443C02E0 401 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RXC__FLEXIO2_FLEXIO_BIT9 0x443C00DC, 0x04, 0x00000000, 0x00, 0x443C02E0 402 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RXC__GPIO4_IO_BIT9 0x443C00DC, 0x05, 0x00000000, 0x00, 0x443C02E0 403 404 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD0__ETH0_RGMII_RD0 0x443C00E0, 0x00, 0x00000000, 0x00, 0x443C02E4 405 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD0__LPUART3_RX 0x443C00E0, 0x01, 0x443C0558, 0x00, 0x443C02E4 406 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD0__ETH0_RMII_RXD0 0x443C00E0, 0x02, 0x00000000, 0x00, 0x443C02E4 407 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD0__FLEXIO2_FLEXIO_BIT10 0x443C00E0, 0x04, 0x00000000, 0x00, 0x443C02E4 408 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD0__GPIO4_IO_BIT10 0x443C00E0, 0x05, 0x00000000, 0x00, 0x443C02E4 409 410 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD1__ETH0_RGMII_RD1 0x443C00E4, 0x00, 0x00000000, 0x00, 0x443C02E8 411 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD1__LPUART3_CTS_B 0x443C00E4, 0x01, 0x443C0554, 0x00, 0x443C02E8 412 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD1__ETH0_RMII_RXD1 0x443C00E4, 0x02, 0x00000000, 0x00, 0x443C02E8 413 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD1__LPTMR2_ALT1 0x443C00E4, 0x03, 0x443C0548, 0x00, 0x443C02E8 414 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD1__FLEXIO2_FLEXIO_BIT11 0x443C00E4, 0x04, 0x00000000, 0x00, 0x443C02E8 415 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD1__GPIO4_IO_BIT11 0x443C00E4, 0x05, 0x00000000, 0x00, 0x443C02E8 416 417 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD2__ETH0_RGMII_RD2 0x443C00E8, 0x00, 0x00000000, 0x00, 0x443C02EC 418 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD2__ETH0_RMII_RX_ER 0x443C00E8, 0x02, 0x443C042C, 0x01, 0x443C02EC 419 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD2__LPTMR2_ALT2 0x443C00E8, 0x03, 0x443C054C, 0x00, 0x443C02EC 420 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD2__FLEXIO2_FLEXIO_BIT12 0x443C00E8, 0x04, 0x00000000, 0x00, 0x443C02EC 421 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD2__GPIO4_IO_BIT12 0x443C00E8, 0x05, 0x00000000, 0x00, 0x443C02EC 422 423 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD3__ETH0_RGMII_RD3 0x443C00EC, 0x00, 0x00000000, 0x00, 0x443C02F0 424 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD3__LPTMR2_ALT3 0x443C00EC, 0x03, 0x443C0550, 0x00, 0x443C02F0 425 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD3__FLEXIO2_FLEXIO_BIT13 0x443C00EC, 0x04, 0x00000000, 0x00, 0x443C02F0 426 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET1_RD3__GPIO4_IO_BIT13 0x443C00EC, 0x05, 0x00000000, 0x00, 0x443C02F0 427 428 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDC__NETC_MDC 0x443C00F0, 0x00, 0x443C0424, 0x01, 0x443C02F4 429 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDC__LPUART4_DCD_B 0x443C00F0, 0x01, 0x00000000, 0x00, 0x443C02F4 430 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDC__SAI2_RX_SYNC 0x443C00F0, 0x02, 0x00000000, 0x00, 0x443C02F4 431 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDC__FLEXIO2_FLEXIO_BIT14 0x443C00F0, 0x04, 0x00000000, 0x00, 0x443C02F4 432 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x443C00F0, 0x05, 0x00000000, 0x00, 0x443C02F4 433 434 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDIO__NETC_MDIO 0x443C00F4, 0x00, 0x443C0428, 0x01, 0x443C02F8 435 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDIO__LPUART4_RIN_B 0x443C00F4, 0x01, 0x00000000, 0x00, 0x443C02F8 436 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x443C00F4, 0x02, 0x00000000, 0x00, 0x443C02F8 437 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDIO__FLEXIO2_FLEXIO_BIT15 0x443C00F4, 0x04, 0x00000000, 0x00, 0x443C02F8 438 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x443C00F4, 0x05, 0x00000000, 0x00, 0x443C02F8 439 440 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD3__SAI2_RX_DATA_BIT0 0x443C00F8, 0x02, 0x00000000, 0x00, 0x443C02FC 441 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD3__FLEXIO2_FLEXIO_BIT16 0x443C00F8, 0x04, 0x00000000, 0x00, 0x443C02FC 442 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD3__GPIO4_IO_BIT16 0x443C00F8, 0x05, 0x00000000, 0x00, 0x443C02FC 443 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD3__ETH1_RGMII_TD3 0x443C00F8, 0x00, 0x00000000, 0x00, 0x443C02FC 444 445 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD2__ETH1_RGMII_TD2 0x443C00FC, 0x00, 0x00000000, 0x00, 0x443C0300 446 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD2__ETH1_RMII_REF50_CLK 0x443C00FC, 0x01, 0x00000000, 0x00, 0x443C0300 447 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD2__SAI2_RX_DATA_BIT1 0x443C00FC, 0x02, 0x00000000, 0x00, 0x443C0300 448 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD2__SAI4_TX_SYNC 0x443C00FC, 0x03, 0x443C05A4, 0x00, 0x443C0300 449 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD2__FLEXIO2_FLEXIO_BIT17 0x443C00FC, 0x04, 0x00000000, 0x00, 0x443C0300 450 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x443C00FC, 0x05, 0x00000000, 0x00, 0x443C0300 451 452 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD1__ETH1_RGMII_TD1 0x443C0100, 0x00, 0x00000000, 0x00, 0x443C0304 453 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD1__LPUART4_RTS_B 0x443C0100, 0x01, 0x00000000, 0x00, 0x443C0304 454 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD1__SAI2_RX_DATA_BIT2 0x443C0100, 0x02, 0x00000000, 0x00, 0x443C0304 455 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD1__SAI4_TX_BCLK 0x443C0100, 0x03, 0x443C05A0, 0x00, 0x443C0304 456 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD1__FLEXIO2_FLEXIO_BIT18 0x443C0100, 0x04, 0x00000000, 0x00, 0x443C0304 457 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x443C0100, 0x05, 0x00000000, 0x00, 0x443C0304 458 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD1__ETH1_RMII_TXD1 0x443C0100, 0x06, 0x00000000, 0x00, 0x443C0304 459 460 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD0__ETH1_RGMII_TD0 0x443C0104, 0x00, 0x00000000, 0x00, 0x443C0308 461 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD0__LPUART4_TX 0x443C0104, 0x01, 0x443C0568, 0x00, 0x443C0308 462 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD0__SAI2_RX_DATA_BIT3 0x443C0104, 0x02, 0x00000000, 0x00, 0x443C0308 463 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD0__SAI4_TX_DATA_BIT0 0x443C0104, 0x03, 0x00000000, 0x00, 0x443C0308 464 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD0__FLEXIO2_FLEXIO_BIT19 0x443C0104, 0x04, 0x00000000, 0x00, 0x443C0308 465 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x443C0104, 0x05, 0x00000000, 0x00, 0x443C0308 466 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TD0__ETH1_RMII_TXD0 0x443C0104, 0x06, 0x00000000, 0x00, 0x443C0308 467 468 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TX_CTL__ETH1_RGMII_TX_CTL 0x443C0108, 0x00, 0x00000000, 0x00, 0x443C030C 469 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x443C0108, 0x01, 0x00000000, 0x00, 0x443C030C 470 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x443C0108, 0x02, 0x00000000, 0x00, 0x443C030C 471 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TX_CTL__ETH1_RMII_TX_EN 0x443C0108, 0x03, 0x00000000, 0x00, 0x443C030C 472 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO_BIT20 \ 473 0x443C0108, 0x04, 0x00000000, 0x00, 0x443C030C 474 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TX_CTL__GPIO4_IO_BIT20 0x443C0108, 0x05, 0x00000000, 0x00, 0x443C030C 475 476 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TXC__ETH1_RGMII_TX_CLK 0x443C010C, 0x00, 0x00000000, 0x00, 0x443C0310 477 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TXC__ENET_CLK_ROOT 0x443C010C, 0x01, 0x00000000, 0x00, 0x443C0310 478 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TXC__SAI2_TX_BCLK 0x443C010C, 0x02, 0x00000000, 0x00, 0x443C0310 479 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TXC__FLEXIO2_FLEXIO_BIT21 0x443C010C, 0x04, 0x00000000, 0x00, 0x443C0310 480 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_TXC__GPIO4_IO_BIT21 0x443C010C, 0x05, 0x00000000, 0x00, 0x443C0310 481 482 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RX_CTL__ETH1_RGMII_RX_CTL 0x443C0110, 0x00, 0x00000000, 0x00, 0x443C0314 483 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x443C0110, 0x01, 0x00000000, 0x00, 0x443C0314 484 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RX_CTL__SAI2_TX_DATA_BIT0 0x443C0110, 0x02, 0x00000000, 0x00, 0x443C0314 485 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO_BIT22 \ 486 0x443C0110, 0x04, 0x00000000, 0x00, 0x443C0314 487 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RX_CTL__GPIO4_IO_BIT22 0x443C0110, 0x05, 0x00000000, 0x00, 0x443C0314 488 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RX_CTL__ETH1_RMII_CRS_DV 0x443C0110, 0x06, 0x00000000, 0x00, 0x443C0314 489 490 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RXC__ETH1_RGMII_RX_CLK 0x443C0114, 0x00, 0x00000000, 0x00, 0x443C0318 491 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RXC__ETH1_RMII_RX_ER 0x443C0114, 0x01, 0x443C0430, 0x00, 0x443C0318 492 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RXC__SAI2_TX_DATA_BIT1 0x443C0114, 0x02, 0x00000000, 0x00, 0x443C0318 493 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RXC__SAI4_RX_SYNC 0x443C0114, 0x03, 0x443C059C, 0x00, 0x443C0318 494 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RXC__FLEXIO2_FLEXIO_BIT23 0x443C0114, 0x04, 0x00000000, 0x00, 0x443C0318 495 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x443C0114, 0x05, 0x00000000, 0x00, 0x443C0318 496 497 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD0__ETH1_RGMII_RD0 0x443C0118, 0x00, 0x00000000, 0x00, 0x443C031C 498 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD0__LPUART4_RX 0x443C0118, 0x01, 0x443C0564, 0x00, 0x443C031C 499 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD0__SAI2_TX_DATA_BIT2 0x443C0118, 0x02, 0x00000000, 0x00, 0x443C031C 500 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD0__SAI4_RX_BCLK 0x443C0118, 0x03, 0x443C0594, 0x00, 0x443C031C 501 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD0__FLEXIO2_FLEXIO_BIT24 0x443C0118, 0x04, 0x00000000, 0x00, 0x443C031C 502 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x443C0118, 0x05, 0x00000000, 0x00, 0x443C031C 503 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD0__ETH1_RMII_RXD0 0x443C0118, 0x06, 0x00000000, 0x00, 0x443C031C 504 505 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD1__ETH1_RGMII_RD1 0x443C011C, 0x00, 0x00000000, 0x00, 0x443C0320 506 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD1__SPDIF_IN 0x443C011C, 0x01, 0x443C0454, 0x00, 0x443C0320 507 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD1__SAI2_TX_DATA_BIT3 0x443C011C, 0x02, 0x00000000, 0x00, 0x443C0320 508 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD1__SAI4_RX_DATA_BIT0 0x443C011C, 0x03, 0x443C0598, 0x00, 0x443C0320 509 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD1__FLEXIO2_FLEXIO_BIT25 0x443C011C, 0x04, 0x00000000, 0x00, 0x443C0320 510 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x443C011C, 0x05, 0x00000000, 0x00, 0x443C0320 511 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD1__ETH1_RMII_RXD1 0x443C011C, 0x06, 0x00000000, 0x00, 0x443C0320 512 513 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD2__ETH1_RGMII_RD2 0x443C0120, 0x00, 0x00000000, 0x00, 0x443C0324 514 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD2__LPUART4_CTS_B 0x443C0120, 0x01, 0x443C0560, 0x00, 0x443C0324 515 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD2__SAI2_MCLK 0x443C0120, 0x02, 0x00000000, 0x00, 0x443C0324 516 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD2__MQS2_RIGHT 0x443C0120, 0x03, 0x00000000, 0x00, 0x443C0324 517 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD2__FLEXIO2_FLEXIO_BIT26 0x443C0120, 0x04, 0x00000000, 0x00, 0x443C0324 518 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD2__GPIO4_IO_BIT26 0x443C0120, 0x05, 0x00000000, 0x00, 0x443C0324 519 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD2__ETH1_RMII_RX_ER 0x443C0120, 0x06, 0x443C0430, 0x01, 0x443C0324 520 521 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD3__ETH1_RGMII_RD3 0x443C0124, 0x00, 0x00000000, 0x00, 0x443C0328 522 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD3__SPDIF_OUT 0x443C0124, 0x01, 0x00000000, 0x00, 0x443C0328 523 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD3__SPDIF_IN 0x443C0124, 0x02, 0x443C0454, 0x01, 0x443C0328 524 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD3__MQS2_LEFT 0x443C0124, 0x03, 0x00000000, 0x00, 0x443C0328 525 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD3__FLEXIO2_FLEXIO_BIT27 0x443C0124, 0x04, 0x00000000, 0x00, 0x443C0328 526 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x443C0124, 0x05, 0x00000000, 0x00, 0x443C0328 527 528 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_CLK__FLEXIO1_FLEXIO_BIT8 0x443C0128, 0x04, 0x443C0488, 0x01, 0x443C032C 529 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_CLK__GPIO3_IO_BIT8 0x443C0128, 0x05, 0x00000000, 0x00, 0x443C032C 530 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_CLK__USDHC1_CLK 0x443C0128, 0x00, 0x00000000, 0x00, 0x443C032C 531 532 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_CMD__USDHC1_CMD 0x443C012C, 0x00, 0x00000000, 0x00, 0x443C0330 533 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_CMD__FLEXIO1_FLEXIO_BIT9 0x443C012C, 0x04, 0x443C048C, 0x01, 0x443C0330 534 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_CMD__GPIO3_IO_BIT9 0x443C012C, 0x05, 0x00000000, 0x00, 0x443C0330 535 536 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA0__USDHC1_DATA0 0x443C0130, 0x00, 0x00000000, 0x00, 0x443C0334 537 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA0__FLEXIO1_FLEXIO_BIT10 0x443C0130, 0x04, 0x443C0490, 0x01, 0x443C0334 538 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA0__GPIO3_IO_BIT10 0x443C0130, 0x05, 0x00000000, 0x00, 0x443C0334 539 540 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA1__USDHC1_DATA1 0x443C0134, 0x00, 0x00000000, 0x00, 0x443C0338 541 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA1__FLEXIO1_FLEXIO_BIT11 0x443C0134, 0x04, 0x443C0494, 0x01, 0x443C0338 542 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA1__GPIO3_IO_BIT11 0x443C0134, 0x05, 0x00000000, 0x00, 0x443C0338 543 544 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA2__USDHC1_DATA2 0x443C0138, 0x00, 0x00000000, 0x00, 0x443C033C 545 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA2__FLEXIO1_FLEXIO_BIT12 0x443C0138, 0x04, 0x443C0498, 0x01, 0x443C033C 546 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA2__GPIO3_IO_BIT12 0x443C0138, 0x05, 0x00000000, 0x00, 0x443C033C 547 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA2__PMIC_READY 0x443C0138, 0x06, 0x00000000, 0x00, 0x443C033C 548 549 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA3__USDHC1_DATA3 0x443C013C, 0x00, 0x00000000, 0x00, 0x443C0340 550 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x443C013C, 0x01, 0x00000000, 0x00, 0x443C0340 551 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA3__FLEXIO1_FLEXIO_BIT13 0x443C013C, 0x04, 0x443C049C, 0x01, 0x443C0340 552 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA3__GPIO3_IO_BIT13 0x443C013C, 0x05, 0x00000000, 0x00, 0x443C0340 553 554 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA4__USDHC1_DATA4 0x443C0140, 0x00, 0x00000000, 0x00, 0x443C0344 555 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA4__FLEXSPI1_A_DATA_BIT4 0x443C0140, 0x01, 0x443C04E4, 0x00, 0x443C0344 556 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA4__FLEXIO1_FLEXIO_BIT14 0x443C0140, 0x04, 0x443C04A0, 0x01, 0x443C0344 557 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA4__GPIO3_IO_BIT14 0x443C0140, 0x05, 0x00000000, 0x00, 0x443C0344 558 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA4__XSPI_DATA_BIT4 0x443C0140, 0x06, 0x443C05FC, 0x00, 0x443C0344 559 560 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA5__USDHC1_DATA5 0x443C0144, 0x00, 0x00000000, 0x00, 0x443C0348 561 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA5__FLEXSPI1_A_DATA_BIT5 0x443C0144, 0x01, 0x443C04E8, 0x00, 0x443C0348 562 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA5__USDHC1_RESET_B 0x443C0144, 0x02, 0x00000000, 0x00, 0x443C0348 563 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA5__FLEXIO1_FLEXIO_BIT15 0x443C0144, 0x04, 0x443C04A4, 0x01, 0x443C0348 564 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA5__GPIO3_IO_BIT15 0x443C0144, 0x05, 0x00000000, 0x00, 0x443C0348 565 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA5__XSPI_DATA_BIT5 0x443C0144, 0x06, 0x443C0600, 0x00, 0x443C0348 566 567 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA6__USDHC1_DATA6 0x443C0148, 0x00, 0x00000000, 0x00, 0x443C034C 568 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA6__FLEXSPI1_A_DATA_BIT6 0x443C0148, 0x01, 0x443C04EC, 0x00, 0x443C034C 569 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA6__USDHC1_CD_B 0x443C0148, 0x02, 0x00000000, 0x00, 0x443C034C 570 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA6__FLEXIO1_FLEXIO_BIT16 0x443C0148, 0x04, 0x443C04A8, 0x01, 0x443C034C 571 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA6__GPIO3_IO_BIT16 0x443C0148, 0x05, 0x00000000, 0x00, 0x443C034C 572 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA6__XSPI_DATA_BIT6 0x443C0148, 0x06, 0x443C0604, 0x00, 0x443C034C 573 574 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA7__USDHC1_DATA7 0x443C014C, 0x00, 0x00000000, 0x00, 0x443C0350 575 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA7__FLEXSPI1_A_DATA_BIT7 0x443C014C, 0x01, 0x443C04F0, 0x00, 0x443C0350 576 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA7__USDHC1_WP 0x443C014C, 0x02, 0x00000000, 0x00, 0x443C0350 577 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA7__FLEXIO1_FLEXIO_BIT17 0x443C014C, 0x04, 0x443C04AC, 0x01, 0x443C0350 578 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA7__GPIO3_IO_BIT17 0x443C014C, 0x05, 0x00000000, 0x00, 0x443C0350 579 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_DATA7__XSPI_DATA_BIT7 0x443C014C, 0x06, 0x443C0608, 0x00, 0x443C0350 580 581 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_STROBE__USDHC1_STROBE 0x443C0150, 0x00, 0x00000000, 0x00, 0x443C0354 582 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x443C0150, 0x01, 0x443C04D0, 0x00, 0x443C0354 583 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_STROBE__FLEXIO1_FLEXIO_BIT18 0x443C0150, 0x04, 0x443C04B0, 0x01, 0x443C0354 584 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_STROBE__GPIO3_IO_BIT18 0x443C0150, 0x05, 0x00000000, 0x00, 0x443C0354 585 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD1_STROBE__XSPI_DQS 0x443C0150, 0x06, 0x443C05E4, 0x00, 0x443C0354 586 587 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_VSELECT__USDHC2_VSELECT 0x443C0154, 0x00, 0x00000000, 0x00, 0x443C0358 588 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_VSELECT__USDHC2_WP 0x443C0154, 0x01, 0x00000000, 0x00, 0x443C0358 589 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_VSELECT__LPTMR2_ALT3 0x443C0154, 0x02, 0x443C0550, 0x01, 0x443C0358 590 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_VSELECT__FLEXIO1_FLEXIO_BIT19 0x443C0154, 0x04, 0x443C04B4, 0x01, 0x443C0358 591 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x443C0154, 0x05, 0x00000000, 0x00, 0x443C0358 592 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_VSELECT__EXT_CLK1 0x443C0154, 0x06, 0x443C0420, 0x01, 0x443C0358 593 594 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CLK__USDHC3_CLK 0x443C0158, 0x00, 0x443C05C8, 0x01, 0x443C035C 595 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x443C0158, 0x01, 0x443C04F4, 0x00, 0x443C035C 596 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CLK__SAI5_TX_DATA_BIT1 0x443C0158, 0x02, 0x00000000, 0x00, 0x443C035C 597 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CLK__SAI5_RX_DATA_BIT0 0x443C0158, 0x03, 0x443C05AC, 0x00, 0x443C035C 598 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CLK__FLEXIO1_FLEXIO_BIT20 0x443C0158, 0x04, 0x443C04B8, 0x01, 0x443C035C 599 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CLK__GPIO3_IO_BIT20 0x443C0158, 0x05, 0x00000000, 0x00, 0x443C035C 600 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CLK__XSPI_CLK 0x443C0158, 0x06, 0x443C05E8, 0x00, 0x443C035C 601 602 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CMD__USDHC3_CMD 0x443C015C, 0x00, 0x443C05CC, 0x01, 0x443C0360 603 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x443C015C, 0x01, 0x00000000, 0x00, 0x443C0360 604 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CMD__SAI5_TX_DATA_BIT2 0x443C015C, 0x02, 0x00000000, 0x00, 0x443C0360 605 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CMD__SAI5_RX_SYNC 0x443C015C, 0x03, 0x443C05BC, 0x00, 0x443C0360 606 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CMD__FLEXIO1_FLEXIO_BIT21 0x443C015C, 0x04, 0x443C04BC, 0x01, 0x443C0360 607 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CMD__GPIO3_IO_BIT21 0x443C015C, 0x05, 0x00000000, 0x00, 0x443C0360 608 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_CMD__XSPI_CS 0x443C015C, 0x06, 0x443C05E0, 0x00, 0x443C0360 609 610 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA0__USDHC3_DATA0 0x443C0160, 0x00, 0x443C05D0, 0x01, 0x443C0364 611 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x443C0160, 0x01, 0x443C04D4, 0x00, 0x443C0364 612 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA0__SAI5_TX_DATA_BIT3 0x443C0160, 0x02, 0x00000000, 0x00, 0x443C0364 613 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA0__SAI5_RX_BCLK 0x443C0160, 0x03, 0x443C05A8, 0x00, 0x443C0364 614 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA0__FLEXIO1_FLEXIO_BIT22 0x443C0160, 0x04, 0x443C04C0, 0x01, 0x443C0364 615 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x443C0160, 0x05, 0x00000000, 0x00, 0x443C0364 616 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA0__XSPI_DATA_BIT0 0x443C0160, 0x06, 0x443C05EC, 0x00, 0x443C0364 617 618 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA1__USDHC3_DATA1 0x443C0164, 0x00, 0x443C05D4, 0x01, 0x443C0368 619 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x443C0164, 0x01, 0x443C04D8, 0x00, 0x443C0368 620 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA1__SAI5_RX_DATA_BIT1 0x443C0164, 0x02, 0x443C05B0, 0x00, 0x443C0368 621 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA1__SAI5_TX_DATA_BIT0 0x443C0164, 0x03, 0x00000000, 0x00, 0x443C0368 622 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA1__FLEXIO1_FLEXIO_BIT23 0x443C0164, 0x04, 0x443C04C4, 0x01, 0x443C0368 623 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA1__GPIO3_IO_BIT23 0x443C0164, 0x05, 0x00000000, 0x00, 0x443C0368 624 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA1__XSPI_DATA_BIT1 0x443C0164, 0x06, 0x443C05F0, 0x00, 0x443C0368 625 626 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA2__USDHC3_DATA2 0x443C0168, 0x00, 0x443C05D8, 0x01, 0x443C036C 627 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x443C0168, 0x01, 0x443C04DC, 0x00, 0x443C036C 628 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA2__SAI5_RX_DATA_BIT2 0x443C0168, 0x02, 0x443C05B4, 0x00, 0x443C036C 629 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA2__SAI5_TX_SYNC 0x443C0168, 0x03, 0x443C05C4, 0x00, 0x443C036C 630 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA2__FLEXIO1_FLEXIO_BIT24 0x443C0168, 0x04, 0x443C04C8, 0x01, 0x443C036C 631 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA2__GPIO3_IO_BIT24 0x443C0168, 0x05, 0x00000000, 0x00, 0x443C036C 632 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA2__XSPI_DATA_BIT2 0x443C0168, 0x06, 0x443C05F4, 0x00, 0x443C036C 633 634 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA3__USDHC3_DATA3 0x443C016C, 0x00, 0x443C05DC, 0x01, 0x443C0370 635 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x443C016C, 0x01, 0x443C04E0, 0x00, 0x443C0370 636 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA3__SAI5_RX_DATA_BIT3 0x443C016C, 0x02, 0x443C05B8, 0x00, 0x443C0370 637 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA3__SAI5_TX_BCLK 0x443C016C, 0x03, 0x443C05C0, 0x00, 0x443C0370 638 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA3__FLEXIO1_FLEXIO_BIT25 0x443C016C, 0x04, 0x443C04CC, 0x01, 0x443C0370 639 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA3__GPIO3_IO_BIT25 0x443C016C, 0x05, 0x00000000, 0x00, 0x443C0370 640 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD3_DATA3__XSPI_DATA_BIT3 0x443C016C, 0x06, 0x443C05F8, 0x00, 0x443C0370 641 642 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x443C0170, 0x00, 0x443C04D4, 0x01, 0x443C0374 643 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA0__SAI2_TX_DATA_BIT4 0x443C0170, 0x01, 0x00000000, 0x00, 0x443C0374 644 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA0__SAI4_TX_BCLK 0x443C0170, 0x02, 0x443C05A0, 0x01, 0x443C0374 645 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA0__SAI4_RX_DATA_BIT1 0x443C0170, 0x03, 0x00000000, 0x00, 0x443C0374 646 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x443C0170, 0x04, 0x443C05EC, 0x01, 0x443C0374 647 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x443C0170, 0x05, 0x00000000, 0x00, 0x443C0374 648 649 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x443C0174, 0x00, 0x443C04D8, 0x01, 0x443C0378 650 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA1__SAI2_TX_DATA_BIT5 0x443C0174, 0x01, 0x00000000, 0x00, 0x443C0378 651 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA1__SAI4_TX_SYNC 0x443C0174, 0x02, 0x443C05A4, 0x01, 0x443C0378 652 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA1__SAI4_TX_DATA_BIT1 0x443C0174, 0x03, 0x00000000, 0x00, 0x443C0378 653 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x443C0174, 0x04, 0x443C05F0, 0x01, 0x443C0378 654 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x443C0174, 0x05, 0x00000000, 0x00, 0x443C0378 655 656 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x443C0178, 0x00, 0x443C04DC, 0x01, 0x443C037C 657 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA2__SAI2_TX_DATA_BIT6 0x443C0178, 0x01, 0x00000000, 0x00, 0x443C037C 658 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA2__SAI4_TX_DATA_BIT0 0x443C0178, 0x02, 0x00000000, 0x00, 0x443C037C 659 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x443C0178, 0x04, 0x443C05F4, 0x01, 0x443C037C 660 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x443C0178, 0x05, 0x00000000, 0x00, 0x443C037C 661 662 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x443C017C, 0x00, 0x443C04E0, 0x01, 0x443C0380 663 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA3__SAI2_TX_DATA_BIT7 0x443C017C, 0x01, 0x00000000, 0x00, 0x443C0380 664 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA3__SAI4_RX_DATA_BIT0 0x443C017C, 0x02, 0x443C0598, 0x01, 0x443C0380 665 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x443C017C, 0x04, 0x443C05F8, 0x01, 0x443C0380 666 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x443C017C, 0x05, 0x00000000, 0x00, 0x443C0380 667 668 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x443C0180, 0x00, 0x443C04E4, 0x01, 0x443C0384 669 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x443C0180, 0x01, 0x00000000, 0x00, 0x443C0384 670 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA4__SAI5_RX_DATA_BIT1 0x443C0180, 0x02, 0x443C05B0, 0x01, 0x443C0384 671 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA4__XSPI_DATA_BIT4 0x443C0180, 0x04, 0x443C05FC, 0x01, 0x443C0384 672 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x443C0180, 0x05, 0x00000000, 0x00, 0x443C0384 673 674 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x443C0184, 0x00, 0x443C04E8, 0x01, 0x443C0388 675 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x443C0184, 0x01, 0x443C05C4, 0x01, 0x443C0388 676 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA5__SAI5_RX_DATA_BIT2 0x443C0184, 0x02, 0x443C05B4, 0x01, 0x443C0388 677 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA5__SAI2_RX_DATA_BIT6 0x443C0184, 0x03, 0x443C043C, 0x00, 0x443C0388 678 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA5__XSPI_DATA_BIT5 0x443C0184, 0x04, 0x443C0600, 0x01, 0x443C0388 679 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x443C0184, 0x05, 0x00000000, 0x00, 0x443C0388 680 681 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x443C0188, 0x00, 0x443C04EC, 0x01, 0x443C038C 682 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x443C0188, 0x01, 0x443C05C0, 0x01, 0x443C038C 683 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA6__SAI5_RX_DATA_BIT3 0x443C0188, 0x02, 0x443C05B8, 0x01, 0x443C038C 684 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA6__SAI2_RX_DATA_BIT7 0x443C0188, 0x03, 0x443C0440, 0x00, 0x443C038C 685 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA6__XSPI_DATA_BIT6 0x443C0188, 0x04, 0x443C0604, 0x01, 0x443C038C 686 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x443C0188, 0x05, 0x00000000, 0x00, 0x443C038C 687 688 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x443C018C, 0x00, 0x443C04F0, 0x01, 0x443C0390 689 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x443C018C, 0x01, 0x443C05AC, 0x01, 0x443C0390 690 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA7__SAI5_TX_DATA_BIT1 0x443C018C, 0x02, 0x00000000, 0x00, 0x443C0390 691 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA7__XSPI_DATA_BIT7 0x443C018C, 0x04, 0x443C0608, 0x01, 0x443C0390 692 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x443C018C, 0x05, 0x00000000, 0x00, 0x443C0390 693 694 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x443C0190, 0x00, 0x443C04D0, 0x01, 0x443C0394 695 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x443C0190, 0x01, 0x443C05BC, 0x01, 0x443C0394 696 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DQS__SAI5_TX_DATA_BIT2 0x443C0190, 0x02, 0x00000000, 0x00, 0x443C0394 697 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DQS__SAI2_RX_DATA_BIT6 0x443C0190, 0x03, 0x443C043C, 0x01, 0x443C0394 698 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DQS__XSPI_DQS 0x443C0190, 0x04, 0x443C05E4, 0x01, 0x443C0394 699 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x443C0190, 0x05, 0x00000000, 0x00, 0x443C0394 700 701 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x443C0194, 0x00, 0x443C04F4, 0x01, 0x443C0398 702 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SCLK__SAI2_RX_DATA_BIT4 0x443C0194, 0x01, 0x00000000, 0x00, 0x443C0398 703 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SCLK__SAI4_RX_SYNC 0x443C0194, 0x02, 0x443C059C, 0x01, 0x443C0398 704 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SCLK__EARC_DC_HPD_IN 0x443C0194, 0x03, 0x00000000, 0x00, 0x443C0398 705 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SCLK__XSPI_CLK 0x443C0194, 0x04, 0x443C05E8, 0x01, 0x443C0398 706 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x443C0194, 0x05, 0x00000000, 0x00, 0x443C0398 707 708 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x443C0198, 0x00, 0x00000000, 0x00, 0x443C039C 709 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS0_B__SAI2_RX_DATA_BIT5 0x443C0198, 0x01, 0x00000000, 0x00, 0x443C039C 710 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS0_B__SAI4_RX_BCLK 0x443C0198, 0x02, 0x443C0594, 0x01, 0x443C039C 711 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS0_B__EARC_CEC_OUT 0x443C0198, 0x03, 0x00000000, 0x00, 0x443C039C 712 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS0_B__XSPI_CS 0x443C0198, 0x04, 0x443C05E0, 0x01, 0x443C039C 713 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x443C0198, 0x05, 0x00000000, 0x00, 0x443C039C 714 715 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x443C019C, 0x00, 0x00000000, 0x00, 0x443C03A0 716 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x443C019C, 0x01, 0x443C05A8, 0x01, 0x443C03A0 717 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS1_B__SAI5_TX_DATA_BIT3 0x443C019C, 0x02, 0x00000000, 0x00, 0x443C03A0 718 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS1_B__SAI2_RX_DATA_BIT7 0x443C019C, 0x03, 0x443C0440, 0x01, 0x443C03A0 719 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x443C019C, 0x05, 0x00000000, 0x00, 0x443C03A0 720 721 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CD_B__USDHC2_CD_B 0x443C01A0, 0x00, 0x00000000, 0x00, 0x443C03A4 722 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CD_B__NETC_TMR_1588_TRIG1 0x443C01A0, 0x01, 0x443C0434, 0x01, 0x443C03A4 723 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CD_B__I3C2_SCL 0x443C01A0, 0x02, 0x443C04F8, 0x01, 0x443C03A4 724 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CD_B__FLEXIO1_FLEXIO_BIT0 0x443C01A0, 0x04, 0x443C0468, 0x01, 0x443C03A4 725 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x443C01A0, 0x05, 0x00000000, 0x00, 0x443C03A4 726 727 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CLK__USDHC2_CLK 0x443C01A4, 0x00, 0x00000000, 0x00, 0x443C03A8 728 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CLK__NETC_TMR_1588_PP1 0x443C01A4, 0x01, 0x00000000, 0x00, 0x443C03A8 729 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CLK__I3C2_SDA 0x443C01A4, 0x02, 0x443C04FC, 0x01, 0x443C03A8 730 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CLK__FLEXIO1_FLEXIO_BIT1 0x443C01A4, 0x04, 0x443C046C, 0x01, 0x443C03A8 731 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CLK__GPIO3_IO_BIT1 0x443C01A4, 0x05, 0x00000000, 0x00, 0x443C03A8 732 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CLK__OBSERVE_0 0x443C01A4, 0x06, 0x00000000, 0x00, 0x443C03A8 733 734 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CMD__USDHC2_CMD 0x443C01A8, 0x00, 0x00000000, 0x00, 0x443C03AC 735 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CMD__NETC_TMR_1588_TRIG2 0x443C01A8, 0x01, 0x443C0438, 0x01, 0x443C03AC 736 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CMD__I3C2_PUR 0x443C01A8, 0x02, 0x00000000, 0x00, 0x443C03AC 737 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CMD__I3C2_PUR_B 0x443C01A8, 0x03, 0x00000000, 0x00, 0x443C03AC 738 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CMD__FLEXIO1_FLEXIO_BIT2 0x443C01A8, 0x04, 0x443C0470, 0x01, 0x443C03AC 739 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CMD__GPIO3_IO_BIT2 0x443C01A8, 0x05, 0x00000000, 0x00, 0x443C03AC 740 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_CMD__OBSERVE_1 0x443C01A8, 0x06, 0x00000000, 0x00, 0x443C03AC 741 742 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA0__USDHC2_DATA0 0x443C01AC, 0x00, 0x00000000, 0x00, 0x443C03B0 743 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA0__NETC_TMR_1588_PP2 0x443C01AC, 0x01, 0x00000000, 0x00, 0x443C03B0 744 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA0__CAN2_TX 0x443C01AC, 0x02, 0x00000000, 0x00, 0x443C03B0 745 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA0__FLEXIO1_FLEXIO_BIT3 0x443C01AC, 0x04, 0x443C0474, 0x01, 0x443C03B0 746 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA0__GPIO3_IO_BIT3 0x443C01AC, 0x05, 0x00000000, 0x00, 0x443C03B0 747 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA0__OBSERVE_2 0x443C01AC, 0x06, 0x00000000, 0x00, 0x443C03B0 748 749 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA1__USDHC2_DATA1 0x443C01B0, 0x00, 0x00000000, 0x00, 0x443C03B4 750 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA1__NETC_TMR_1588_CLK 0x443C01B0, 0x01, 0x00000000, 0x00, 0x443C03B4 751 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA1__CAN2_RX 0x443C01B0, 0x02, 0x443C0444, 0x03, 0x443C03B4 752 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA1__FLEXIO1_FLEXIO_BIT4 0x443C01B0, 0x04, 0x443C0478, 0x01, 0x443C03B4 753 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA1__GPIO3_IO_BIT4 0x443C01B0, 0x05, 0x00000000, 0x00, 0x443C03B4 754 755 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA2__USDHC2_DATA2 0x443C01B4, 0x00, 0x00000000, 0x00, 0x443C03B8 756 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA2__NETC_TMR_1588_PP3 0x443C01B4, 0x01, 0x00000000, 0x00, 0x443C03B8 757 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA2__MQS2_RIGHT 0x443C01B4, 0x02, 0x00000000, 0x00, 0x443C03B8 758 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA2__FLEXIO1_FLEXIO_BIT5 0x443C01B4, 0x04, 0x443C047C, 0x01, 0x443C03B8 759 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA2__GPIO3_IO_BIT5 0x443C01B4, 0x05, 0x00000000, 0x00, 0x443C03B8 760 761 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA3__USDHC2_DATA3 0x443C01B8, 0x00, 0x00000000, 0x00, 0x443C03BC 762 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA3__LPTMR2_ALT1 0x443C01B8, 0x01, 0x443C0548, 0x01, 0x443C03BC 763 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA3__MQS2_LEFT 0x443C01B8, 0x02, 0x00000000, 0x00, 0x443C03BC 764 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA3__NETC_TMR_1588_ALARM1 0x443C01B8, 0x03, 0x00000000, 0x00, 0x443C03BC 765 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA3__FLEXIO1_FLEXIO_BIT6 0x443C01B8, 0x04, 0x443C0480, 0x01, 0x443C03BC 766 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_DATA3__GPIO3_IO_BIT6 0x443C01B8, 0x05, 0x00000000, 0x00, 0x443C03BC 767 768 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_RESET_B__USDHC2_RESET_B 0x443C01BC, 0x00, 0x00000000, 0x00, 0x443C03C0 769 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_RESET_B__LPTMR2_ALT2 0x443C01BC, 0x01, 0x443C054C, 0x01, 0x443C03C0 770 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_RESET_B__NETC_TMR_1588_GCLK 0x443C01BC, 0x03, 0x00000000, 0x00, 0x443C03C0 771 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_RESET_B__FLEXIO1_FLEXIO_BIT7 0x443C01BC, 0x04, 0x443C0484, 0x01, 0x443C03C0 772 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x443C01BC, 0x05, 0x00000000, 0x00, 0x443C03C0 773 774 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL 0x443C01C0, 0x00, 0x00000000, 0x00, 0x443C03C4 775 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SCL__I3C1_SCL 0x443C01C0, 0x01, 0x00000000, 0x00, 0x443C03C4 776 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SCL__LPUART1_DCD_B 0x443C01C0, 0x02, 0x00000000, 0x00, 0x443C03C4 777 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SCL__TPM2_CH0 0x443C01C0, 0x03, 0x00000000, 0x00, 0x443C03C4 778 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SCL__UART_RX 0x443C01C0, 0x04, 0x00000000, 0x00, 0x443C03C4 779 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SCL__GPIO1_IO_BIT0 0x443C01C0, 0x05, 0x00000000, 0x00, 0x443C03C4 780 781 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA 0x443C01C4, 0x00, 0x00000000, 0x00, 0x443C03C8 782 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SDA__I3C1_SDA 0x443C01C4, 0x01, 0x00000000, 0x00, 0x443C03C8 783 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SDA__LPUART1_RIN_B 0x443C01C4, 0x02, 0x00000000, 0x00, 0x443C03C8 784 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SDA__TPM2_CH1 0x443C01C4, 0x03, 0x00000000, 0x00, 0x443C03C8 785 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SDA__UART_TX 0x443C01C4, 0x04, 0x00000000, 0x00, 0x443C03C8 786 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C1_SDA__GPIO1_IO_BIT1 0x443C01C4, 0x05, 0x00000000, 0x00, 0x443C03C8 787 788 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL 0x443C01C8, 0x00, 0x00000000, 0x00, 0x443C03CC 789 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SCL__I3C1_PUR 0x443C01C8, 0x01, 0x00000000, 0x00, 0x443C03CC 790 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SCL__LPUART2_DCD_B 0x443C01C8, 0x02, 0x00000000, 0x00, 0x443C03CC 791 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SCL__TPM2_CH2 0x443C01C8, 0x03, 0x00000000, 0x00, 0x443C03CC 792 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SCL__SAI1_RX_SYNC 0x443C01C8, 0x04, 0x00000000, 0x00, 0x443C03CC 793 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SCL__GPIO1_IO_BIT2 0x443C01C8, 0x05, 0x00000000, 0x00, 0x443C03CC 794 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SCL__I3C1_PUR_B 0x443C01C8, 0x06, 0x00000000, 0x00, 0x443C03CC 795 796 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA 0x443C01CC, 0x00, 0x00000000, 0x00, 0x443C03D0 797 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SDA__LPUART2_RIN_B 0x443C01CC, 0x02, 0x00000000, 0x00, 0x443C03D0 798 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SDA__TPM2_CH3 0x443C01CC, 0x03, 0x00000000, 0x00, 0x443C03D0 799 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SDA__SAI1_RX_BCLK 0x443C01CC, 0x04, 0x00000000, 0x00, 0x443C03D0 800 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_I2C2_SDA__GPIO1_IO_BIT3 0x443C01CC, 0x05, 0x00000000, 0x00, 0x443C03D0 801 802 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_RXD__LPUART1_RX 0x443C01D0, 0x00, 0x00000000, 0x00, 0x443C03D4 803 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_RXD__S400_UART_RX 0x443C01D0, 0x01, 0x00000000, 0x00, 0x443C03D4 804 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_RXD__LPSPI2_SIN 0x443C01D0, 0x02, 0x00000000, 0x00, 0x443C03D4 805 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_RXD__TPM1_CH0 0x443C01D0, 0x03, 0x00000000, 0x00, 0x443C03D4 806 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_RXD__GPIO1_IO_BIT4 0x443C01D0, 0x05, 0x00000000, 0x00, 0x443C03D4 807 808 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_TXD__LPUART1_TX 0x443C01D4, 0x00, 0x00000000, 0x00, 0x443C03D8 809 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_TXD__S400_UART_TX 0x443C01D4, 0x01, 0x00000000, 0x00, 0x443C03D8 810 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_TXD__LPSPI2_PCS0 0x443C01D4, 0x02, 0x00000000, 0x00, 0x443C03D8 811 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_TXD__TPM1_CH1 0x443C01D4, 0x03, 0x00000000, 0x00, 0x443C03D8 812 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART1_TXD__GPIO1_IO_BIT5 0x443C01D4, 0x05, 0x00000000, 0x00, 0x443C03D8 813 814 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_RXD__LPUART2_RX 0x443C01D8, 0x00, 0x00000000, 0x00, 0x443C03DC 815 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_RXD__LPUART1_CTS_B 0x443C01D8, 0x01, 0x00000000, 0x00, 0x443C03DC 816 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_RXD__LPSPI2_SOUT 0x443C01D8, 0x02, 0x00000000, 0x00, 0x443C03DC 817 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_RXD__TPM1_CH2 0x443C01D8, 0x03, 0x00000000, 0x00, 0x443C03DC 818 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_RXD__SAI1_MCLK 0x443C01D8, 0x04, 0x443C041C, 0x00, 0x443C03DC 819 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_RXD__GPIO1_IO_BIT6 0x443C01D8, 0x05, 0x00000000, 0x00, 0x443C03DC 820 821 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_TXD__LPUART2_TX 0x443C01DC, 0x00, 0x00000000, 0x00, 0x443C03E0 822 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_TXD__LPUART1_RTS_B 0x443C01DC, 0x01, 0x00000000, 0x00, 0x443C03E0 823 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_TXD__LPSPI2_SCK 0x443C01DC, 0x02, 0x00000000, 0x00, 0x443C03E0 824 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_TXD__TPM1_CH3 0x443C01DC, 0x03, 0x00000000, 0x00, 0x443C03E0 825 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_UART2_TXD__GPIO1_IO_BIT7 0x443C01DC, 0x05, 0x00000000, 0x00, 0x443C03E0 826 827 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_CLK__PDM_CLK 0x443C01E0, 0x00, 0x00000000, 0x00, 0x443C03E4 828 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_CLK__MQS1_LEFT 0x443C01E0, 0x01, 0x00000000, 0x00, 0x443C03E4 829 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_CLK__LPTMR1_ALT1 0x443C01E0, 0x04, 0x00000000, 0x00, 0x443C03E4 830 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_CLK__GPIO1_IO_BIT8 0x443C01E0, 0x05, 0x00000000, 0x00, 0x443C03E4 831 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_CLK__CAN1_TX 0x443C01E0, 0x06, 0x00000000, 0x00, 0x443C03E4 832 833 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM_BIT0 \ 834 0x443C01E4, 0x00, 0x443C040C, 0x00, 0x443C03E8 835 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x443C01E4, 0x01, 0x00000000, 0x00, 0x443C03E8 836 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x443C01E4, 0x02, 0x00000000, 0x00, 0x443C03E8 837 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x443C01E4, 0x03, 0x00000000, 0x00, 0x443C03E8 838 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x443C01E4, 0x04, 0x00000000, 0x00, 0x443C03E8 839 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM0__GPIO1_IO_BIT9 0x443C01E4, 0x05, 0x00000000, 0x00, 0x443C03E8 840 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX 0x443C01E4, 0x06, 0x443C0408, 0x00, 0x443C03E8 841 842 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM_BIT1 \ 843 0x443C01E8, 0x00, 0x443C0410, 0x00, 0x443C03EC 844 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x443C01E8, 0x01, 0x00000000, 0x00, 0x443C03EC 845 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x443C01E8, 0x02, 0x00000000, 0x00, 0x443C03EC 846 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x443C01E8, 0x03, 0x00000000, 0x00, 0x443C03EC 847 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x443C01E8, 0x04, 0x00000000, 0x00, 0x443C03EC 848 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO_BIT10 0x443C01E8, 0x05, 0x00000000, 0x00, 0x443C03EC 849 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PDM_BIT_STREAM1__EXT_CLK1 0x443C01E8, 0x06, 0x443C0420, 0x00, 0x443C03EC 850 851 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x443C01EC, 0x00, 0x00000000, 0x00, 0x443C03F0 852 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXFS__SAI1_TX_DATA_BIT1 0x443C01EC, 0x01, 0x00000000, 0x00, 0x443C03F0 853 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXFS__LPSPI1_PCS0 0x443C01EC, 0x02, 0x00000000, 0x00, 0x443C03F0 854 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXFS__LPUART2_DTR_B 0x443C01EC, 0x03, 0x00000000, 0x00, 0x443C03F0 855 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXFS__MQS1_LEFT 0x443C01EC, 0x04, 0x00000000, 0x00, 0x443C03F0 856 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXFS__GPIO1_IO_BIT11 0x443C01EC, 0x05, 0x00000000, 0x00, 0x443C03F0 857 858 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXC__SAI1_TX_BCLK 0x443C01F0, 0x00, 0x00000000, 0x00, 0x443C03F4 859 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXC__LPUART2_CTS_B 0x443C01F0, 0x01, 0x00000000, 0x00, 0x443C03F4 860 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXC__LPSPI1_SIN 0x443C01F0, 0x02, 0x00000000, 0x00, 0x443C03F4 861 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXC__LPUART1_DSR_B 0x443C01F0, 0x03, 0x00000000, 0x00, 0x443C03F4 862 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXC__CAN1_RX 0x443C01F0, 0x04, 0x443C0408, 0x01, 0x443C03F4 863 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXC__GPIO1_IO_BIT12 0x443C01F0, 0x05, 0x00000000, 0x00, 0x443C03F4 864 865 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXD0__SAI1_TX_DATA_BIT0 0x443C01F4, 0x00, 0x00000000, 0x00, 0x443C03F8 866 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXD0__LPUART2_RTS_B 0x443C01F4, 0x01, 0x00000000, 0x00, 0x443C03F8 867 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXD0__LPSPI1_SCK 0x443C01F4, 0x02, 0x00000000, 0x00, 0x443C03F8 868 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXD0__LPUART1_DTR_B 0x443C01F4, 0x03, 0x00000000, 0x00, 0x443C03F8 869 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXD0__CAN1_TX 0x443C01F4, 0x04, 0x00000000, 0x00, 0x443C03F8 870 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_TXD0__GPIO1_IO_BIT13 0x443C01F4, 0x05, 0x00000000, 0x00, 0x443C03F8 871 872 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_RXD0__SAI1_RX_DATA_BIT0 0x443C01F8, 0x00, 0x00000000, 0x00, 0x443C03FC 873 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_RXD0__SAI1_MCLK 0x443C01F8, 0x01, 0x443C041C, 0x01, 0x443C03FC 874 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_RXD0__LPSPI1_SOUT 0x443C01F8, 0x02, 0x00000000, 0x00, 0x443C03FC 875 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_RXD0__LPUART2_DSR_B 0x443C01F8, 0x03, 0x00000000, 0x00, 0x443C03FC 876 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_RXD0__MQS1_RIGHT 0x443C01F8, 0x04, 0x00000000, 0x00, 0x443C03FC 877 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SAI1_RXD0__GPIO1_IO_BIT14 0x443C01F8, 0x05, 0x00000000, 0x00, 0x443C03FC 878 879 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_WDOG_ANY__WDOG_ANY 0x443C01FC, 0x00, 0x00000000, 0x00, 0x443C0400 880 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_WDOG_ANY__FCCU_EOUT1 0x443C01FC, 0x01, 0x00000000, 0x00, 0x443C0400 881 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_WDOG_ANY__GPIO1_IO_BIT15 0x443C01FC, 0x05, 0x00000000, 0x00, 0x443C0400 882 /*@}*/ 883 884 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_MUX_MODE_MASK (0x7U) 885 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_MUX_MODE_SHIFT (0U) 886 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_MUX_MODE(x) \ 887 (((uint32_t)(((uint32_t)(x)) << HAL_PINCTRL_PLATFORM_IOMUXC_PAD_MUX_MODE_SHIFT)) & \ 888 HAL_PINCTRL_PLATFORM_IOMUXC_PAD_MUX_MODE_MASK) 889 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SION_MASK (0x10) 890 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SION_SHIFT (4U) 891 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SION(x) \ 892 (((uint32_t)(((uint32_t)(x)) << HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SION_SHIFT)) & \ 893 HAL_PINCTRL_PLATFORM_IOMUXC_PAD_SION_MASK) 894 895 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DSE_MASK (0x7EU) 896 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DSE_SHIFT (1U) 897 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DSE(x) \ 898 (((uint32_t)(((uint32_t)(x)) << HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DSE_SHIFT)) & \ 899 HAL_PINCTRL_PLATFORM_IOMUXC_PAD_DSE_MASK) 900 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_FSEL1_MASK (0x180U) 901 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_FSEL1_SHIFT (7U) 902 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_FSEL1(x) \ 903 (((uint32_t)(((uint32_t)(x)) << HAL_PINCTRL_PLATFORM_IOMUXC_PAD_FSEL1_SHIFT)) & \ 904 HAL_PINCTRL_PLATFORM_IOMUXC_PAD_FSEL1_MASK) 905 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PU_MASK (0x200U) 906 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PU_SHIFT (9U) 907 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PU(x) \ 908 (((uint32_t)(((uint32_t)(x)) << HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PU_SHIFT)) & \ 909 HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PU_MASK) 910 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PD_MASK (0x400U) 911 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PD_SHIFT (10U) 912 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PD(x) \ 913 (((uint32_t)(((uint32_t)(x)) << HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PD_SHIFT)) & \ 914 HAL_PINCTRL_PLATFORM_IOMUXC_PAD_PD_MASK) 915 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_OD_MASK (0x800U) 916 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_OD_SHIFT (11U) 917 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_OD(x) \ 918 (((uint32_t)(((uint32_t)(x)) << HAL_PINCTRL_PLATFORM_IOMUXC_PAD_OD_SHIFT)) & \ 919 HAL_PINCTRL_PLATFORM_IOMUXC_PAD_OD_MASK) 920 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_HYS_MASK (0x1000U) 921 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_HYS_SHIFT (11U) 922 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_HYS(x) \ 923 (((uint32_t)(((uint32_t)(x)) << HAL_PINCTRL_PLATFORM_IOMUXC_PAD_HYS_SHIFT)) & \ 924 HAL_PINCTRL_PLATFORM_IOMUXC_PAD_HYS_MASK) 925 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_APC_MASK (0xFF000000U) 926 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_APC_SHIFT (24U) 927 #define HAL_PINCTRL_PLATFORM_IOMUXC_PAD_APC(x) \ 928 (((uint32_t)(((uint32_t)(x)) << HAL_PINCTRL_PLATFORM_IOMUXC_PAD_APC_SHIFT)) & \ 929 HAL_PINCTRL_PLATFORM_IOMUXC_PAD_APC_MASK) 930 931 /*@}*/ 932 933 #if defined(__cplusplus) 934 } 935 #endif /*__cplusplus */ 936 937 /*! @}*/ 938 939 #endif /* _HAL_PINCTRL_PLATFORM_H_ */
