1 /*
2 * Copyright (c) 2023 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_VPR_CSR_H__
35 #define NRF_VPR_CSR_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_vpr_csr_hal VPR CSR HAL
45 * @{
46 * @ingroup nrf_vpr
47 * @brief Hardware access layer for managing the VPR RISC-V CPU Control
48 * and Status Registers (VPR CSR).
49 */
50
51 #if defined(VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Msk) || defined(__NRFX_DOXYGEN__)
52 /** @brief Symbol indicating whether setting high priority for VPR RAM transactions is present. */
53 #define NRF_VPR_HAS_RAM_PRIO 1
54 #else
55 #define NRF_VPR_HAS_RAM_PRIO 0
56 #endif
57
58 /** @brief Nordic key for CSR writes. */
59 #define NRF_VPR_CSR_NORDIC_KEY_MASK \
60 (VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Enabled << VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Pos)
61
62 /** @brief Interrupt threshold levels. */
63 typedef enum
64 {
65 NRF_VPR_CSR_INT_THRESHOLD_DISABLED = VPRCSR_MINTTHRESH_TH_DISABLED, ///< Threshold disabled.
66 NRF_VPR_CSR_INT_THRESHOLD_LEVEL0 = VPRCSR_MINTTHRESH_TH_THRESHLEVEL0, ///< Threshold level 0.
67 NRF_VPR_CSR_INT_THRESHOLD_LEVEL1 = VPRCSR_MINTTHRESH_TH_THRESHLEVEL1, ///< Threshold level 1.
68 NRF_VPR_CSR_INT_THRESHOLD_LEVEL2 = VPRCSR_MINTTHRESH_TH_THRESHLEVEL2, ///< Threshold level 2.
69 NRF_VPR_CSR_INT_THRESHOLD_LEVEL3 = VPRCSR_MINTTHRESH_TH_THRESHLEVEL3, ///< Threshold level 3.
70 } nrf_vpr_csr_int_threshold_t;
71
72 /** @brief Trap causes. */
73 typedef enum
74 {
75 NRF_VPR_CSR_TRAP_CAUSE_INSTR_ADDR_MISALIGNED = VPRCSR_MCAUSE_EXCEPTIONCODE_INSTADDRMISALIGN, ///< Instruction address misaligned.
76 NRF_VPR_CSR_TRAP_CAUSE_INSTR_ACCESS_FAULT = VPRCSR_MCAUSE_EXCEPTIONCODE_INSTACCESSFAULT, ///< Instruction access fault.
77 NRF_VPR_CSR_TRAP_CAUSE_INSTR_ILLEGAL = VPRCSR_MCAUSE_EXCEPTIONCODE_ILLEGALINST, ///< Illegal instruction.
78 NRF_VPR_CSR_TRAP_CAUSE_BREAKPOINT = VPRCSR_MCAUSE_EXCEPTIONCODE_BKPT, ///< Breakpoint.
79 NRF_VPR_CSR_TRAP_CAUSE_LOAD_ADDR_MISALIGNED = VPRCSR_MCAUSE_EXCEPTIONCODE_LOADADDRMISALIGN, ///< Load address misaligned.
80 NRF_VPR_CSR_TRAP_CAUSE_LOAD_ACCESS_FAULT = VPRCSR_MCAUSE_EXCEPTIONCODE_LOADACCESSFAULT, ///< Load access fault.
81 NRF_VPR_CSR_TRAP_CAUSE_STORE_ADDR_MISALIGNED = VPRCSR_MCAUSE_EXCEPTIONCODE_STOREADDRMISALIGN, ///< Store/AMO address misaligned.
82 NRF_VPR_CSR_TRAP_CAUSE_STORE_ACCESS_FAULT = VPRCSR_MCAUSE_EXCEPTIONCODE_STOREACCESSFAULT, ///< Store/AMO access misaligned.
83 NRF_VPR_CSR_TRAP_CAUSE_ECALL_M = VPRCSR_MCAUSE_EXCEPTIONCODE_ECALLMMODE, ///< Environment call M-mode.
84 NRF_VPR_CSR_TRAP_CAUSE_STACKING_BUS_FAULT = VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTSTACKING, ///< Bus fault on stacking.
85 NRF_VPR_CSR_TRAP_CAUSE_STACKING_UNALIGNED = VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNSTACKING, ///< Misaligned Stacking.
86 NRF_VPR_CSR_TRAP_CAUSE_VECTOR_FAULT = VPRCSR_MCAUSE_EXCEPTIONCODE_INTVECTORFAULT, ///< Interrupt Vector Fault.
87 NRF_VPR_CSR_TRAP_CAUSE_STACKING_UNALIGNED_EX = VPRCSR_MCAUSE_EXCEPTIONCODE_STACKINGEXCFAULT, ///< Fault on Exception Stacking.
88 NRF_VPR_CSR_TRAP_CAUSE_UNSTACKING_UNALIGNED = VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNUNSTACKING, ///< Misaligned Unstacking.
89 NRF_VPR_CSR_TRAP_CAUSE_UNSTACKING_BUS_FAULT = VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTUNSTACKING, ///< Bus fault on unstacking.
90 NRF_VPR_CSR_TRAP_CAUSE_STORE_TIMEOUT_FAULT = VPRCSR_MCAUSE_EXCEPTIONCODE_STORETIMEOUTFAULT, ///< Store timeout fault.
91 NRF_VPR_CSR_TRAP_CAUSE_LOAD_TIMEOUT_FAULT = VPRCSR_MCAUSE_EXCEPTIONCODE_LOADTIMEOUTFAULT, ///< Load timeout fault.
92 } nrf_vpr_csr_trap_cause_t;
93
94 /** @brief Sleep states. */
95 typedef enum
96 {
97 NRF_VPR_CSR_SLEEP_STATE_WAIT = VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_WAIT, ///< During sleep, clock is not turned off.
98 NRF_VPR_CSR_SLEEP_STATE_RESET = VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_RESET, ///< Sleep mode out of reset.
99 NRF_VPR_CSR_SLEEP_STATE_SLEEP = VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_SLEEP, ///< During sleep, clock is turned off.
100 NRF_VPR_CSR_SLEEP_STATE_DEEP_SLEEP = VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_DEEPSLEEP, ///< During sleep, clock and power are turned off.
101 NRF_VPR_CSR_SLEEP_STATE_HIBERNATE = VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_HIBERNATE, ///< During sleep, clock is turned off. All the registers are saved automatically. Restart by a reset.
102 } nrf_vpr_csr_sleep_state_t;
103
104 /** @brief Function for enabling the interrupts in machine mode. */
105 NRF_STATIC_INLINE void nrf_vpr_csr_machine_interrupts_enable(void);
106
107 /** @brief Function for disabling the interrupts in machine mode. */
108 NRF_STATIC_INLINE void nrf_vpr_csr_machine_interrupts_disable(void);
109
110 /**
111 * @brief Function for checking whether interrupts are enabled in machine mode.
112 *
113 * @retval true Interrupts are enabled.
114 * @retval false Interrupts are disabled.
115 */
116 NRF_STATIC_INLINE bool nrf_vpr_csr_machine_interrupts_check(void);
117
118 /**
119 * @brief Function for setting the base address of trap vector table.
120 *
121 * @param[in] address Machine trap vector table base address to be set.
122 * Has to be aligned on 64-byte or greater power-of-two boundary.
123 */
124 NRF_STATIC_INLINE void nrf_vpr_csr_machine_trap_vector_table_addr_set(uint32_t address);
125
126 /**
127 * @brief Function for getting the machine trap vector table base address.
128 *
129 * @return Machine trap vector table base address.
130 */
131 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_machine_trap_vector_table_addr_get(void);
132
133 /**
134 * @brief Function for getting the machine exception program counter.
135 *
136 * @return Virtual address of the instruction that was interrupted or that encountered the exception.
137 */
138 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_machine_exception_pc_get(void);
139
140 /**
141 * @brief Function for getting the machine trap cause exception code.
142 *
143 * @return Exception code.
144 */
145 NRF_STATIC_INLINE nrf_vpr_csr_trap_cause_t nrf_vpr_csr_machine_trap_cause_code_get(void);
146
147 /**
148 * @brief Function for checking the state of the interrupt bit for machine trap.
149 *
150 * @retval true Trap was caused by an interrupt.
151 * @retval false Trap was not caused by an interrupt.
152 */
153 NRF_STATIC_INLINE bool nrf_vpr_csr_machine_trap_interrupt_check(void);
154
155 /**
156 * @brief Function for getting the machine trap value.
157 *
158 * @return Exception-specific information.
159 */
160 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_machine_trap_value_get(void);
161
162 /**
163 * @brief Function for setting the machine mode interrupt level threshold.
164 *
165 * @param[in] th Machine mode interrupt level threshold to be set.
166 */
167 NRF_STATIC_INLINE void nrf_vpr_csr_machine_interrupt_threshold_set(nrf_vpr_csr_int_threshold_t th);
168
169 /**
170 * @brief Function for getting the machine mode interrupt level threshold.
171 *
172 * @return Machine mode interrupt level threshold.
173 */
174 NRF_STATIC_INLINE nrf_vpr_csr_int_threshold_t nrf_vpr_csr_machine_interrupt_threshold_get(void);
175
176 /**
177 * @brief Function for enabling or disabling the Cycle Counter.
178 *
179 * @param[in] enable True if Cycle Counter is to be enabled, false otherwise.
180 */
181 NRF_STATIC_INLINE void nrf_vpr_csr_machine_cycle_counter_enable_set(bool enable);
182
183 /**
184 * @brief Function for checking whether the Cycle Counter is enabled.
185 *
186 * @retval true Cycle counter is enabled.
187 * @retval false Cycle counter is disabled.
188 */
189 NRF_STATIC_INLINE bool nrf_vpr_csr_machine_cycle_counter_enable_check(void);
190
191 /**
192 * @brief Function for getting the machine cycle counter.
193 *
194 * @return Number of clock cycles executed by the processor core.
195 */
196 NRF_STATIC_INLINE uint64_t nrf_vpr_csr_machine_cycle_counter_get(void);
197
198 /**
199 * @brief Function for enabling or disabling the Instruction Counter.
200 *
201 * @param[in] enable True if Instruction Counter is to be enabled, false otherwise.
202 */
203 NRF_STATIC_INLINE void nrf_vpr_csr_machine_instruction_counter_enable_set(bool enable);
204
205 /**
206 * @brief Function for checking whether the Instruction Counter is enabled.
207 *
208 * @retval true Instruction counter is enabled.
209 * @retval false Instruction counter is disabled.
210 */
211 NRF_STATIC_INLINE bool nrf_vpr_csr_machine_instruction_counter_enable_check(void);
212 /**
213 * @brief Function for getting the machine instruction counter.
214 *
215 * @return Number of instructions exectuted by the processor.
216 */
217 NRF_STATIC_INLINE uint64_t nrf_vpr_csr_machine_instruction_counter_get(void);
218
219 /**
220 * @brief Function for enabling or disabling the Real-Time Peripherals.
221 *
222 * @param[in] enable True if RT Perhiperals are to be enabled, false otherwise.
223 */
224 NRF_STATIC_INLINE void nrf_vpr_csr_rtperiph_enable_set(bool enable);
225
226 /**
227 * @brief Function for checking whether the Real-Time Peripherals are enabled.
228 *
229 * @retval true RT Peripherals are enabled.
230 * @retval false RT Peripherals are disabled.
231 */
232 NRF_STATIC_INLINE bool nrf_vpr_csr_rtperiph_enable_check(void);
233
234 /**
235 * @brief Function for enabling or disabling the remap functionality.
236 *
237 * @param[in] enable True if remap is to be enabled, false otherwise.
238 */
239 NRF_STATIC_INLINE void nrf_vpr_csr_remap_enable_set(bool enable);
240
241 /**
242 * @brief Function for checking whether the remap functionality is enabled.
243 *
244 * @retval true Remap is enabled.
245 * @retval false Remap is disabled.
246 */
247 NRF_STATIC_INLINE bool nrf_vpr_csr_remap_enable_check(void);
248 /**
249 * @brief Function for enabling or disabling the generation of IRQ at position CNT_IRQ_POSITION.
250 *
251 * @param[in] enable True if generation of IRQ at position CNT_IRQ_POSITION is to be enabled, false otherwise.
252 */
253 NRF_STATIC_INLINE void nrf_vpr_csr_cnt_irq_enable_set(bool enable);
254
255 /**
256 * @brief Function for checking whether the generation of IRQ at position CNT_IRQ_POSITION is enabled.
257 *
258 * @retval true Generation of IRQ is enabled.
259 * @retval false Generation of IRQ is disabled.
260 */
261 NRF_STATIC_INLINE bool nrf_vpr_csr_cnt_irq_enable_check(void);
262
263 #if NRF_VPR_HAS_RAM_PRIO
264 /**
265 * @brief Function for enabling or disabling the high priority for VPR RAM transactions on bus.
266 *
267 * @param[in] enable True if high priority is to be enabled, false otherwise.
268 */
269 NRF_STATIC_INLINE void nrf_vpr_csr_ram_prio_enable_set(bool enable);
270
271 /**
272 * @brief Function for checking whether the high priority for VPR RAM transactions on bus is enabled.
273 *
274 * @retval true High priority is enabled.
275 * @retval false High priority is disabled.
276 */
277 NRF_STATIC_INLINE bool nrf_vpr_csr_ram_prio_enable_check(void);
278 #endif
279
280 /**
281 * @brief Function for setting the sleep state.
282 *
283 * @param[in] state Sleep state to be set.
284 */
285 NRF_STATIC_INLINE void nrf_vpr_csr_sleep_state_set(nrf_vpr_csr_sleep_state_t state);
286
287 /**
288 * @brief Function for getting the sleep state.
289 *
290 * @return Current sleep state.
291 */
292 NRF_STATIC_INLINE nrf_vpr_csr_sleep_state_t nrf_vpr_csr_sleep_state_get(void);
293
294 /**
295 * @brief Function for enabling or disabling the return to sleep functionality.
296 *
297 * @param[in] enable True if CPU should be forced to return to sleep when it returns in a non-handler program,
298 * false otherwise.
299 */
300 NRF_STATIC_INLINE void nrf_vpr_csr_return_to_sleep_set(bool enable);
301
302 /**
303 * @brief Function for checking whether the return to sleep functionality is enabled.
304 *
305 * @retval true Return to sleep functionality is enabled.
306 * @retval false Return to sleep functionality is disabled.
307 */
308 NRF_STATIC_INLINE bool nrf_vpr_csr_return_to_sleep_check(void);
309
310 /**
311 * @brief Function for enabling or disabling the stack on sleep functionality.
312 *
313 * @param[in] enable True if CPU should be forced to stack the context before going to sleep (used in order to have a fast wake-up),
314 * false otherwise.
315 */
316 NRF_STATIC_INLINE void nrf_vpr_csr_stack_on_sleep_set(bool enable);
317
318 /**
319 * @brief Function for checking whether the stack on sleep functionality is enabled.
320 *
321 * @retval true Stack on sleep functionality is enabled.
322 * @retval false Stack on sleep functionality is disabled.
323 */
324 NRF_STATIC_INLINE bool nrf_vpr_csr_stack_on_sleep_check(void);
325
326 /**
327 * @brief Function for enabling or disabling the CLIC round robin arbitration.
328 *
329 * @param[in] enable True if round robin arbitration should be used for CLIC interrupt requests,
330 * false otherwise.
331 */
332 NRF_STATIC_INLINE void nrf_vpr_csr_clic_round_robin_set(bool enable);
333
334 /**
335 * @brief Function for checking whether the CLIC round robin arbitration is enabled.
336 *
337 * @retval true CLIC round robin arbitration is enabled.
338 * @retval false CLIC round robin arbitration is disabled.
339 */
340 NRF_STATIC_INLINE bool nrf_vpr_csr_clic_round_robin_check(void);
341
342 /**
343 * @brief Function for enabling or disabling the unrecoverable return functionality.
344 *
345 * @param[in] enable True if unrecoverable return from exception is to be forced, false otherwise.
346 */
347 NRF_STATIC_INLINE void nrf_vpr_csr_unrecoverable_return_set(bool enable);
348
349 /**
350 * @brief Function for checking whether the unrecoverable return is enabled.
351 *
352 * @retval true Unrecoverable return is enabled.
353 * @retval false Unrecoverable return is disabled.
354 */
355 NRF_STATIC_INLINE bool nrf_vpr_csr_unrecoverable_return_check(void);
356
357 #ifndef NRF_DECLARE_ONLY
nrf_vpr_csr_machine_interrupts_enable(void)358 NRF_STATIC_INLINE void nrf_vpr_csr_machine_interrupts_enable(void)
359 {
360 nrf_csr_set_bits(VPRCSR_MSTATUS, VPRCSR_MSTATUS_MIE_Msk);
361 }
362
nrf_vpr_csr_machine_interrupts_disable(void)363 NRF_STATIC_INLINE void nrf_vpr_csr_machine_interrupts_disable(void)
364 {
365 nrf_csr_clear_bits(VPRCSR_MSTATUS, VPRCSR_MSTATUS_MIE_Msk);
366 }
367
nrf_vpr_csr_machine_interrupts_check(void)368 NRF_STATIC_INLINE bool nrf_vpr_csr_machine_interrupts_check(void)
369 {
370 return nrf_csr_read(VPRCSR_MSTATUS) & VPRCSR_MSTATUS_MIE_Msk;
371 }
372
nrf_vpr_csr_machine_trap_vector_table_addr_set(uint32_t address)373 NRF_STATIC_INLINE void nrf_vpr_csr_machine_trap_vector_table_addr_set(uint32_t address)
374 {
375 NRFX_ASSERT(!(address & 0xF));
376
377 nrf_csr_write(VPRCSR_MTVT, address);
378 }
379
nrf_vpr_csr_machine_trap_vector_table_addr_get(void)380 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_machine_trap_vector_table_addr_get(void)
381 {
382 return nrf_csr_read(VPRCSR_MTVT);
383 }
384
nrf_vpr_csr_machine_exception_pc_get(void)385 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_machine_exception_pc_get(void)
386 {
387 return nrf_csr_read(VPRCSR_MEPC);
388 }
389
nrf_vpr_csr_machine_trap_cause_code_get(void)390 NRF_STATIC_INLINE nrf_vpr_csr_trap_cause_t nrf_vpr_csr_machine_trap_cause_code_get(void)
391 {
392 return (nrf_vpr_csr_trap_cause_t)((nrf_csr_read(VPRCSR_MCAUSE)
393 & VPRCSR_MCAUSE_EXCEPTIONCODE_Msk)
394 >> VPRCSR_MCAUSE_EXCEPTIONCODE_Pos);
395 }
396
nrf_vpr_csr_machine_trap_interrupt_check(void)397 NRF_STATIC_INLINE bool nrf_vpr_csr_machine_trap_interrupt_check(void)
398 {
399 return (nrf_csr_read(VPRCSR_MCAUSE) & VPRCSR_MCAUSE_INTERRUPT_Msk) >> VPRCSR_MCAUSE_INTERRUPT_Pos;
400 }
401
nrf_vpr_csr_machine_trap_value_get(void)402 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_machine_trap_value_get(void)
403 {
404 return nrf_csr_read(VPRCSR_MTVAL);
405 }
406
nrf_vpr_csr_machine_interrupt_threshold_set(nrf_vpr_csr_int_threshold_t th)407 NRF_STATIC_INLINE void nrf_vpr_csr_machine_interrupt_threshold_set(nrf_vpr_csr_int_threshold_t th)
408 {
409 nrf_csr_write(VPRCSR_MINTTHRESH, (th << VPRCSR_MINTTHRESH_TH_Pos));
410 }
411
nrf_vpr_csr_machine_interrupt_threshold_get(void)412 NRF_STATIC_INLINE nrf_vpr_csr_int_threshold_t nrf_vpr_csr_machine_interrupt_threshold_get(void)
413 {
414 return (nrf_csr_read(VPRCSR_MINTTHRESH) & VPRCSR_MINTTHRESH_TH_Msk) >> VPRCSR_MINTTHRESH_TH_Pos;
415 }
416
nrf_vpr_csr_machine_cycle_counter_enable_set(bool enable)417 NRF_STATIC_INLINE void nrf_vpr_csr_machine_cycle_counter_enable_set(bool enable)
418 {
419 uint32_t reg = nrf_csr_read(VPRCSR_MCOUNTINHIBIT);
420
421 reg = (reg & ~VPRCSR_MCOUNTINHIBIT_CY_Msk) | (enable ?
422 (VPRCSR_MCOUNTINHIBIT_CY_INCREMENT << VPRCSR_MCOUNTINHIBIT_CY_Pos) :
423 (VPRCSR_MCOUNTINHIBIT_CY_INHIBIT << VPRCSR_MCOUNTINHIBIT_CY_Pos));
424
425 nrf_csr_write(VPRCSR_MCOUNTINHIBIT, reg);
426 }
427
nrf_vpr_csr_machine_cycle_counter_enable_check(void)428 NRF_STATIC_INLINE bool nrf_vpr_csr_machine_cycle_counter_enable_check(void)
429 {
430 uint32_t reg = nrf_csr_read(VPRCSR_MCOUNTINHIBIT);
431
432 return (reg & (VPRCSR_MCOUNTINHIBIT_CY_INHIBIT << VPRCSR_MCOUNTINHIBIT_CY_Pos)) ? false : true;
433 }
434
nrf_vpr_csr_machine_cycle_counter_get(void)435 NRF_STATIC_INLINE uint64_t nrf_vpr_csr_machine_cycle_counter_get(void)
436 {
437 return nrf_csr_read(VPRCSR_MCYCLE) | ((uint64_t)nrf_csr_read(VPRCSR_MCYCLEH) << 32);
438 }
439
nrf_vpr_csr_machine_instruction_counter_enable_set(bool enable)440 NRF_STATIC_INLINE void nrf_vpr_csr_machine_instruction_counter_enable_set(bool enable)
441 {
442 uint32_t reg = nrf_csr_read(VPRCSR_MCOUNTINHIBIT);
443
444 reg = (reg & ~VPRCSR_MCOUNTINHIBIT_IR_Msk) | (enable ?
445 (VPRCSR_MCOUNTINHIBIT_IR_INCREMENT << VPRCSR_MCOUNTINHIBIT_IR_Pos) :
446 (VPRCSR_MCOUNTINHIBIT_IR_INHIBIT << VPRCSR_MCOUNTINHIBIT_IR_Pos));
447
448 nrf_csr_write(VPRCSR_MCOUNTINHIBIT, reg);
449 }
450
nrf_vpr_csr_machine_instruction_counter_enable_check(void)451 NRF_STATIC_INLINE bool nrf_vpr_csr_machine_instruction_counter_enable_check(void)
452 {
453 uint32_t reg = nrf_csr_read(VPRCSR_MCOUNTINHIBIT);
454
455 return (reg & (VPRCSR_MCOUNTINHIBIT_IR_INHIBIT << VPRCSR_MCOUNTINHIBIT_IR_Pos)) ? false : true;
456 }
457
nrf_vpr_csr_machine_instruction_counter_get(void)458 NRF_STATIC_INLINE uint64_t nrf_vpr_csr_machine_instruction_counter_get(void)
459 {
460 return nrf_csr_read(VPRCSR_MINSTRET) | ((uint64_t)nrf_csr_read(VPRCSR_MINSTRETH) << 32);
461 }
462
nrf_vpr_csr_rtperiph_enable_set(bool enable)463 NRF_STATIC_INLINE void nrf_vpr_csr_rtperiph_enable_set(bool enable)
464 {
465 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_VPRNORDICCTRL);
466 reg = (reg & ~VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Msk) | NRF_VPR_CSR_NORDIC_KEY_MASK;
467
468 reg |= ((enable ? VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Enabled :
469 VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Disabled)
470 << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos) | NRF_VPR_CSR_NORDIC_KEY_MASK;
471
472 nrf_csr_write(VPRCSR_NORDIC_VPRNORDICCTRL, reg);
473 }
474
nrf_vpr_csr_rtperiph_enable_check(void)475 NRF_STATIC_INLINE bool nrf_vpr_csr_rtperiph_enable_check(void)
476 {
477 return (nrf_csr_read(VPRCSR_NORDIC_VPRNORDICCTRL) & VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Msk)
478 >> VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos;
479 }
480
nrf_vpr_csr_remap_enable_set(bool enable)481 NRF_STATIC_INLINE void nrf_vpr_csr_remap_enable_set(bool enable)
482 {
483 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_VPRNORDICCTRL);
484 reg = (reg & ~VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Msk) | NRF_VPR_CSR_NORDIC_KEY_MASK;
485
486 reg |= ((enable ? VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Enabled :
487 VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Disabled)
488 << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos) | NRF_VPR_CSR_NORDIC_KEY_MASK;
489
490 nrf_csr_write(VPRCSR_NORDIC_VPRNORDICCTRL, reg);
491 }
492
nrf_vpr_csr_remap_enable_check(void)493 NRF_STATIC_INLINE bool nrf_vpr_csr_remap_enable_check(void)
494 {
495 return (nrf_csr_read(VPRCSR_NORDIC_VPRNORDICCTRL) & VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Msk)
496 >> VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos;
497 }
498
nrf_vpr_csr_cnt_irq_enable_set(bool enable)499 NRF_STATIC_INLINE void nrf_vpr_csr_cnt_irq_enable_set(bool enable)
500 {
501 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_VPRNORDICCTRL);
502 reg &= ~(VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Msk | NRF_VPR_CSR_NORDIC_KEY_MASK);
503
504 reg |= ((enable ? VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Enabled :
505 VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Disabled)
506 << VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos) | NRF_VPR_CSR_NORDIC_KEY_MASK;
507
508 nrf_csr_write(VPRCSR_NORDIC_VPRNORDICCTRL, reg);
509 }
510
nrf_vpr_csr_cnt_irq_enable_check(void)511 NRF_STATIC_INLINE bool nrf_vpr_csr_cnt_irq_enable_check(void)
512 {
513 return (nrf_csr_read(VPRCSR_NORDIC_VPRNORDICCTRL) & VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Msk)
514 >> VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos;
515 }
516
517 #if NRF_VPR_HAS_RAM_PRIO
nrf_vpr_csr_ram_prio_enable_set(bool enable)518 NRF_STATIC_INLINE void nrf_vpr_csr_ram_prio_enable_set(bool enable)
519 {
520 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_VPRNORDICCTRL);
521 reg = (reg & ~VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Msk) | NRF_VPR_CSR_NORDIC_KEY_MASK;
522
523 reg |= ((enable ? VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_LowPriority :
524 VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_HighPriority)
525 << VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Pos) | NRF_VPR_CSR_NORDIC_KEY_MASK;
526
527 nrf_csr_write(VPRCSR_NORDIC_VPRNORDICCTRL, reg);
528 }
529
nrf_vpr_csr_ram_prio_enable_check(void)530 NRF_STATIC_INLINE bool nrf_vpr_csr_ram_prio_enable_check(void)
531 {
532 return (nrf_csr_read(VPRCSR_NORDIC_VPRNORDICCTRL) & VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Msk)
533 >> VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Pos;
534 }
535 #endif
536
nrf_vpr_csr_sleep_state_set(nrf_vpr_csr_sleep_state_t state)537 NRF_STATIC_INLINE void nrf_vpr_csr_sleep_state_set(nrf_vpr_csr_sleep_state_t state)
538 {
539 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_VPRNORDICSLEEPCTRL);
540 reg &= ~VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Msk;
541
542 reg |= (uint32_t)state << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos;
543 nrf_csr_write(VPRCSR_NORDIC_VPRNORDICSLEEPCTRL, reg);
544 }
545
nrf_vpr_csr_sleep_state_get(void)546 NRF_STATIC_INLINE nrf_vpr_csr_sleep_state_t nrf_vpr_csr_sleep_state_get(void)
547 {
548 return (nrf_vpr_csr_sleep_state_t)((nrf_csr_read(VPRCSR_NORDIC_VPRNORDICSLEEPCTRL)
549 & VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Msk)
550 >> VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos);
551 }
552
nrf_vpr_csr_return_to_sleep_set(bool enable)553 NRF_STATIC_INLINE void nrf_vpr_csr_return_to_sleep_set(bool enable)
554 {
555 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_VPRNORDICSLEEPCTRL);
556 reg &= ~VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Msk;
557
558 reg |= (enable ? VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Enabled :
559 VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Disabled)
560 << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos;
561 nrf_csr_write(VPRCSR_NORDIC_VPRNORDICSLEEPCTRL, reg);
562 }
563
nrf_vpr_csr_return_to_sleep_check(void)564 NRF_STATIC_INLINE bool nrf_vpr_csr_return_to_sleep_check(void)
565 {
566 return (nrf_csr_read(VPRCSR_NORDIC_VPRNORDICSLEEPCTRL)
567 & VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Msk)
568 >> VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos;
569 }
570
nrf_vpr_csr_stack_on_sleep_set(bool enable)571 NRF_STATIC_INLINE void nrf_vpr_csr_stack_on_sleep_set(bool enable)
572 {
573 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_VPRNORDICSLEEPCTRL);
574 reg &= ~VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Msk;
575
576 reg |= (enable ? VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Enabled :
577 VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Disabled)
578 << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos;
579 nrf_csr_write(VPRCSR_NORDIC_VPRNORDICSLEEPCTRL, reg);
580 }
581
nrf_vpr_csr_stack_on_sleep_check(void)582 NRF_STATIC_INLINE bool nrf_vpr_csr_stack_on_sleep_check(void)
583 {
584 return (nrf_csr_read(VPRCSR_NORDIC_VPRNORDICSLEEPCTRL)
585 & VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Msk)
586 >> VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos;
587 }
588
nrf_vpr_csr_clic_round_robin_set(bool enable)589 NRF_STATIC_INLINE void nrf_vpr_csr_clic_round_robin_set(bool enable)
590 {
591 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE);
592 reg = (reg & ~VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Msk) |
593 NRF_VPR_CSR_NORDIC_KEY_MASK;
594
595 reg |= (enable ? VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Enabled :
596 VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Disabled)
597 << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos;
598 nrf_csr_write(VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE, reg);
599 }
600
nrf_vpr_csr_clic_round_robin_check(void)601 NRF_STATIC_INLINE bool nrf_vpr_csr_clic_round_robin_check(void)
602 {
603 return ((nrf_csr_read(VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE)
604 & VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Msk)
605 >> VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos
606 == VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Enabled);
607 }
608
nrf_vpr_csr_unrecoverable_return_set(bool enable)609 NRF_STATIC_INLINE void nrf_vpr_csr_unrecoverable_return_set(bool enable)
610 {
611 uint32_t reg = nrf_csr_read(VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE);
612 reg = (reg & ~VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Msk) |
613 NRF_VPR_CSR_NORDIC_KEY_MASK;
614
615 reg |= (enable ? VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Enabled :
616 VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Disabled)
617 << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos;
618 nrf_csr_write(VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE, reg);
619 }
620
nrf_vpr_csr_unrecoverable_return_check(void)621 NRF_STATIC_INLINE bool nrf_vpr_csr_unrecoverable_return_check(void)
622 {
623 return ((nrf_csr_read(VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE)
624 & VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Msk)
625 >> VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos
626 == VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Enabled);
627 }
628
629 #endif // NRF_DECLARE_ONLY
630
631 /** @} */
632
633 #ifdef __cplusplus
634 }
635 #endif
636
637 #endif // NRF_VPR_CSR_H__
638
