1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #pragma once
16
17 #include <stdbool.h>
18 #include "soc/memprot_defs.h"
19 #include "hal/memprot_types.h"
20
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24
25 /**
26 * ========================================================================================
27 * === PeriBus1 common
28 * ========================================================================================
29 */
memprot_ll_peri1_clear_intr(void)30 static inline void memprot_ll_peri1_clear_intr(void)
31 {
32 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
33 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
34 }
35
memprot_ll_peri1_get_intr_source_num(void)36 static inline uint32_t memprot_ll_peri1_get_intr_source_num(void)
37 {
38 return ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE;
39 }
40
memprot_ll_peri1_intr_ena(bool enable)41 static inline void memprot_ll_peri1_intr_ena(bool enable)
42 {
43 if (enable) {
44 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN);
45 } else {
46 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN);
47 }
48 }
49
memprot_ll_peri1_get_ctrl_reg(void)50 static inline uint32_t memprot_ll_peri1_get_ctrl_reg(void)
51 {
52 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_6_REG);
53 }
54
memprot_ll_peri1_get_fault_reg(void)55 static inline uint32_t memprot_ll_peri1_get_fault_reg(void)
56 {
57 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_7_REG);
58 }
59
memprot_ll_peri1_get_fault_op_type(uint32_t * op_type,uint32_t * op_subtype)60 static inline void memprot_ll_peri1_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype)
61 {
62 uint32_t status_bits = memprot_ll_peri1_get_fault_reg();
63 //*op_type = (uint32_t)status_bits & PERI1_INTR_ST_OP_RW_BIT;
64 *op_type = 0;
65 //! DPORT_PMS_PRO_DPORT_7_REG is missing op_type bit
66 *op_subtype = (uint32_t)status_bits & PERI1_INTR_ST_OP_TYPE_BIT;
67 }
68
memprot_ll_peri1_is_assoc_intr(void)69 static inline bool memprot_ll_peri1_is_assoc_intr(void)
70 {
71 return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_7_REG, DPORT_PMS_PRO_DPORT_ILG_INTR) > 0;
72 }
73
memprot_ll_peri1_get_intr_ena_bit(void)74 static inline uint32_t memprot_ll_peri1_get_intr_ena_bit(void)
75 {
76 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN);
77 }
78
memprot_ll_peri1_get_intr_on_bit(void)79 static inline uint32_t memprot_ll_peri1_get_intr_on_bit(void)
80 {
81 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_INTR);
82 }
83
memprot_ll_peri1_get_intr_clr_bit(void)84 static inline uint32_t memprot_ll_peri1_get_intr_clr_bit(void)
85 {
86 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR);
87 }
88
memprot_ll_peri1_get_lock_reg(void)89 static inline uint32_t memprot_ll_peri1_get_lock_reg(void)
90 {
91 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_0_REG);
92 }
93
94 //resets automatically on CPU restart
memprot_ll_peri1_set_lock(void)95 static inline void memprot_ll_peri1_set_lock(void)
96 {
97 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DPORT_0_REG, DPORT_PMS_PRO_DPORT_LOCK);
98 }
99
memprot_ll_peri1_get_lock_bit(void)100 static inline uint32_t memprot_ll_peri1_get_lock_bit(void)
101 {
102 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_0_REG, DPORT_PMS_PRO_DPORT_LOCK);
103 }
104
105 /**
106 * ========================================================================================
107 * === PeriBus1 RTC SLOW
108 * ========================================================================================
109 */
memprot_ll_peri1_rtcslow_get_fault_address(void)110 static inline intptr_t memprot_ll_peri1_rtcslow_get_fault_address(void)
111 {
112 uint32_t status_bits = memprot_ll_peri1_get_fault_reg();
113 uint32_t fault_address = (status_bits & PERI1_INTR_ST_FAULTADDR_M) >> PERI1_INTR_ST_FAULTADDR_S;
114 uint32_t high_bits = (status_bits & PERI1_INTR_ST_OP_HIGH_BITS) ? PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 : 0;
115 return (intptr_t)(fault_address | high_bits);
116 }
117
memprot_ll_peri1_rtcslow_is_intr_mine(void)118 static inline bool memprot_ll_peri1_rtcslow_is_intr_mine(void)
119 {
120 if (memprot_ll_dram0_is_assoc_intr()) {
121 uint32_t faulting_address = (uint32_t)memprot_ll_peri1_rtcslow_get_fault_address();
122 return faulting_address >= PERI1_RTCSLOW_ADDRESS_LOW && faulting_address <= PERI1_RTCSLOW_ADDRESS_HIGH;
123 }
124 return false;
125 }
126
memprot_ll_peri1_rtcslow_set_prot(uint32_t * split_addr,bool lw,bool lr,bool hw,bool hr)127 static inline memprot_ll_err_t memprot_ll_peri1_rtcslow_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
128 {
129 uint32_t addr = (uint32_t)split_addr;
130
131 //check corresponding range fit & aligment to 32bit boundaries
132 if (addr < PERI1_RTCSLOW_ADDRESS_LOW || addr > PERI1_RTCSLOW_ADDRESS_HIGH) {
133 return MEMP_LL_ERR_SPLIT_ADDR_INVALID;
134 }
135 if (addr % 0x4 != 0) {
136 return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED;
137 }
138
139 uint32_t reg_split_addr = PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr);
140
141 //prepare high & low permission mask
142 uint32_t permission_mask = 0;
143 if (lw) {
144 permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_L_W;
145 }
146 if (lr) {
147 permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_L_R;
148 }
149 if (hw) {
150 permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_H_W;
151 }
152 if (hr) {
153 permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_H_R;
154 }
155
156 //write PERIBUS1 RTC SLOW cfg register
157 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG, reg_split_addr | permission_mask);
158
159 return MEMP_LL_OK;
160 }
161
memprot_ll_peri1_rtcslow_get_split_sgnf_bits(bool * lw,bool * lr,bool * hw,bool * hr)162 static inline void memprot_ll_peri1_rtcslow_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr)
163 {
164 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W);
165 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_R);
166 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_W);
167 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R);
168 }
169
memprot_ll_peri1_rtcslow_set_read_perm(bool lr,bool hr)170 static inline void memprot_ll_peri1_rtcslow_set_read_perm(bool lr, bool hr)
171 {
172 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_R, lr ? 1 : 0);
173 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R, hr ? 1 : 0);
174 }
175
memprot_ll_peri1_rtcslow_set_write_perm(bool lw,bool hw)176 static inline void memprot_ll_peri1_rtcslow_set_write_perm(bool lw, bool hw)
177 {
178 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W, lw ? 1 : 0);
179 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_W, hw ? 1 : 0);
180 }
181
memprot_ll_peri1_rtcslow_get_conf_reg(void)182 static inline uint32_t memprot_ll_peri1_rtcslow_get_conf_reg(void)
183 {
184 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG);
185 }
186
187 /**
188 * ========================================================================================
189 * === PeriBus2 common
190 * ========================================================================================
191 */
memprot_ll_peri2_clear_intr(void)192 static inline void memprot_ll_peri2_clear_intr(void)
193 {
194 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
195 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
196 }
197
memprot_ll_peri2_get_intr_source_num(void)198 static inline uint32_t memprot_ll_peri2_get_intr_source_num(void)
199 {
200 return ETS_PMS_PRO_AHB_ILG_INTR_SOURCE;
201 }
202
memprot_ll_peri2_intr_ena(bool enable)203 static inline void memprot_ll_peri2_intr_ena(bool enable)
204 {
205 if (enable) {
206 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN);
207 } else {
208 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN);
209 }
210 }
211
memprot_ll_peri2_get_ctrl_reg(void)212 static inline uint32_t memprot_ll_peri2_get_ctrl_reg(void)
213 {
214 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_3_REG);
215 }
216
memprot_ll_peri2_get_fault_reg(void)217 static inline uint32_t memprot_ll_peri2_get_fault_reg(void)
218 {
219 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_4_REG);
220 }
221
memprot_ll_peri2_get_fault_op_type(uint32_t * op_type,uint32_t * op_subtype)222 static inline void memprot_ll_peri2_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype)
223 {
224 uint32_t status_bits = memprot_ll_peri2_get_fault_reg();
225 *op_type = (uint32_t)status_bits & PERI2_INTR_ST_OP_RW_BIT;
226 *op_subtype = (uint32_t)status_bits & PERI2_INTR_ST_OP_TYPE_BIT;
227 }
228
memprot_ll_peri2_is_assoc_intr(void)229 static inline bool memprot_ll_peri2_is_assoc_intr(void)
230 {
231 return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_INTR) > 0;
232 }
233
memprot_ll_peri2_get_intr_ena_bit(void)234 static inline uint32_t memprot_ll_peri2_get_intr_ena_bit(void)
235 {
236 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN);
237 }
238
memprot_ll_peri2_get_intr_on_bit(void)239 static inline uint32_t memprot_ll_peri2_get_intr_on_bit(void)
240 {
241 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_INTR);
242 }
243
memprot_ll_peri2_get_intr_clr_bit(void)244 static inline uint32_t memprot_ll_peri2_get_intr_clr_bit(void)
245 {
246 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR);
247 }
248
memprot_ll_peri2_get_lock_reg(void)249 static inline uint32_t memprot_ll_peri2_get_lock_reg(void)
250 {
251 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_0_REG);
252 }
253
254 //resets automatically on CPU restart
memprot_ll_peri2_set_lock(void)255 static inline void memprot_ll_peri2_set_lock(void)
256 {
257 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_0_REG, DPORT_PMS_PRO_AHB_LOCK);
258 }
259
memprot_ll_peri2_get_lock_bit(void)260 static inline uint32_t memprot_ll_peri2_get_lock_bit(void)
261 {
262 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_0_REG, DPORT_PMS_PRO_AHB_LOCK);
263 }
264
memprot_ll_peri2_rtcslow_get_fault_address(void)265 static inline intptr_t memprot_ll_peri2_rtcslow_get_fault_address(void)
266 {
267 uint32_t status_bits = memprot_ll_peri2_get_fault_reg();
268 return (intptr_t)(status_bits & PERI2_INTR_ST_FAULTADDR_M);
269 }
270
271 /**
272 * ========================================================================================
273 * === PeriBus2 RTC SLOW 0 (AHB0)
274 * ========================================================================================
275 */
memprot_ll_peri2_rtcslow_0_is_intr_mine(void)276 static inline bool memprot_ll_peri2_rtcslow_0_is_intr_mine(void)
277 {
278 if (memprot_ll_peri2_is_assoc_intr()) {
279 uint32_t faulting_address = (uint32_t)memprot_ll_peri2_rtcslow_get_fault_address();
280 return faulting_address >= PERI2_RTCSLOW_0_ADDRESS_LOW && faulting_address <= PERI2_RTCSLOW_0_ADDRESS_HIGH;
281 }
282 return false;
283 }
284
memprot_ll_peri2_rtcslow_0_set_prot(uint32_t * split_addr,bool lw,bool lr,bool lx,bool hw,bool hr,bool hx)285 static inline memprot_ll_err_t memprot_ll_peri2_rtcslow_0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
286 {
287 uint32_t addr = (uint32_t)split_addr;
288
289 //check corresponding range fit & aligment to 32bit boundaries
290 if (addr < PERI2_RTCSLOW_0_ADDRESS_LOW || addr > PERI2_RTCSLOW_0_ADDRESS_HIGH) {
291 return MEMP_LL_ERR_SPLIT_ADDR_INVALID;
292 }
293 if (addr % 0x4 != 0) {
294 return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED;
295 }
296
297 uint32_t reg_split_addr = PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr);
298
299 //prepare high & low permission mask
300 uint32_t permission_mask = 0;
301 if (lw) {
302 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W;
303 }
304 if (lr) {
305 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R;
306 }
307 if (lx) {
308 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F;
309 }
310 if (hw) {
311 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W;
312 }
313 if (hr) {
314 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R;
315 }
316 if (hx) {
317 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F;
318 }
319
320 //write PERIBUS1 RTC SLOW cfg register
321 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_1_REG, reg_split_addr | permission_mask);
322
323 return MEMP_LL_OK;
324 }
325
memprot_ll_peri2_rtcslow_0_get_split_sgnf_bits(bool * lw,bool * lr,bool * lx,bool * hw,bool * hr,bool * hx)326 static inline void memprot_ll_peri2_rtcslow_0_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx)
327 {
328 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W);
329 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R);
330 *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F);
331 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W);
332 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R);
333 *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F);
334 }
335
memprot_ll_peri2_rtcslow_0_set_read_perm(bool lr,bool hr)336 static inline void memprot_ll_peri2_rtcslow_0_set_read_perm(bool lr, bool hr)
337 {
338 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R, lr ? 1 : 0);
339 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R, hr ? 1 : 0);
340 }
341
memprot_ll_peri2_rtcslow_0_set_write_perm(bool lw,bool hw)342 static inline void memprot_ll_peri2_rtcslow_0_set_write_perm(bool lw, bool hw)
343 {
344 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W, lw ? 1 : 0);
345 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W, hw ? 1 : 0);
346 }
347
memprot_ll_peri2_rtcslow_0_set_exec_perm(bool lx,bool hx)348 static inline void memprot_ll_peri2_rtcslow_0_set_exec_perm(bool lx, bool hx)
349 {
350 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F, lx ? 1 : 0);
351 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F, hx ? 1 : 0);
352 }
353
memprot_ll_peri2_rtcslow_0_get_conf_reg(void)354 static inline uint32_t memprot_ll_peri2_rtcslow_0_get_conf_reg(void)
355 {
356 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG);
357 }
358
359 /**
360 * ========================================================================================
361 * === PeriBus2 RTC SLOW 1 (AHB1)
362 * ========================================================================================
363 */
memprot_ll_peri2_rtcslow_1_is_intr_mine(void)364 static inline bool memprot_ll_peri2_rtcslow_1_is_intr_mine(void)
365 {
366 if (memprot_ll_peri2_is_assoc_intr()) {
367 uint32_t faulting_address = (uint32_t)memprot_ll_peri2_rtcslow_get_fault_address();
368 return faulting_address >= PERI2_RTCSLOW_1_ADDRESS_LOW && faulting_address <= PERI2_RTCSLOW_1_ADDRESS_HIGH;
369 }
370 return false;
371 }
372
memprot_ll_peri2_rtcslow_1_set_prot(uint32_t * split_addr,bool lw,bool lr,bool lx,bool hw,bool hr,bool hx)373 static inline memprot_ll_err_t memprot_ll_peri2_rtcslow_1_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
374 {
375 uint32_t addr = (uint32_t)split_addr;
376
377 //check corresponding range fit & aligment to 32bit boundaries
378 if (addr < PERI2_RTCSLOW_1_ADDRESS_LOW || addr > PERI2_RTCSLOW_1_ADDRESS_HIGH) {
379 return MEMP_LL_ERR_SPLIT_ADDR_INVALID;
380 }
381 if (addr % 0x4 != 0) {
382 return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED;
383 }
384
385 uint32_t reg_split_addr = PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr);
386
387 //prepare high & low permission mask
388 uint32_t permission_mask = 0;
389 if (lw) {
390 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W;
391 }
392 if (lr) {
393 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R;
394 }
395 if (lx) {
396 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F;
397 }
398 if (hw) {
399 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W;
400 }
401 if (hr) {
402 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R;
403 }
404 if (hx) {
405 permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F;
406 }
407
408 //write PERIBUS1 RTC SLOW cfg register
409 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_2_REG, reg_split_addr | permission_mask);
410
411 return MEMP_LL_OK;
412 }
413
memprot_ll_peri2_rtcslow_1_get_split_sgnf_bits(bool * lw,bool * lr,bool * lx,bool * hw,bool * hr,bool * hx)414 static inline void memprot_ll_peri2_rtcslow_1_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx)
415 {
416 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W);
417 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R);
418 *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F);
419 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W);
420 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R);
421 *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F);
422 }
423
memprot_ll_peri2_rtcslow_1_set_read_perm(bool lr,bool hr)424 static inline void memprot_ll_peri2_rtcslow_1_set_read_perm(bool lr, bool hr)
425 {
426 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R, lr ? 1 : 0);
427 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R, hr ? 1 : 0);
428 }
429
memprot_ll_peri2_rtcslow_1_set_write_perm(bool lw,bool hw)430 static inline void memprot_ll_peri2_rtcslow_1_set_write_perm(bool lw, bool hw)
431 {
432 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W, lw ? 1 : 0);
433 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W, hw ? 1 : 0);
434 }
435
memprot_ll_peri2_rtcslow_1_set_exec_perm(bool lx,bool hx)436 static inline void memprot_ll_peri2_rtcslow_1_set_exec_perm(bool lx, bool hx)
437 {
438 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F, lx ? 1 : 0);
439 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F, hx ? 1 : 0);
440 }
441
memprot_ll_peri2_rtcslow_1_get_conf_reg(void)442 static inline uint32_t memprot_ll_peri2_rtcslow_1_get_conf_reg(void)
443 {
444 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_2_REG);
445 }
446
447 #ifdef __cplusplus
448 }
449 #endif
450
