1 /***************************************************************************//** 2 * \file gpio_xmc7200_272_bga.h 3 * 4 * \brief 5 * XMC7200 device GPIO header for 272-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_XMC7200_272_BGA_H_ 28 #define _GPIO_XMC7200_272_BGA_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA 44 #define CY_GPIO_PIN_COUNT 272u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_EFUSE, 50 AMUXBUS_MAIN, 51 AMUXBUS_REGHC_ISENSE, 52 AMUXBUS_TEST, 53 AMUXBUS_TESTECT, 54 AMUXBUS_TESTSRSS, 55 }; 56 57 /* AMUX Splitter Controls */ 58 typedef enum 59 { 60 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 61 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 62 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_EFUSE */ 63 AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_REGHC_ISENSE */ 64 } cy_en_amux_split_t; 65 66 /* Port List */ 67 /* PORT 0 (AUTOLVL) */ 68 #define P0_0_PORT GPIO_PRT0 69 #define P0_0_PIN 0u 70 #define P0_0_NUM 0u 71 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 72 #define P0_1_PORT GPIO_PRT0 73 #define P0_1_PIN 1u 74 #define P0_1_NUM 1u 75 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 76 #define P0_2_PORT GPIO_PRT0 77 #define P0_2_PIN 2u 78 #define P0_2_NUM 2u 79 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 80 #define P0_3_PORT GPIO_PRT0 81 #define P0_3_PIN 3u 82 #define P0_3_NUM 3u 83 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 84 85 /* PORT 1 (AUTOLVL) */ 86 #define P1_0_PORT GPIO_PRT1 87 #define P1_0_PIN 0u 88 #define P1_0_NUM 0u 89 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 90 #define P1_1_PORT GPIO_PRT1 91 #define P1_1_PIN 1u 92 #define P1_1_NUM 1u 93 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 94 #define P1_2_PORT GPIO_PRT1 95 #define P1_2_PIN 2u 96 #define P1_2_NUM 2u 97 #define P1_2_AMUXSEGMENT AMUXBUS_MAIN 98 #define P1_3_PORT GPIO_PRT1 99 #define P1_3_PIN 3u 100 #define P1_3_NUM 3u 101 #define P1_3_AMUXSEGMENT AMUXBUS_MAIN 102 #define P1_4_PORT GPIO_PRT1 103 #define P1_4_PIN 4u 104 #define P1_4_NUM 4u 105 #define P1_4_AMUXSEGMENT AMUXBUS_MAIN 106 107 /* PORT 2 (AUTOLVL) */ 108 #define P2_0_PORT GPIO_PRT2 109 #define P2_0_PIN 0u 110 #define P2_0_NUM 0u 111 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 112 #define P2_1_PORT GPIO_PRT2 113 #define P2_1_PIN 1u 114 #define P2_1_NUM 1u 115 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 116 #define P2_2_PORT GPIO_PRT2 117 #define P2_2_PIN 2u 118 #define P2_2_NUM 2u 119 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 120 #define P2_3_PORT GPIO_PRT2 121 #define P2_3_PIN 3u 122 #define P2_3_NUM 3u 123 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 124 #define P2_4_PORT GPIO_PRT2 125 #define P2_4_PIN 4u 126 #define P2_4_NUM 4u 127 #define P2_4_AMUXSEGMENT AMUXBUS_MAIN 128 #define P2_5_PORT GPIO_PRT2 129 #define P2_5_PIN 5u 130 #define P2_5_NUM 5u 131 #define P2_5_AMUXSEGMENT AMUXBUS_MAIN 132 #define P2_6_PORT GPIO_PRT2 133 #define P2_6_PIN 6u 134 #define P2_6_NUM 6u 135 #define P2_6_AMUXSEGMENT AMUXBUS_MAIN 136 #define P2_7_PORT GPIO_PRT2 137 #define P2_7_PIN 7u 138 #define P2_7_NUM 7u 139 #define P2_7_AMUXSEGMENT AMUXBUS_MAIN 140 141 /* PORT 3 (AUTOLVL) */ 142 #define P3_0_PORT GPIO_PRT3 143 #define P3_0_PIN 0u 144 #define P3_0_NUM 0u 145 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 146 #define P3_1_PORT GPIO_PRT3 147 #define P3_1_PIN 1u 148 #define P3_1_NUM 1u 149 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 150 #define P3_2_PORT GPIO_PRT3 151 #define P3_2_PIN 2u 152 #define P3_2_NUM 2u 153 #define P3_2_AMUXSEGMENT AMUXBUS_MAIN 154 #define P3_3_PORT GPIO_PRT3 155 #define P3_3_PIN 3u 156 #define P3_3_NUM 3u 157 #define P3_3_AMUXSEGMENT AMUXBUS_MAIN 158 #define P3_4_PORT GPIO_PRT3 159 #define P3_4_PIN 4u 160 #define P3_4_NUM 4u 161 #define P3_4_AMUXSEGMENT AMUXBUS_MAIN 162 #define P3_5_PORT GPIO_PRT3 163 #define P3_5_PIN 5u 164 #define P3_5_NUM 5u 165 #define P3_5_AMUXSEGMENT AMUXBUS_MAIN 166 #define P3_6_PORT GPIO_PRT3 167 #define P3_6_PIN 6u 168 #define P3_6_NUM 6u 169 #define P3_6_AMUXSEGMENT AMUXBUS_MAIN 170 #define P3_7_PORT GPIO_PRT3 171 #define P3_7_PIN 7u 172 #define P3_7_NUM 7u 173 #define P3_7_AMUXSEGMENT AMUXBUS_MAIN 174 175 /* PORT 4 (AUTOLVL) */ 176 #define P4_0_PORT GPIO_PRT4 177 #define P4_0_PIN 0u 178 #define P4_0_NUM 0u 179 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 180 #define P4_1_PORT GPIO_PRT4 181 #define P4_1_PIN 1u 182 #define P4_1_NUM 1u 183 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 184 #define P4_2_PORT GPIO_PRT4 185 #define P4_2_PIN 2u 186 #define P4_2_NUM 2u 187 #define P4_2_AMUXSEGMENT AMUXBUS_MAIN 188 #define P4_3_PORT GPIO_PRT4 189 #define P4_3_PIN 3u 190 #define P4_3_NUM 3u 191 #define P4_3_AMUXSEGMENT AMUXBUS_MAIN 192 #define P4_4_PORT GPIO_PRT4 193 #define P4_4_PIN 4u 194 #define P4_4_NUM 4u 195 #define P4_4_AMUXSEGMENT AMUXBUS_MAIN 196 197 /* PORT 5 (AUTOLVL) */ 198 #define P5_0_PORT GPIO_PRT5 199 #define P5_0_PIN 0u 200 #define P5_0_NUM 0u 201 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 202 #define P5_1_PORT GPIO_PRT5 203 #define P5_1_PIN 1u 204 #define P5_1_NUM 1u 205 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 206 #define P5_2_PORT GPIO_PRT5 207 #define P5_2_PIN 2u 208 #define P5_2_NUM 2u 209 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 210 #define P5_3_PORT GPIO_PRT5 211 #define P5_3_PIN 3u 212 #define P5_3_NUM 3u 213 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 214 #define P5_4_PORT GPIO_PRT5 215 #define P5_4_PIN 4u 216 #define P5_4_NUM 4u 217 #define P5_4_AMUXSEGMENT AMUXBUS_MAIN 218 #define P5_5_PORT GPIO_PRT5 219 #define P5_5_PIN 5u 220 #define P5_5_NUM 5u 221 #define P5_5_AMUXSEGMENT AMUXBUS_MAIN 222 223 /* PORT 6 (AUTOLVL) */ 224 #define P6_0_PORT GPIO_PRT6 225 #define P6_0_PIN 0u 226 #define P6_0_NUM 0u 227 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 228 #define P6_1_PORT GPIO_PRT6 229 #define P6_1_PIN 1u 230 #define P6_1_NUM 1u 231 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 232 #define P6_2_PORT GPIO_PRT6 233 #define P6_2_PIN 2u 234 #define P6_2_NUM 2u 235 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 236 #define P6_3_PORT GPIO_PRT6 237 #define P6_3_PIN 3u 238 #define P6_3_NUM 3u 239 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 240 #define P6_4_PORT GPIO_PRT6 241 #define P6_4_PIN 4u 242 #define P6_4_NUM 4u 243 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 244 #define P6_5_PORT GPIO_PRT6 245 #define P6_5_PIN 5u 246 #define P6_5_NUM 5u 247 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 248 #define P6_6_PORT GPIO_PRT6 249 #define P6_6_PIN 6u 250 #define P6_6_NUM 6u 251 #define P6_6_AMUXSEGMENT AMUXBUS_MAIN 252 #define P6_7_PORT GPIO_PRT6 253 #define P6_7_PIN 7u 254 #define P6_7_NUM 7u 255 #define P6_7_AMUXSEGMENT AMUXBUS_MAIN 256 257 /* PORT 7 (AUTOLVL) */ 258 #define P7_0_PORT GPIO_PRT7 259 #define P7_0_PIN 0u 260 #define P7_0_NUM 0u 261 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 262 #define P7_1_PORT GPIO_PRT7 263 #define P7_1_PIN 1u 264 #define P7_1_NUM 1u 265 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 266 #define P7_2_PORT GPIO_PRT7 267 #define P7_2_PIN 2u 268 #define P7_2_NUM 2u 269 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 270 #define P7_3_PORT GPIO_PRT7 271 #define P7_3_PIN 3u 272 #define P7_3_NUM 3u 273 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 274 #define P7_4_PORT GPIO_PRT7 275 #define P7_4_PIN 4u 276 #define P7_4_NUM 4u 277 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 278 #define P7_5_PORT GPIO_PRT7 279 #define P7_5_PIN 5u 280 #define P7_5_NUM 5u 281 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 282 #define P7_6_PORT GPIO_PRT7 283 #define P7_6_PIN 6u 284 #define P7_6_NUM 6u 285 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 286 #define P7_7_PORT GPIO_PRT7 287 #define P7_7_PIN 7u 288 #define P7_7_NUM 7u 289 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 290 291 /* PORT 8 (AUTOLVL) */ 292 #define P8_0_PORT GPIO_PRT8 293 #define P8_0_PIN 0u 294 #define P8_0_NUM 0u 295 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 296 #define P8_1_PORT GPIO_PRT8 297 #define P8_1_PIN 1u 298 #define P8_1_NUM 1u 299 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 300 #define P8_2_PORT GPIO_PRT8 301 #define P8_2_PIN 2u 302 #define P8_2_NUM 2u 303 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 304 #define P8_3_PORT GPIO_PRT8 305 #define P8_3_PIN 3u 306 #define P8_3_NUM 3u 307 #define P8_3_AMUXSEGMENT AMUXBUS_MAIN 308 #define P8_4_PORT GPIO_PRT8 309 #define P8_4_PIN 4u 310 #define P8_4_NUM 4u 311 #define P8_4_AMUXSEGMENT AMUXBUS_MAIN 312 313 /* PORT 9 (AUTOLVL) */ 314 #define P9_0_PORT GPIO_PRT9 315 #define P9_0_PIN 0u 316 #define P9_0_NUM 0u 317 #define P9_0_AMUXSEGMENT AMUXBUS_MAIN 318 #define P9_1_PORT GPIO_PRT9 319 #define P9_1_PIN 1u 320 #define P9_1_NUM 1u 321 #define P9_1_AMUXSEGMENT AMUXBUS_MAIN 322 #define P9_2_PORT GPIO_PRT9 323 #define P9_2_PIN 2u 324 #define P9_2_NUM 2u 325 #define P9_2_AMUXSEGMENT AMUXBUS_MAIN 326 #define P9_3_PORT GPIO_PRT9 327 #define P9_3_PIN 3u 328 #define P9_3_NUM 3u 329 #define P9_3_AMUXSEGMENT AMUXBUS_MAIN 330 331 /* PORT 10 (AUTOLVL) */ 332 #define P10_0_PORT GPIO_PRT10 333 #define P10_0_PIN 0u 334 #define P10_0_NUM 0u 335 #define P10_0_AMUXSEGMENT AMUXBUS_MAIN 336 #define P10_1_PORT GPIO_PRT10 337 #define P10_1_PIN 1u 338 #define P10_1_NUM 1u 339 #define P10_1_AMUXSEGMENT AMUXBUS_MAIN 340 #define P10_2_PORT GPIO_PRT10 341 #define P10_2_PIN 2u 342 #define P10_2_NUM 2u 343 #define P10_2_AMUXSEGMENT AMUXBUS_MAIN 344 #define P10_3_PORT GPIO_PRT10 345 #define P10_3_PIN 3u 346 #define P10_3_NUM 3u 347 #define P10_3_AMUXSEGMENT AMUXBUS_MAIN 348 #define P10_4_PORT GPIO_PRT10 349 #define P10_4_PIN 4u 350 #define P10_4_NUM 4u 351 #define P10_4_AMUXSEGMENT AMUXBUS_MAIN 352 #define P10_5_PORT GPIO_PRT10 353 #define P10_5_PIN 5u 354 #define P10_5_NUM 5u 355 #define P10_5_AMUXSEGMENT AMUXBUS_MAIN 356 #define P10_6_PORT GPIO_PRT10 357 #define P10_6_PIN 6u 358 #define P10_6_NUM 6u 359 #define P10_6_AMUXSEGMENT AMUXBUS_MAIN 360 #define P10_7_PORT GPIO_PRT10 361 #define P10_7_PIN 7u 362 #define P10_7_NUM 7u 363 #define P10_7_AMUXSEGMENT AMUXBUS_MAIN 364 365 /* PORT 11 (AUTOLVL) */ 366 #define P11_0_PORT GPIO_PRT11 367 #define P11_0_PIN 0u 368 #define P11_0_NUM 0u 369 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 370 #define P11_1_PORT GPIO_PRT11 371 #define P11_1_PIN 1u 372 #define P11_1_NUM 1u 373 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 374 #define P11_2_PORT GPIO_PRT11 375 #define P11_2_PIN 2u 376 #define P11_2_NUM 2u 377 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 378 379 /* PORT 12 (AUTOLVL) */ 380 #define P12_0_PORT GPIO_PRT12 381 #define P12_0_PIN 0u 382 #define P12_0_NUM 0u 383 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 384 #define P12_1_PORT GPIO_PRT12 385 #define P12_1_PIN 1u 386 #define P12_1_NUM 1u 387 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 388 #define P12_2_PORT GPIO_PRT12 389 #define P12_2_PIN 2u 390 #define P12_2_NUM 2u 391 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 392 #define P12_3_PORT GPIO_PRT12 393 #define P12_3_PIN 3u 394 #define P12_3_NUM 3u 395 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 396 #define P12_4_PORT GPIO_PRT12 397 #define P12_4_PIN 4u 398 #define P12_4_NUM 4u 399 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 400 #define P12_5_PORT GPIO_PRT12 401 #define P12_5_PIN 5u 402 #define P12_5_NUM 5u 403 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 404 #define P12_6_PORT GPIO_PRT12 405 #define P12_6_PIN 6u 406 #define P12_6_NUM 6u 407 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 408 #define P12_7_PORT GPIO_PRT12 409 #define P12_7_PIN 7u 410 #define P12_7_NUM 7u 411 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 412 413 /* PORT 13 (AUTOLVL) */ 414 #define P13_0_PORT GPIO_PRT13 415 #define P13_0_PIN 0u 416 #define P13_0_NUM 0u 417 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 418 #define P13_1_PORT GPIO_PRT13 419 #define P13_1_PIN 1u 420 #define P13_1_NUM 1u 421 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 422 #define P13_2_PORT GPIO_PRT13 423 #define P13_2_PIN 2u 424 #define P13_2_NUM 2u 425 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 426 #define P13_3_PORT GPIO_PRT13 427 #define P13_3_PIN 3u 428 #define P13_3_NUM 3u 429 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 430 #define P13_4_PORT GPIO_PRT13 431 #define P13_4_PIN 4u 432 #define P13_4_NUM 4u 433 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 434 #define P13_5_PORT GPIO_PRT13 435 #define P13_5_PIN 5u 436 #define P13_5_NUM 5u 437 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 438 #define P13_6_PORT GPIO_PRT13 439 #define P13_6_PIN 6u 440 #define P13_6_NUM 6u 441 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 442 #define P13_7_PORT GPIO_PRT13 443 #define P13_7_PIN 7u 444 #define P13_7_NUM 7u 445 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 446 447 /* PORT 14 (AUTOLVL) */ 448 #define P14_0_PORT GPIO_PRT14 449 #define P14_0_PIN 0u 450 #define P14_0_NUM 0u 451 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 452 #define P14_1_PORT GPIO_PRT14 453 #define P14_1_PIN 1u 454 #define P14_1_NUM 1u 455 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 456 #define P14_2_PORT GPIO_PRT14 457 #define P14_2_PIN 2u 458 #define P14_2_NUM 2u 459 #define P14_2_AMUXSEGMENT AMUXBUS_MAIN 460 #define P14_3_PORT GPIO_PRT14 461 #define P14_3_PIN 3u 462 #define P14_3_NUM 3u 463 #define P14_3_AMUXSEGMENT AMUXBUS_MAIN 464 #define P14_4_PORT GPIO_PRT14 465 #define P14_4_PIN 4u 466 #define P14_4_NUM 4u 467 #define P14_4_AMUXSEGMENT AMUXBUS_MAIN 468 #define P14_5_PORT GPIO_PRT14 469 #define P14_5_PIN 5u 470 #define P14_5_NUM 5u 471 #define P14_5_AMUXSEGMENT AMUXBUS_MAIN 472 #define P14_6_PORT GPIO_PRT14 473 #define P14_6_PIN 6u 474 #define P14_6_NUM 6u 475 #define P14_6_AMUXSEGMENT AMUXBUS_MAIN 476 #define P14_7_PORT GPIO_PRT14 477 #define P14_7_PIN 7u 478 #define P14_7_NUM 7u 479 #define P14_7_AMUXSEGMENT AMUXBUS_MAIN 480 481 /* PORT 15 (AUTOLVL) */ 482 #define P15_0_PORT GPIO_PRT15 483 #define P15_0_PIN 0u 484 #define P15_0_NUM 0u 485 #define P15_0_AMUXSEGMENT AMUXBUS_MAIN 486 #define P15_1_PORT GPIO_PRT15 487 #define P15_1_PIN 1u 488 #define P15_1_NUM 1u 489 #define P15_1_AMUXSEGMENT AMUXBUS_MAIN 490 #define P15_2_PORT GPIO_PRT15 491 #define P15_2_PIN 2u 492 #define P15_2_NUM 2u 493 #define P15_2_AMUXSEGMENT AMUXBUS_MAIN 494 #define P15_3_PORT GPIO_PRT15 495 #define P15_3_PIN 3u 496 #define P15_3_NUM 3u 497 #define P15_3_AMUXSEGMENT AMUXBUS_MAIN 498 499 /* PORT 16 (AUTOLVL) */ 500 #define P16_0_PORT GPIO_PRT16 501 #define P16_0_PIN 0u 502 #define P16_0_NUM 0u 503 #define P16_0_AMUXSEGMENT AMUXBUS_MAIN 504 #define P16_1_PORT GPIO_PRT16 505 #define P16_1_PIN 1u 506 #define P16_1_NUM 1u 507 #define P16_1_AMUXSEGMENT AMUXBUS_MAIN 508 #define P16_2_PORT GPIO_PRT16 509 #define P16_2_PIN 2u 510 #define P16_2_NUM 2u 511 #define P16_2_AMUXSEGMENT AMUXBUS_MAIN 512 #define P16_3_PORT GPIO_PRT16 513 #define P16_3_PIN 3u 514 #define P16_3_NUM 3u 515 #define P16_3_AMUXSEGMENT AMUXBUS_MAIN 516 #define P16_4_PORT GPIO_PRT16 517 #define P16_4_PIN 4u 518 #define P16_4_NUM 4u 519 #define P16_4_AMUXSEGMENT AMUXBUS_MAIN 520 #define P16_5_PORT GPIO_PRT16 521 #define P16_5_PIN 5u 522 #define P16_5_NUM 5u 523 #define P16_5_AMUXSEGMENT AMUXBUS_MAIN 524 #define P16_6_PORT GPIO_PRT16 525 #define P16_6_PIN 6u 526 #define P16_6_NUM 6u 527 #define P16_6_AMUXSEGMENT AMUXBUS_MAIN 528 #define P16_7_PORT GPIO_PRT16 529 #define P16_7_PIN 7u 530 #define P16_7_NUM 7u 531 #define P16_7_AMUXSEGMENT AMUXBUS_MAIN 532 533 /* PORT 17 (AUTOLVL) */ 534 #define P17_0_PORT GPIO_PRT17 535 #define P17_0_PIN 0u 536 #define P17_0_NUM 0u 537 #define P17_0_AMUXSEGMENT AMUXBUS_MAIN 538 #define P17_1_PORT GPIO_PRT17 539 #define P17_1_PIN 1u 540 #define P17_1_NUM 1u 541 #define P17_1_AMUXSEGMENT AMUXBUS_MAIN 542 #define P17_2_PORT GPIO_PRT17 543 #define P17_2_PIN 2u 544 #define P17_2_NUM 2u 545 #define P17_2_AMUXSEGMENT AMUXBUS_MAIN 546 #define P17_3_PORT GPIO_PRT17 547 #define P17_3_PIN 3u 548 #define P17_3_NUM 3u 549 #define P17_3_AMUXSEGMENT AMUXBUS_MAIN 550 #define P17_4_PORT GPIO_PRT17 551 #define P17_4_PIN 4u 552 #define P17_4_NUM 4u 553 #define P17_4_AMUXSEGMENT AMUXBUS_MAIN 554 #define P17_5_PORT GPIO_PRT17 555 #define P17_5_PIN 5u 556 #define P17_5_NUM 5u 557 #define P17_5_AMUXSEGMENT AMUXBUS_MAIN 558 #define P17_6_PORT GPIO_PRT17 559 #define P17_6_PIN 6u 560 #define P17_6_NUM 6u 561 #define P17_6_AMUXSEGMENT AMUXBUS_MAIN 562 #define P17_7_PORT GPIO_PRT17 563 #define P17_7_PIN 7u 564 #define P17_7_NUM 7u 565 #define P17_7_AMUXSEGMENT AMUXBUS_MAIN 566 567 /* PORT 18 (AUTOLVL) */ 568 #define P18_0_PORT GPIO_PRT18 569 #define P18_0_PIN 0u 570 #define P18_0_NUM 0u 571 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 572 #define P18_1_PORT GPIO_PRT18 573 #define P18_1_PIN 1u 574 #define P18_1_NUM 1u 575 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 576 #define P18_2_PORT GPIO_PRT18 577 #define P18_2_PIN 2u 578 #define P18_2_NUM 2u 579 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 580 #define P18_3_PORT GPIO_PRT18 581 #define P18_3_PIN 3u 582 #define P18_3_NUM 3u 583 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 584 #define P18_4_PORT GPIO_PRT18 585 #define P18_4_PIN 4u 586 #define P18_4_NUM 4u 587 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 588 #define P18_5_PORT GPIO_PRT18 589 #define P18_5_PIN 5u 590 #define P18_5_NUM 5u 591 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 592 #define P18_6_PORT GPIO_PRT18 593 #define P18_6_PIN 6u 594 #define P18_6_NUM 6u 595 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 596 #define P18_7_PORT GPIO_PRT18 597 #define P18_7_PIN 7u 598 #define P18_7_NUM 7u 599 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 600 601 /* PORT 19 (AUTOLVL) */ 602 #define P19_0_PORT GPIO_PRT19 603 #define P19_0_PIN 0u 604 #define P19_0_NUM 0u 605 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 606 #define P19_1_PORT GPIO_PRT19 607 #define P19_1_PIN 1u 608 #define P19_1_NUM 1u 609 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 610 #define P19_2_PORT GPIO_PRT19 611 #define P19_2_PIN 2u 612 #define P19_2_NUM 2u 613 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 614 #define P19_3_PORT GPIO_PRT19 615 #define P19_3_PIN 3u 616 #define P19_3_NUM 3u 617 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 618 #define P19_4_PORT GPIO_PRT19 619 #define P19_4_PIN 4u 620 #define P19_4_NUM 4u 621 #define P19_4_AMUXSEGMENT AMUXBUS_MAIN 622 623 /* PORT 20 (AUTOLVL) */ 624 #define P20_0_PORT GPIO_PRT20 625 #define P20_0_PIN 0u 626 #define P20_0_NUM 0u 627 #define P20_0_AMUXSEGMENT AMUXBUS_MAIN 628 #define P20_1_PORT GPIO_PRT20 629 #define P20_1_PIN 1u 630 #define P20_1_NUM 1u 631 #define P20_1_AMUXSEGMENT AMUXBUS_MAIN 632 #define P20_2_PORT GPIO_PRT20 633 #define P20_2_PIN 2u 634 #define P20_2_NUM 2u 635 #define P20_2_AMUXSEGMENT AMUXBUS_MAIN 636 #define P20_3_PORT GPIO_PRT20 637 #define P20_3_PIN 3u 638 #define P20_3_NUM 3u 639 #define P20_3_AMUXSEGMENT AMUXBUS_MAIN 640 #define P20_4_PORT GPIO_PRT20 641 #define P20_4_PIN 4u 642 #define P20_4_NUM 4u 643 #define P20_4_AMUXSEGMENT AMUXBUS_MAIN 644 #define P20_5_PORT GPIO_PRT20 645 #define P20_5_PIN 5u 646 #define P20_5_NUM 5u 647 #define P20_5_AMUXSEGMENT AMUXBUS_MAIN 648 #define P20_6_PORT GPIO_PRT20 649 #define P20_6_PIN 6u 650 #define P20_6_NUM 6u 651 #define P20_6_AMUXSEGMENT AMUXBUS_MAIN 652 #define P20_7_PORT GPIO_PRT20 653 #define P20_7_PIN 7u 654 #define P20_7_NUM 7u 655 #define P20_7_AMUXSEGMENT AMUXBUS_MAIN 656 657 /* PORT 21 (AUTOLVL) */ 658 #define P21_0_PORT GPIO_PRT21 659 #define P21_0_PIN 0u 660 #define P21_0_NUM 0u 661 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 662 #define P21_1_PORT GPIO_PRT21 663 #define P21_1_PIN 1u 664 #define P21_1_NUM 1u 665 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 666 #define P21_2_PORT GPIO_PRT21 667 #define P21_2_PIN 2u 668 #define P21_2_NUM 2u 669 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 670 #define P21_3_PORT GPIO_PRT21 671 #define P21_3_PIN 3u 672 #define P21_3_NUM 3u 673 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 674 #define P21_4_PORT GPIO_PRT21 675 #define P21_4_PIN 4u 676 #define P21_4_NUM 4u 677 #define P21_4_AMUXSEGMENT AMUXBUS_MAIN 678 #define P21_5_PORT GPIO_PRT21 679 #define P21_5_PIN 5u 680 #define P21_5_NUM 5u 681 #define P21_5_AMUXSEGMENT AMUXBUS_MAIN 682 #define P21_6_PORT GPIO_PRT21 683 #define P21_6_PIN 6u 684 #define P21_6_NUM 6u 685 #define P21_6_AMUXSEGMENT AMUXBUS_MAIN 686 #define P21_7_PORT GPIO_PRT21 687 #define P21_7_PIN 7u 688 #define P21_7_NUM 7u 689 #define P21_7_AMUXSEGMENT AMUXBUS_MAIN 690 691 /* PORT 22 (AUTOLVL) */ 692 #define P22_1_PORT GPIO_PRT22 693 #define P22_1_PIN 1u 694 #define P22_1_NUM 1u 695 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 696 #define P22_2_PORT GPIO_PRT22 697 #define P22_2_PIN 2u 698 #define P22_2_NUM 2u 699 #define P22_2_AMUXSEGMENT AMUXBUS_MAIN 700 #define P22_3_PORT GPIO_PRT22 701 #define P22_3_PIN 3u 702 #define P22_3_NUM 3u 703 #define P22_3_AMUXSEGMENT AMUXBUS_MAIN 704 #define P22_4_PORT GPIO_PRT22 705 #define P22_4_PIN 4u 706 #define P22_4_NUM 4u 707 #define P22_4_AMUXSEGMENT AMUXBUS_MAIN 708 #define P22_5_PORT GPIO_PRT22 709 #define P22_5_PIN 5u 710 #define P22_5_NUM 5u 711 #define P22_5_AMUXSEGMENT AMUXBUS_MAIN 712 #define P22_6_PORT GPIO_PRT22 713 #define P22_6_PIN 6u 714 #define P22_6_NUM 6u 715 #define P22_6_AMUXSEGMENT AMUXBUS_MAIN 716 #define P22_7_PORT GPIO_PRT22 717 #define P22_7_PIN 7u 718 #define P22_7_NUM 7u 719 #define P22_7_AMUXSEGMENT AMUXBUS_MAIN 720 721 /* PORT 23 (AUTOLVL) */ 722 #define P23_0_PORT GPIO_PRT23 723 #define P23_0_PIN 0u 724 #define P23_0_NUM 0u 725 #define P23_0_AMUXSEGMENT AMUXBUS_MAIN 726 #define P23_1_PORT GPIO_PRT23 727 #define P23_1_PIN 1u 728 #define P23_1_NUM 1u 729 #define P23_1_AMUXSEGMENT AMUXBUS_MAIN 730 #define P23_2_PORT GPIO_PRT23 731 #define P23_2_PIN 2u 732 #define P23_2_NUM 2u 733 #define P23_2_AMUXSEGMENT AMUXBUS_MAIN 734 #define P23_3_PORT GPIO_PRT23 735 #define P23_3_PIN 3u 736 #define P23_3_NUM 3u 737 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 738 #define P23_4_PORT GPIO_PRT23 739 #define P23_4_PIN 4u 740 #define P23_4_NUM 4u 741 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 742 #define P23_5_PORT GPIO_PRT23 743 #define P23_5_PIN 5u 744 #define P23_5_NUM 5u 745 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 746 #define P23_6_PORT GPIO_PRT23 747 #define P23_6_PIN 6u 748 #define P23_6_NUM 6u 749 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 750 #define P23_7_PORT GPIO_PRT23 751 #define P23_7_PIN 7u 752 #define P23_7_NUM 7u 753 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 754 755 /* PORT 24 (HSIO, AUTOLVL) */ 756 #define P24_0_PORT GPIO_PRT24 757 #define P24_0_PIN 0u 758 #define P24_0_NUM 0u 759 #define P24_0_AMUXSEGMENT AMUXBUS_MAIN 760 #define P24_1_PORT GPIO_PRT24 761 #define P24_1_PIN 1u 762 #define P24_1_NUM 1u 763 #define P24_1_AMUXSEGMENT AMUXBUS_MAIN 764 #define P24_2_PORT GPIO_PRT24 765 #define P24_2_PIN 2u 766 #define P24_2_NUM 2u 767 #define P24_2_AMUXSEGMENT AMUXBUS_MAIN 768 #define P24_3_PORT GPIO_PRT24 769 #define P24_3_PIN 3u 770 #define P24_3_NUM 3u 771 #define P24_3_AMUXSEGMENT AMUXBUS_MAIN 772 #define P24_4_PORT GPIO_PRT24 773 #define P24_4_PIN 4u 774 #define P24_4_NUM 4u 775 #define P24_4_AMUXSEGMENT AMUXBUS_MAIN 776 777 /* PORT 25 (HSIO, AUTOLVL) */ 778 #define P25_0_PORT GPIO_PRT25 779 #define P25_0_PIN 0u 780 #define P25_0_NUM 0u 781 #define P25_0_AMUXSEGMENT AMUXBUS_MAIN 782 #define P25_1_PORT GPIO_PRT25 783 #define P25_1_PIN 1u 784 #define P25_1_NUM 1u 785 #define P25_1_AMUXSEGMENT AMUXBUS_MAIN 786 #define P25_2_PORT GPIO_PRT25 787 #define P25_2_PIN 2u 788 #define P25_2_NUM 2u 789 #define P25_2_AMUXSEGMENT AMUXBUS_MAIN 790 #define P25_3_PORT GPIO_PRT25 791 #define P25_3_PIN 3u 792 #define P25_3_NUM 3u 793 #define P25_3_AMUXSEGMENT AMUXBUS_MAIN 794 #define P25_4_PORT GPIO_PRT25 795 #define P25_4_PIN 4u 796 #define P25_4_NUM 4u 797 #define P25_4_AMUXSEGMENT AMUXBUS_MAIN 798 #define P25_5_PORT GPIO_PRT25 799 #define P25_5_PIN 5u 800 #define P25_5_NUM 5u 801 #define P25_5_AMUXSEGMENT AMUXBUS_MAIN 802 #define P25_6_PORT GPIO_PRT25 803 #define P25_6_PIN 6u 804 #define P25_6_NUM 6u 805 #define P25_6_AMUXSEGMENT AMUXBUS_MAIN 806 #define P25_7_PORT GPIO_PRT25 807 #define P25_7_PIN 7u 808 #define P25_7_NUM 7u 809 #define P25_7_AMUXSEGMENT AMUXBUS_MAIN 810 811 /* PORT 26 (HSIO, AUTOLVL) */ 812 #define P26_0_PORT GPIO_PRT26 813 #define P26_0_PIN 0u 814 #define P26_0_NUM 0u 815 #define P26_0_AMUXSEGMENT AMUXBUS_MAIN 816 #define P26_1_PORT GPIO_PRT26 817 #define P26_1_PIN 1u 818 #define P26_1_NUM 1u 819 #define P26_1_AMUXSEGMENT AMUXBUS_MAIN 820 #define P26_2_PORT GPIO_PRT26 821 #define P26_2_PIN 2u 822 #define P26_2_NUM 2u 823 #define P26_2_AMUXSEGMENT AMUXBUS_MAIN 824 #define P26_3_PORT GPIO_PRT26 825 #define P26_3_PIN 3u 826 #define P26_3_NUM 3u 827 #define P26_3_AMUXSEGMENT AMUXBUS_MAIN 828 #define P26_4_PORT GPIO_PRT26 829 #define P26_4_PIN 4u 830 #define P26_4_NUM 4u 831 #define P26_4_AMUXSEGMENT AMUXBUS_MAIN 832 #define P26_5_PORT GPIO_PRT26 833 #define P26_5_PIN 5u 834 #define P26_5_NUM 5u 835 #define P26_5_AMUXSEGMENT AMUXBUS_MAIN 836 #define P26_6_PORT GPIO_PRT26 837 #define P26_6_PIN 6u 838 #define P26_6_NUM 6u 839 #define P26_6_AMUXSEGMENT AMUXBUS_MAIN 840 #define P26_7_PORT GPIO_PRT26 841 #define P26_7_PIN 7u 842 #define P26_7_NUM 7u 843 #define P26_7_AMUXSEGMENT AMUXBUS_MAIN 844 845 /* PORT 27 (HSIO, AUTOLVL) */ 846 #define P27_0_PORT GPIO_PRT27 847 #define P27_0_PIN 0u 848 #define P27_0_NUM 0u 849 #define P27_0_AMUXSEGMENT AMUXBUS_MAIN 850 #define P27_1_PORT GPIO_PRT27 851 #define P27_1_PIN 1u 852 #define P27_1_NUM 1u 853 #define P27_1_AMUXSEGMENT AMUXBUS_MAIN 854 #define P27_2_PORT GPIO_PRT27 855 #define P27_2_PIN 2u 856 #define P27_2_NUM 2u 857 #define P27_2_AMUXSEGMENT AMUXBUS_MAIN 858 #define P27_3_PORT GPIO_PRT27 859 #define P27_3_PIN 3u 860 #define P27_3_NUM 3u 861 #define P27_3_AMUXSEGMENT AMUXBUS_MAIN 862 #define P27_4_PORT GPIO_PRT27 863 #define P27_4_PIN 4u 864 #define P27_4_NUM 4u 865 #define P27_4_AMUXSEGMENT AMUXBUS_MAIN 866 #define P27_5_PORT GPIO_PRT27 867 #define P27_5_PIN 5u 868 #define P27_5_NUM 5u 869 #define P27_5_AMUXSEGMENT AMUXBUS_MAIN 870 #define P27_6_PORT GPIO_PRT27 871 #define P27_6_PIN 6u 872 #define P27_6_NUM 6u 873 #define P27_6_AMUXSEGMENT AMUXBUS_MAIN 874 #define P27_7_PORT GPIO_PRT27 875 #define P27_7_PIN 7u 876 #define P27_7_NUM 7u 877 #define P27_7_AMUXSEGMENT AMUXBUS_MAIN 878 879 /* PORT 28 (AUTOLVL) */ 880 #define P28_0_PORT GPIO_PRT28 881 #define P28_0_PIN 0u 882 #define P28_0_NUM 0u 883 #define P28_0_AMUXSEGMENT AMUXBUS_MAIN 884 #define P28_1_PORT GPIO_PRT28 885 #define P28_1_PIN 1u 886 #define P28_1_NUM 1u 887 #define P28_1_AMUXSEGMENT AMUXBUS_MAIN 888 #define P28_2_PORT GPIO_PRT28 889 #define P28_2_PIN 2u 890 #define P28_2_NUM 2u 891 #define P28_2_AMUXSEGMENT AMUXBUS_MAIN 892 #define P28_3_PORT GPIO_PRT28 893 #define P28_3_PIN 3u 894 #define P28_3_NUM 3u 895 #define P28_3_AMUXSEGMENT AMUXBUS_MAIN 896 #define P28_4_PORT GPIO_PRT28 897 #define P28_4_PIN 4u 898 #define P28_4_NUM 4u 899 #define P28_4_AMUXSEGMENT AMUXBUS_MAIN 900 #define P28_5_PORT GPIO_PRT28 901 #define P28_5_PIN 5u 902 #define P28_5_NUM 5u 903 #define P28_5_AMUXSEGMENT AMUXBUS_MAIN 904 #define P28_6_PORT GPIO_PRT28 905 #define P28_6_PIN 6u 906 #define P28_6_NUM 6u 907 #define P28_6_AMUXSEGMENT AMUXBUS_MAIN 908 #define P28_7_PORT GPIO_PRT28 909 #define P28_7_PIN 7u 910 #define P28_7_NUM 7u 911 #define P28_7_AMUXSEGMENT AMUXBUS_MAIN 912 913 /* PORT 29 (AUTOLVL) */ 914 #define P29_0_PORT GPIO_PRT29 915 #define P29_0_PIN 0u 916 #define P29_0_NUM 0u 917 #define P29_0_AMUXSEGMENT AMUXBUS_MAIN 918 #define P29_1_PORT GPIO_PRT29 919 #define P29_1_PIN 1u 920 #define P29_1_NUM 1u 921 #define P29_1_AMUXSEGMENT AMUXBUS_MAIN 922 #define P29_2_PORT GPIO_PRT29 923 #define P29_2_PIN 2u 924 #define P29_2_NUM 2u 925 #define P29_2_AMUXSEGMENT AMUXBUS_MAIN 926 #define P29_3_PORT GPIO_PRT29 927 #define P29_3_PIN 3u 928 #define P29_3_NUM 3u 929 #define P29_3_AMUXSEGMENT AMUXBUS_MAIN 930 #define P29_4_PORT GPIO_PRT29 931 #define P29_4_PIN 4u 932 #define P29_4_NUM 4u 933 #define P29_4_AMUXSEGMENT AMUXBUS_MAIN 934 #define P29_5_PORT GPIO_PRT29 935 #define P29_5_PIN 5u 936 #define P29_5_NUM 5u 937 #define P29_5_AMUXSEGMENT AMUXBUS_MAIN 938 #define P29_6_PORT GPIO_PRT29 939 #define P29_6_PIN 6u 940 #define P29_6_NUM 6u 941 #define P29_6_AMUXSEGMENT AMUXBUS_MAIN 942 #define P29_7_PORT GPIO_PRT29 943 #define P29_7_PIN 7u 944 #define P29_7_NUM 7u 945 #define P29_7_AMUXSEGMENT AMUXBUS_MAIN 946 947 /* PORT 30 (AUTOLVL) */ 948 #define P30_0_PORT GPIO_PRT30 949 #define P30_0_PIN 0u 950 #define P30_0_NUM 0u 951 #define P30_0_AMUXSEGMENT AMUXBUS_MAIN 952 #define P30_1_PORT GPIO_PRT30 953 #define P30_1_PIN 1u 954 #define P30_1_NUM 1u 955 #define P30_1_AMUXSEGMENT AMUXBUS_MAIN 956 #define P30_2_PORT GPIO_PRT30 957 #define P30_2_PIN 2u 958 #define P30_2_NUM 2u 959 #define P30_2_AMUXSEGMENT AMUXBUS_MAIN 960 #define P30_3_PORT GPIO_PRT30 961 #define P30_3_PIN 3u 962 #define P30_3_NUM 3u 963 #define P30_3_AMUXSEGMENT AMUXBUS_MAIN 964 965 /* PORT 31 (AUTOLVL) */ 966 #define P31_0_PORT GPIO_PRT31 967 #define P31_0_PIN 0u 968 #define P31_0_NUM 0u 969 #define P31_0_AMUXSEGMENT AMUXBUS_MAIN 970 #define P31_1_PORT GPIO_PRT31 971 #define P31_1_PIN 1u 972 #define P31_1_NUM 1u 973 #define P31_1_AMUXSEGMENT AMUXBUS_MAIN 974 #define P31_2_PORT GPIO_PRT31 975 #define P31_2_PIN 2u 976 #define P31_2_NUM 2u 977 #define P31_2_AMUXSEGMENT AMUXBUS_MAIN 978 979 /* PORT 32 (AUTOLVL) */ 980 #define P32_0_PORT GPIO_PRT32 981 #define P32_0_PIN 0u 982 #define P32_0_NUM 0u 983 #define P32_0_AMUXSEGMENT AMUXBUS_MAIN 984 #define P32_1_PORT GPIO_PRT32 985 #define P32_1_PIN 1u 986 #define P32_1_NUM 1u 987 #define P32_1_AMUXSEGMENT AMUXBUS_MAIN 988 #define P32_2_PORT GPIO_PRT32 989 #define P32_2_PIN 2u 990 #define P32_2_NUM 2u 991 #define P32_2_AMUXSEGMENT AMUXBUS_MAIN 992 #define P32_3_PORT GPIO_PRT32 993 #define P32_3_PIN 3u 994 #define P32_3_NUM 3u 995 #define P32_3_AMUXSEGMENT AMUXBUS_MAIN 996 #define P32_4_PORT GPIO_PRT32 997 #define P32_4_PIN 4u 998 #define P32_4_NUM 4u 999 #define P32_4_AMUXSEGMENT AMUXBUS_MAIN 1000 #define P32_5_PORT GPIO_PRT32 1001 #define P32_5_PIN 5u 1002 #define P32_5_NUM 5u 1003 #define P32_5_AMUXSEGMENT AMUXBUS_MAIN 1004 #define P32_6_PORT GPIO_PRT32 1005 #define P32_6_PIN 6u 1006 #define P32_6_NUM 6u 1007 #define P32_6_AMUXSEGMENT AMUXBUS_MAIN 1008 #define P32_7_PORT GPIO_PRT32 1009 #define P32_7_PIN 7u 1010 #define P32_7_NUM 7u 1011 #define P32_7_AMUXSEGMENT AMUXBUS_MAIN 1012 1013 /* Analog Connections */ 1014 #define PASS0_I_TEMP_KELVIN_PORT 21u 1015 #define PASS0_I_TEMP_KELVIN_PIN 2u 1016 #define PASS0_SARMUX_MOTOR0_PORT 11u 1017 #define PASS0_SARMUX_MOTOR0_PIN 0u 1018 #define PASS0_SARMUX_MOTOR1_PORT 11u 1019 #define PASS0_SARMUX_MOTOR1_PIN 1u 1020 #define PASS0_SARMUX_MOTOR2_PORT 11u 1021 #define PASS0_SARMUX_MOTOR2_PIN 2u 1022 #define PASS0_SARMUX_PADS0_PORT 6u 1023 #define PASS0_SARMUX_PADS0_PIN 0u 1024 #define PASS0_SARMUX_PADS1_PORT 6u 1025 #define PASS0_SARMUX_PADS1_PIN 1u 1026 #define PASS0_SARMUX_PADS10_PORT 32u 1027 #define PASS0_SARMUX_PADS10_PIN 2u 1028 #define PASS0_SARMUX_PADS11_PORT 32u 1029 #define PASS0_SARMUX_PADS11_PIN 3u 1030 #define PASS0_SARMUX_PADS12_PORT 32u 1031 #define PASS0_SARMUX_PADS12_PIN 4u 1032 #define PASS0_SARMUX_PADS13_PORT 32u 1033 #define PASS0_SARMUX_PADS13_PIN 5u 1034 #define PASS0_SARMUX_PADS14_PORT 32u 1035 #define PASS0_SARMUX_PADS14_PIN 6u 1036 #define PASS0_SARMUX_PADS15_PORT 32u 1037 #define PASS0_SARMUX_PADS15_PIN 7u 1038 #define PASS0_SARMUX_PADS16_PORT 7u 1039 #define PASS0_SARMUX_PADS16_PIN 0u 1040 #define PASS0_SARMUX_PADS17_PORT 7u 1041 #define PASS0_SARMUX_PADS17_PIN 1u 1042 #define PASS0_SARMUX_PADS18_PORT 7u 1043 #define PASS0_SARMUX_PADS18_PIN 2u 1044 #define PASS0_SARMUX_PADS19_PORT 7u 1045 #define PASS0_SARMUX_PADS19_PIN 3u 1046 #define PASS0_SARMUX_PADS2_PORT 6u 1047 #define PASS0_SARMUX_PADS2_PIN 2u 1048 #define PASS0_SARMUX_PADS20_PORT 7u 1049 #define PASS0_SARMUX_PADS20_PIN 4u 1050 #define PASS0_SARMUX_PADS21_PORT 7u 1051 #define PASS0_SARMUX_PADS21_PIN 5u 1052 #define PASS0_SARMUX_PADS22_PORT 7u 1053 #define PASS0_SARMUX_PADS22_PIN 6u 1054 #define PASS0_SARMUX_PADS23_PORT 7u 1055 #define PASS0_SARMUX_PADS23_PIN 7u 1056 #define PASS0_SARMUX_PADS24_PORT 8u 1057 #define PASS0_SARMUX_PADS24_PIN 1u 1058 #define PASS0_SARMUX_PADS25_PORT 8u 1059 #define PASS0_SARMUX_PADS25_PIN 2u 1060 #define PASS0_SARMUX_PADS26_PORT 8u 1061 #define PASS0_SARMUX_PADS26_PIN 3u 1062 #define PASS0_SARMUX_PADS27_PORT 8u 1063 #define PASS0_SARMUX_PADS27_PIN 4u 1064 #define PASS0_SARMUX_PADS28_PORT 9u 1065 #define PASS0_SARMUX_PADS28_PIN 0u 1066 #define PASS0_SARMUX_PADS29_PORT 9u 1067 #define PASS0_SARMUX_PADS29_PIN 1u 1068 #define PASS0_SARMUX_PADS3_PORT 6u 1069 #define PASS0_SARMUX_PADS3_PIN 3u 1070 #define PASS0_SARMUX_PADS30_PORT 9u 1071 #define PASS0_SARMUX_PADS30_PIN 2u 1072 #define PASS0_SARMUX_PADS31_PORT 9u 1073 #define PASS0_SARMUX_PADS31_PIN 3u 1074 #define PASS0_SARMUX_PADS32_PORT 10u 1075 #define PASS0_SARMUX_PADS32_PIN 4u 1076 #define PASS0_SARMUX_PADS33_PORT 10u 1077 #define PASS0_SARMUX_PADS33_PIN 5u 1078 #define PASS0_SARMUX_PADS34_PORT 10u 1079 #define PASS0_SARMUX_PADS34_PIN 6u 1080 #define PASS0_SARMUX_PADS35_PORT 10u 1081 #define PASS0_SARMUX_PADS35_PIN 7u 1082 #define PASS0_SARMUX_PADS36_PORT 12u 1083 #define PASS0_SARMUX_PADS36_PIN 0u 1084 #define PASS0_SARMUX_PADS37_PORT 12u 1085 #define PASS0_SARMUX_PADS37_PIN 1u 1086 #define PASS0_SARMUX_PADS38_PORT 12u 1087 #define PASS0_SARMUX_PADS38_PIN 2u 1088 #define PASS0_SARMUX_PADS39_PORT 12u 1089 #define PASS0_SARMUX_PADS39_PIN 3u 1090 #define PASS0_SARMUX_PADS4_PORT 6u 1091 #define PASS0_SARMUX_PADS4_PIN 4u 1092 #define PASS0_SARMUX_PADS40_PORT 12u 1093 #define PASS0_SARMUX_PADS40_PIN 4u 1094 #define PASS0_SARMUX_PADS41_PORT 12u 1095 #define PASS0_SARMUX_PADS41_PIN 5u 1096 #define PASS0_SARMUX_PADS42_PORT 12u 1097 #define PASS0_SARMUX_PADS42_PIN 6u 1098 #define PASS0_SARMUX_PADS43_PORT 12u 1099 #define PASS0_SARMUX_PADS43_PIN 7u 1100 #define PASS0_SARMUX_PADS44_PORT 13u 1101 #define PASS0_SARMUX_PADS44_PIN 0u 1102 #define PASS0_SARMUX_PADS45_PORT 13u 1103 #define PASS0_SARMUX_PADS45_PIN 1u 1104 #define PASS0_SARMUX_PADS46_PORT 13u 1105 #define PASS0_SARMUX_PADS46_PIN 2u 1106 #define PASS0_SARMUX_PADS47_PORT 13u 1107 #define PASS0_SARMUX_PADS47_PIN 3u 1108 #define PASS0_SARMUX_PADS48_PORT 13u 1109 #define PASS0_SARMUX_PADS48_PIN 4u 1110 #define PASS0_SARMUX_PADS49_PORT 13u 1111 #define PASS0_SARMUX_PADS49_PIN 5u 1112 #define PASS0_SARMUX_PADS5_PORT 6u 1113 #define PASS0_SARMUX_PADS5_PIN 5u 1114 #define PASS0_SARMUX_PADS50_PORT 13u 1115 #define PASS0_SARMUX_PADS50_PIN 6u 1116 #define PASS0_SARMUX_PADS51_PORT 13u 1117 #define PASS0_SARMUX_PADS51_PIN 7u 1118 #define PASS0_SARMUX_PADS52_PORT 14u 1119 #define PASS0_SARMUX_PADS52_PIN 0u 1120 #define PASS0_SARMUX_PADS53_PORT 14u 1121 #define PASS0_SARMUX_PADS53_PIN 1u 1122 #define PASS0_SARMUX_PADS54_PORT 14u 1123 #define PASS0_SARMUX_PADS54_PIN 2u 1124 #define PASS0_SARMUX_PADS55_PORT 14u 1125 #define PASS0_SARMUX_PADS55_PIN 3u 1126 #define PASS0_SARMUX_PADS56_PORT 14u 1127 #define PASS0_SARMUX_PADS56_PIN 4u 1128 #define PASS0_SARMUX_PADS57_PORT 14u 1129 #define PASS0_SARMUX_PADS57_PIN 5u 1130 #define PASS0_SARMUX_PADS58_PORT 14u 1131 #define PASS0_SARMUX_PADS58_PIN 6u 1132 #define PASS0_SARMUX_PADS59_PORT 14u 1133 #define PASS0_SARMUX_PADS59_PIN 7u 1134 #define PASS0_SARMUX_PADS6_PORT 6u 1135 #define PASS0_SARMUX_PADS6_PIN 6u 1136 #define PASS0_SARMUX_PADS60_PORT 15u 1137 #define PASS0_SARMUX_PADS60_PIN 0u 1138 #define PASS0_SARMUX_PADS61_PORT 15u 1139 #define PASS0_SARMUX_PADS61_PIN 1u 1140 #define PASS0_SARMUX_PADS62_PORT 15u 1141 #define PASS0_SARMUX_PADS62_PIN 2u 1142 #define PASS0_SARMUX_PADS63_PORT 15u 1143 #define PASS0_SARMUX_PADS63_PIN 3u 1144 #define PASS0_SARMUX_PADS64_PORT 16u 1145 #define PASS0_SARMUX_PADS64_PIN 0u 1146 #define PASS0_SARMUX_PADS65_PORT 16u 1147 #define PASS0_SARMUX_PADS65_PIN 1u 1148 #define PASS0_SARMUX_PADS66_PORT 16u 1149 #define PASS0_SARMUX_PADS66_PIN 2u 1150 #define PASS0_SARMUX_PADS67_PORT 16u 1151 #define PASS0_SARMUX_PADS67_PIN 3u 1152 #define PASS0_SARMUX_PADS68_PORT 16u 1153 #define PASS0_SARMUX_PADS68_PIN 4u 1154 #define PASS0_SARMUX_PADS69_PORT 16u 1155 #define PASS0_SARMUX_PADS69_PIN 5u 1156 #define PASS0_SARMUX_PADS7_PORT 6u 1157 #define PASS0_SARMUX_PADS7_PIN 7u 1158 #define PASS0_SARMUX_PADS70_PORT 16u 1159 #define PASS0_SARMUX_PADS70_PIN 6u 1160 #define PASS0_SARMUX_PADS71_PORT 16u 1161 #define PASS0_SARMUX_PADS71_PIN 7u 1162 #define PASS0_SARMUX_PADS72_PORT 17u 1163 #define PASS0_SARMUX_PADS72_PIN 0u 1164 #define PASS0_SARMUX_PADS73_PORT 17u 1165 #define PASS0_SARMUX_PADS73_PIN 1u 1166 #define PASS0_SARMUX_PADS74_PORT 17u 1167 #define PASS0_SARMUX_PADS74_PIN 2u 1168 #define PASS0_SARMUX_PADS75_PORT 17u 1169 #define PASS0_SARMUX_PADS75_PIN 3u 1170 #define PASS0_SARMUX_PADS76_PORT 17u 1171 #define PASS0_SARMUX_PADS76_PIN 4u 1172 #define PASS0_SARMUX_PADS77_PORT 17u 1173 #define PASS0_SARMUX_PADS77_PIN 5u 1174 #define PASS0_SARMUX_PADS78_PORT 17u 1175 #define PASS0_SARMUX_PADS78_PIN 6u 1176 #define PASS0_SARMUX_PADS79_PORT 17u 1177 #define PASS0_SARMUX_PADS79_PIN 7u 1178 #define PASS0_SARMUX_PADS8_PORT 32u 1179 #define PASS0_SARMUX_PADS8_PIN 0u 1180 #define PASS0_SARMUX_PADS80_PORT 18u 1181 #define PASS0_SARMUX_PADS80_PIN 0u 1182 #define PASS0_SARMUX_PADS81_PORT 18u 1183 #define PASS0_SARMUX_PADS81_PIN 1u 1184 #define PASS0_SARMUX_PADS82_PORT 18u 1185 #define PASS0_SARMUX_PADS82_PIN 2u 1186 #define PASS0_SARMUX_PADS83_PORT 18u 1187 #define PASS0_SARMUX_PADS83_PIN 3u 1188 #define PASS0_SARMUX_PADS84_PORT 18u 1189 #define PASS0_SARMUX_PADS84_PIN 4u 1190 #define PASS0_SARMUX_PADS85_PORT 18u 1191 #define PASS0_SARMUX_PADS85_PIN 5u 1192 #define PASS0_SARMUX_PADS86_PORT 18u 1193 #define PASS0_SARMUX_PADS86_PIN 6u 1194 #define PASS0_SARMUX_PADS87_PORT 18u 1195 #define PASS0_SARMUX_PADS87_PIN 7u 1196 #define PASS0_SARMUX_PADS88_PORT 19u 1197 #define PASS0_SARMUX_PADS88_PIN 0u 1198 #define PASS0_SARMUX_PADS89_PORT 19u 1199 #define PASS0_SARMUX_PADS89_PIN 1u 1200 #define PASS0_SARMUX_PADS9_PORT 32u 1201 #define PASS0_SARMUX_PADS9_PIN 1u 1202 #define PASS0_SARMUX_PADS90_PORT 19u 1203 #define PASS0_SARMUX_PADS90_PIN 2u 1204 #define PASS0_SARMUX_PADS91_PORT 19u 1205 #define PASS0_SARMUX_PADS91_PIN 3u 1206 #define PASS0_SARMUX_PADS92_PORT 19u 1207 #define PASS0_SARMUX_PADS92_PIN 4u 1208 #define PASS0_SARMUX_PADS93_PORT 20u 1209 #define PASS0_SARMUX_PADS93_PIN 0u 1210 #define PASS0_SARMUX_PADS94_PORT 20u 1211 #define PASS0_SARMUX_PADS94_PIN 1u 1212 #define PASS0_SARMUX_PADS95_PORT 20u 1213 #define PASS0_SARMUX_PADS95_PIN 2u 1214 #define PASS0_VB_TEMP_KELVIN_PORT 10u 1215 #define PASS0_VB_TEMP_KELVIN_PIN 4u 1216 #define PASS0_VE_TEMP_KELVIN_PORT 23u 1217 #define PASS0_VE_TEMP_KELVIN_PIN 4u 1218 #define SRSS_ADFT_PIN0_PORT 23u 1219 #define SRSS_ADFT_PIN0_PIN 4u 1220 #define SRSS_ADFT_PIN1_PORT 23u 1221 #define SRSS_ADFT_PIN1_PIN 3u 1222 #define SRSS_ADFT_POR_PAD_HV_PORT 21u 1223 #define SRSS_ADFT_POR_PAD_HV_PIN 4u 1224 #define SRSS_ECO_IN_PORT 21u 1225 #define SRSS_ECO_IN_PIN 2u 1226 #define SRSS_ECO_OUT_PORT 21u 1227 #define SRSS_ECO_OUT_PIN 3u 1228 #define SRSS_REGHC_ISENSE_INM_PORT 22u 1229 #define SRSS_REGHC_ISENSE_INM_PIN 2u 1230 #define SRSS_REGHC_ISENSE_INP_PORT 22u 1231 #define SRSS_REGHC_ISENSE_INP_PIN 1u 1232 #define SRSS_REGHC_RST_VOUT_PORT 22u 1233 #define SRSS_REGHC_RST_VOUT_PIN 3u 1234 #define SRSS_VEXT_REF_REG_PORT 21u 1235 #define SRSS_VEXT_REF_REG_PIN 3u 1236 #define SRSS_WCO_IN_PORT 21u 1237 #define SRSS_WCO_IN_PIN 0u 1238 #define SRSS_WCO_OUT_PORT 21u 1239 #define SRSS_WCO_OUT_PIN 1u 1240 1241 /* HSIOM Connections */ 1242 typedef enum 1243 { 1244 /* Generic HSIOM connections */ 1245 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 1246 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1247 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1248 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1249 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 1250 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 1251 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1252 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1253 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 1254 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 1255 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 1256 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 1257 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 1258 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 1259 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 1260 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 1261 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 1262 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 1263 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 1264 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 1265 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 1266 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 1267 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 1268 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 1269 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 1270 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 1271 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 1272 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 1273 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 1274 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 1275 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 1276 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 1277 1278 /* P0.0 */ 1279 P0_0_GPIO = 0, /* GPIO controls 'out' */ 1280 P0_0_AMUXA = 4, /* Analog mux bus A */ 1281 P0_0_AMUXB = 5, /* Analog mux bus B */ 1282 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1283 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1284 P0_0_TCPWM1_LINE18 = 8, /* Digital Active - tcpwm[1].line[18]:1 */ 1285 P0_0_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:1 */ 1286 P0_0_TCPWM1_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[54]:1 */ 1287 P0_0_TCPWM1_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[67]:1 */ 1288 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 1289 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 1290 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 1291 P0_0_TCPWM0_LINE512 = 22, /* Digital Active - tcpwm[0].line[512] */ 1292 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 1293 1294 /* P0.1 */ 1295 P0_1_GPIO = 0, /* GPIO controls 'out' */ 1296 P0_1_AMUXA = 4, /* Analog mux bus A */ 1297 P0_1_AMUXB = 5, /* Analog mux bus B */ 1298 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1299 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1300 P0_1_TCPWM1_LINE17 = 8, /* Digital Active - tcpwm[1].line[17]:1 */ 1301 P0_1_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */ 1302 P0_1_TCPWM1_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[51]:1 */ 1303 P0_1_TCPWM1_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[55]:1 */ 1304 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 1305 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 1306 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 1307 P0_1_TCPWM0_LINE_COMPL512 = 22, /* Digital Active - tcpwm[0].line_compl[512] */ 1308 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 1309 1310 /* P0.2 */ 1311 P0_2_GPIO = 0, /* GPIO controls 'out' */ 1312 P0_2_AMUXA = 4, /* Analog mux bus A */ 1313 P0_2_AMUXB = 5, /* Analog mux bus B */ 1314 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1315 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1316 P0_2_TCPWM1_LINE14 = 8, /* Digital Active - tcpwm[1].line[14]:1 */ 1317 P0_2_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */ 1318 P0_2_TCPWM1_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[42]:1 */ 1319 P0_2_TCPWM1_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[52]:1 */ 1320 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 1321 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 1322 P0_2_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:2 */ 1323 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 1324 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 1325 P0_2_TCPWM0_TR_ONE_CNT_IN1536 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536] */ 1326 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 1327 1328 /* P0.3 */ 1329 P0_3_GPIO = 0, /* GPIO controls 'out' */ 1330 P0_3_AMUXA = 4, /* Analog mux bus A */ 1331 P0_3_AMUXB = 5, /* Analog mux bus B */ 1332 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1333 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1334 P0_3_TCPWM1_LINE13 = 8, /* Digital Active - tcpwm[1].line[13]:1 */ 1335 P0_3_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 1336 P0_3_TCPWM1_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[39]:1 */ 1337 P0_3_TCPWM1_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[43]:1 */ 1338 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 1339 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 1340 P0_3_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:2 */ 1341 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 1342 P0_3_TCPWM0_TR_ONE_CNT_IN1537 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537] */ 1343 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 1344 1345 /* P1.0 */ 1346 P1_0_GPIO = 0, /* GPIO controls 'out' */ 1347 P1_0_AMUXA = 4, /* Analog mux bus A */ 1348 P1_0_AMUXB = 5, /* Analog mux bus B */ 1349 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1350 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1351 P1_0_TCPWM1_LINE12 = 8, /* Digital Active - tcpwm[1].line[12]:1 */ 1352 P1_0_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:1 */ 1353 P1_0_TCPWM1_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[36]:1 */ 1354 P1_0_TCPWM1_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[40]:1 */ 1355 P1_0_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 1356 P1_0_TCPWM1_LINE516 = 16, /* Digital Active - tcpwm[1].line[516]:0 */ 1357 P1_0_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:2 */ 1358 P1_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 1359 1360 /* P1.1 */ 1361 P1_1_GPIO = 0, /* GPIO controls 'out' */ 1362 P1_1_AMUXA = 4, /* Analog mux bus A */ 1363 P1_1_AMUXB = 5, /* Analog mux bus B */ 1364 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1365 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1366 P1_1_TCPWM1_LINE11 = 8, /* Digital Active - tcpwm[1].line[11]:1 */ 1367 P1_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ 1368 P1_1_TCPWM1_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[33]:1 */ 1369 P1_1_TCPWM1_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[37]:1 */ 1370 P1_1_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 1371 P1_1_TCPWM1_LINE517 = 16, /* Digital Active - tcpwm[1].line[517]:0 */ 1372 P1_1_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:2 */ 1373 P1_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 1374 1375 /* P1.2 */ 1376 P1_2_GPIO = 0, /* GPIO controls 'out' */ 1377 P1_2_AMUXA = 4, /* Analog mux bus A */ 1378 P1_2_AMUXB = 5, /* Analog mux bus B */ 1379 P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1380 P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1381 P1_2_TCPWM1_LINE10 = 8, /* Digital Active - tcpwm[1].line[10]:1 */ 1382 P1_2_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ 1383 P1_2_TCPWM1_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[30]:1 */ 1384 P1_2_TCPWM1_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[34]:1 */ 1385 P1_2_TCPWM1_LINE518 = 16, /* Digital Active - tcpwm[1].line[518]:0 */ 1386 P1_2_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:2 */ 1387 P1_2_PERI_TR_IO_INPUT0 = 26, /* Digital Active - peri.tr_io_input[0]:0 */ 1388 P1_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:1 */ 1389 1390 /* P1.3 */ 1391 P1_3_GPIO = 0, /* GPIO controls 'out' */ 1392 P1_3_AMUXA = 4, /* Analog mux bus A */ 1393 P1_3_AMUXB = 5, /* Analog mux bus B */ 1394 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1395 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1396 P1_3_TCPWM1_LINE8 = 8, /* Digital Active - tcpwm[1].line[8]:1 */ 1397 P1_3_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:1 */ 1398 P1_3_TCPWM1_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[24]:1 */ 1399 P1_3_TCPWM1_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[31]:1 */ 1400 P1_3_TCPWM1_LINE519 = 16, /* Digital Active - tcpwm[1].line[519]:0 */ 1401 P1_3_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:2 */ 1402 P1_3_PERI_TR_IO_INPUT1 = 26, /* Digital Active - peri.tr_io_input[1]:0 */ 1403 P1_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:1 */ 1404 1405 /* P1.4 */ 1406 P1_4_GPIO = 0, /* GPIO controls 'out' */ 1407 P1_4_AMUXA = 4, /* Analog mux bus A */ 1408 P1_4_AMUXB = 5, /* Analog mux bus B */ 1409 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1410 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1411 P1_4_TCPWM1_LINE71 = 8, /* Digital Active - tcpwm[1].line[71]:0 */ 1412 P1_4_TCPWM1_LINE_COMPL70 = 9, /* Digital Active - tcpwm[1].line_compl[70]:0 */ 1413 P1_4_TCPWM1_TR_ONE_CNT_IN213 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[213]:0 */ 1414 P1_4_TCPWM1_TR_ONE_CNT_IN211 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[211]:0 */ 1415 P1_4_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:1 */ 1416 P1_4_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:1 */ 1417 P1_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:2 */ 1418 1419 /* P2.0 */ 1420 P2_0_GPIO = 0, /* GPIO controls 'out' */ 1421 P2_0_AMUXA = 4, /* Analog mux bus A */ 1422 P2_0_AMUXB = 5, /* Analog mux bus B */ 1423 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1424 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1425 P2_0_TCPWM1_LINE7 = 8, /* Digital Active - tcpwm[1].line[7]:1 */ 1426 P2_0_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ 1427 P2_0_TCPWM1_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[21]:1 */ 1428 P2_0_TCPWM1_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[25]:1 */ 1429 P2_0_TCPWM1_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1548]:0 */ 1430 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 1431 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 1432 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 1433 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 1434 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 1435 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 1436 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 1437 1438 /* P2.1 */ 1439 P2_1_GPIO = 0, /* GPIO controls 'out' */ 1440 P2_1_AMUXA = 4, /* Analog mux bus A */ 1441 P2_1_AMUXB = 5, /* Analog mux bus B */ 1442 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1443 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1444 P2_1_TCPWM1_LINE6 = 8, /* Digital Active - tcpwm[1].line[6]:1 */ 1445 P2_1_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 1446 P2_1_TCPWM1_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[18]:1 */ 1447 P2_1_TCPWM1_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[22]:1 */ 1448 P2_1_TCPWM1_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1551]:0 */ 1449 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 1450 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 1451 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 1452 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 1453 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 1454 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 1455 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 1456 1457 /* P2.2 */ 1458 P2_2_GPIO = 0, /* GPIO controls 'out' */ 1459 P2_2_AMUXA = 4, /* Analog mux bus A */ 1460 P2_2_AMUXB = 5, /* Analog mux bus B */ 1461 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1462 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1463 P2_2_TCPWM1_LINE5 = 8, /* Digital Active - tcpwm[1].line[5]:1 */ 1464 P2_2_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 1465 P2_2_TCPWM1_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[15]:1 */ 1466 P2_2_TCPWM1_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[19]:1 */ 1467 P2_2_TCPWM1_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1554]:0 */ 1468 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 1469 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 1470 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 1471 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 1472 P2_2_ETH0_RX_ER = 24, /* Digital Active - eth[0].rx_er:0 */ 1473 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 1474 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 1475 1476 /* P2.3 */ 1477 P2_3_GPIO = 0, /* GPIO controls 'out' */ 1478 P2_3_AMUXA = 4, /* Analog mux bus A */ 1479 P2_3_AMUXB = 5, /* Analog mux bus B */ 1480 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1481 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1482 P2_3_TCPWM1_LINE4 = 8, /* Digital Active - tcpwm[1].line[4]:1 */ 1483 P2_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 1484 P2_3_TCPWM1_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[12]:1 */ 1485 P2_3_TCPWM1_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[16]:1 */ 1486 P2_3_TCPWM1_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1557]:0 */ 1487 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 1488 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 1489 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 1490 P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL = 24, /* Digital Active - eth[0].eth_tsu_timer_cmp_val:0 */ 1491 P2_3_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:2 */ 1492 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 1493 1494 /* P2.4 */ 1495 P2_4_GPIO = 0, /* GPIO controls 'out' */ 1496 P2_4_AMUXA = 4, /* Analog mux bus A */ 1497 P2_4_AMUXB = 5, /* Analog mux bus B */ 1498 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1499 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1500 P2_4_TCPWM1_LINE3 = 8, /* Digital Active - tcpwm[1].line[3]:1 */ 1501 P2_4_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 1502 P2_4_TCPWM1_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[9]:1 */ 1503 P2_4_TCPWM1_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[13]:1 */ 1504 P2_4_TCPWM1_LINE_COMPL516 = 16, /* Digital Active - tcpwm[1].line_compl[516]:0 */ 1505 P2_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:0 */ 1506 P2_4_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:1 */ 1507 P2_4_PERI_TR_IO_INPUT6 = 26, /* Digital Active - peri.tr_io_input[6]:0 */ 1508 1509 /* P2.5 */ 1510 P2_5_GPIO = 0, /* GPIO controls 'out' */ 1511 P2_5_AMUXA = 4, /* Analog mux bus A */ 1512 P2_5_AMUXB = 5, /* Analog mux bus B */ 1513 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1514 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1515 P2_5_TCPWM1_LINE2 = 8, /* Digital Active - tcpwm[1].line[2]:1 */ 1516 P2_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1517 P2_5_TCPWM1_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[6]:1 */ 1518 P2_5_TCPWM1_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[10]:1 */ 1519 P2_5_TCPWM1_LINE_COMPL517 = 16, /* Digital Active - tcpwm[1].line_compl[517]:0 */ 1520 P2_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:0 */ 1521 P2_5_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:1 */ 1522 P2_5_PERI_TR_IO_INPUT7 = 26, /* Digital Active - peri.tr_io_input[7]:0 */ 1523 1524 /* P2.6 */ 1525 P2_6_GPIO = 0, /* GPIO controls 'out' */ 1526 P2_6_AMUXA = 4, /* Analog mux bus A */ 1527 P2_6_AMUXB = 5, /* Analog mux bus B */ 1528 P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1529 P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1530 P2_6_TCPWM1_LINE72 = 8, /* Digital Active - tcpwm[1].line[72]:0 */ 1531 P2_6_TCPWM1_LINE_COMPL71 = 9, /* Digital Active - tcpwm[1].line_compl[71]:0 */ 1532 P2_6_TCPWM1_TR_ONE_CNT_IN216 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[216]:0 */ 1533 P2_6_TCPWM1_TR_ONE_CNT_IN214 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[214]:0 */ 1534 P2_6_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:1 */ 1535 P2_6_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:1 */ 1536 1537 /* P2.7 */ 1538 P2_7_GPIO = 0, /* GPIO controls 'out' */ 1539 P2_7_AMUXA = 4, /* Analog mux bus A */ 1540 P2_7_AMUXB = 5, /* Analog mux bus B */ 1541 P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1542 P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1543 P2_7_TCPWM1_LINE73 = 8, /* Digital Active - tcpwm[1].line[73]:0 */ 1544 P2_7_TCPWM1_LINE_COMPL72 = 9, /* Digital Active - tcpwm[1].line_compl[72]:0 */ 1545 P2_7_TCPWM1_TR_ONE_CNT_IN219 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[219]:0 */ 1546 P2_7_TCPWM1_TR_ONE_CNT_IN217 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[217]:0 */ 1547 P2_7_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:1 */ 1548 P2_7_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:1 */ 1549 1550 /* P3.0 */ 1551 P3_0_GPIO = 0, /* GPIO controls 'out' */ 1552 P3_0_AMUXA = 4, /* Analog mux bus A */ 1553 P3_0_AMUXB = 5, /* Analog mux bus B */ 1554 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1555 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1556 P3_0_TCPWM1_LINE1 = 8, /* Digital Active - tcpwm[1].line[1]:1 */ 1557 P3_0_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1558 P3_0_TCPWM1_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[3]:1 */ 1559 P3_0_TCPWM1_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[7]:1 */ 1560 P3_0_TCPWM1_LINE_COMPL518 = 16, /* Digital Active - tcpwm[1].line_compl[518]:0 */ 1561 P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ 1562 P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ 1563 P3_0_CANFD0_TTCAN_TX3 = 21, /* Digital Active - canfd[0].ttcan_tx[3]:0 */ 1564 P3_0_ETH0_MDIO = 24, /* Digital Active - eth[0].mdio:0 */ 1565 P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 1566 1567 /* P3.1 */ 1568 P3_1_GPIO = 0, /* GPIO controls 'out' */ 1569 P3_1_AMUXA = 4, /* Analog mux bus A */ 1570 P3_1_AMUXB = 5, /* Analog mux bus B */ 1571 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1572 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1573 P3_1_TCPWM1_LINE0 = 8, /* Digital Active - tcpwm[1].line[0]:1 */ 1574 P3_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1575 P3_1_TCPWM1_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[0]:1 */ 1576 P3_1_TCPWM1_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[4]:1 */ 1577 P3_1_TCPWM1_LINE_COMPL519 = 16, /* Digital Active - tcpwm[1].line_compl[519]:0 */ 1578 P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ 1579 P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ 1580 P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ 1581 P3_1_CANFD0_TTCAN_RX3 = 21, /* Digital Active - canfd[0].ttcan_rx[3]:0 */ 1582 P3_1_ETH0_MDC = 24, /* Digital Active - eth[0].mdc:0 */ 1583 P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 1584 1585 /* P3.2 */ 1586 P3_2_GPIO = 0, /* GPIO controls 'out' */ 1587 P3_2_AMUXA = 4, /* Analog mux bus A */ 1588 P3_2_AMUXB = 5, /* Analog mux bus B */ 1589 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1590 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1591 P3_2_TCPWM1_LINE259 = 8, /* Digital Active - tcpwm[1].line[259]:1 */ 1592 P3_2_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1593 P3_2_TCPWM1_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[777]:1 */ 1594 P3_2_TCPWM1_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[1]:1 */ 1595 P3_2_TCPWM1_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1549]:0 */ 1596 P3_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:0 */ 1597 P3_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:0 */ 1598 P3_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:0 */ 1599 1600 /* P3.3 */ 1601 P3_3_GPIO = 0, /* GPIO controls 'out' */ 1602 P3_3_AMUXA = 4, /* Analog mux bus A */ 1603 P3_3_AMUXB = 5, /* Analog mux bus B */ 1604 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1605 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1606 P3_3_TCPWM1_LINE258 = 8, /* Digital Active - tcpwm[1].line[258]:1 */ 1607 P3_3_TCPWM1_LINE_COMPL259 = 9, /* Digital Active - tcpwm[1].line_compl[259]:1 */ 1608 P3_3_TCPWM1_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[774]:1 */ 1609 P3_3_TCPWM1_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[778]:1 */ 1610 P3_3_TCPWM1_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1552]:0 */ 1611 P3_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:0 */ 1612 P3_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:0 */ 1613 1614 /* P3.4 */ 1615 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1616 P3_4_AMUXA = 4, /* Analog mux bus A */ 1617 P3_4_AMUXB = 5, /* Analog mux bus B */ 1618 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1619 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1620 P3_4_TCPWM1_LINE257 = 8, /* Digital Active - tcpwm[1].line[257]:1 */ 1621 P3_4_TCPWM1_LINE_COMPL258 = 9, /* Digital Active - tcpwm[1].line_compl[258]:1 */ 1622 P3_4_TCPWM1_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[771]:1 */ 1623 P3_4_TCPWM1_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[775]:1 */ 1624 P3_4_TCPWM1_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1555]:0 */ 1625 P3_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:0 */ 1626 P3_4_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:2 */ 1627 1628 /* P3.5 */ 1629 P3_5_GPIO = 0, /* GPIO controls 'out' */ 1630 P3_5_AMUXA = 4, /* Analog mux bus A */ 1631 P3_5_AMUXB = 5, /* Analog mux bus B */ 1632 P3_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1633 P3_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1634 P3_5_TCPWM1_LINE256 = 8, /* Digital Active - tcpwm[1].line[256]:1 */ 1635 P3_5_TCPWM1_LINE_COMPL257 = 9, /* Digital Active - tcpwm[1].line_compl[257]:1 */ 1636 P3_5_TCPWM1_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[768]:1 */ 1637 P3_5_TCPWM1_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[772]:1 */ 1638 P3_5_TCPWM1_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1558]:0 */ 1639 P3_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:0 */ 1640 P3_5_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:2 */ 1641 1642 /* P3.6 */ 1643 P3_6_GPIO = 0, /* GPIO controls 'out' */ 1644 P3_6_AMUXA = 4, /* Analog mux bus A */ 1645 P3_6_AMUXB = 5, /* Analog mux bus B */ 1646 P3_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1647 P3_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1648 P3_6_TCPWM1_LINE74 = 8, /* Digital Active - tcpwm[1].line[74]:0 */ 1649 P3_6_TCPWM1_LINE_COMPL73 = 9, /* Digital Active - tcpwm[1].line_compl[73]:0 */ 1650 P3_6_TCPWM1_TR_ONE_CNT_IN222 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[222]:0 */ 1651 P3_6_TCPWM1_TR_ONE_CNT_IN220 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[220]:0 */ 1652 P3_6_SCB8_SPI_SELECT2 = 19, /* Digital Active - scb[8].spi_select2:0 */ 1653 P3_6_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:1 */ 1654 P3_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:2 */ 1655 1656 /* P3.7 */ 1657 P3_7_GPIO = 0, /* GPIO controls 'out' */ 1658 P3_7_AMUXA = 4, /* Analog mux bus A */ 1659 P3_7_AMUXB = 5, /* Analog mux bus B */ 1660 P3_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1661 P3_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1662 P3_7_TCPWM1_LINE75 = 8, /* Digital Active - tcpwm[1].line[75]:0 */ 1663 P3_7_TCPWM1_LINE_COMPL74 = 9, /* Digital Active - tcpwm[1].line_compl[74]:0 */ 1664 P3_7_TCPWM1_TR_ONE_CNT_IN225 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[225]:0 */ 1665 P3_7_TCPWM1_TR_ONE_CNT_IN223 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[223]:0 */ 1666 P3_7_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:1 */ 1667 P3_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:2 */ 1668 1669 /* P4.0 */ 1670 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1671 P4_0_AMUXA = 4, /* Analog mux bus A */ 1672 P4_0_AMUXB = 5, /* Analog mux bus B */ 1673 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1674 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1675 P4_0_TCPWM1_LINE4 = 8, /* Digital Active - tcpwm[1].line[4]:0 */ 1676 P4_0_TCPWM1_LINE_COMPL256 = 9, /* Digital Active - tcpwm[1].line_compl[256]:1 */ 1677 P4_0_TCPWM1_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[12]:0 */ 1678 P4_0_TCPWM1_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[769]:1 */ 1679 P4_0_PASS0_SAR_EXT_MUX_SEL0 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[0] */ 1680 P4_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:0 */ 1681 P4_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:0 */ 1682 P4_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:1 */ 1683 P4_0_PERI_TR_IO_INPUT10 = 26, /* Digital Active - peri.tr_io_input[10]:0 */ 1684 1685 /* P4.1 */ 1686 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1687 P4_1_AMUXA = 4, /* Analog mux bus A */ 1688 P4_1_AMUXB = 5, /* Analog mux bus B */ 1689 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1690 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1691 P4_1_TCPWM1_LINE5 = 8, /* Digital Active - tcpwm[1].line[5]:0 */ 1692 P4_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 1693 P4_1_TCPWM1_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[15]:0 */ 1694 P4_1_TCPWM1_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[13]:0 */ 1695 P4_1_PASS0_SAR_EXT_MUX_SEL1 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[1] */ 1696 P4_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:0 */ 1697 P4_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:0 */ 1698 P4_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:0 */ 1699 P4_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:1 */ 1700 P4_1_PERI_TR_IO_INPUT11 = 26, /* Digital Active - peri.tr_io_input[11]:0 */ 1701 1702 /* P4.2 */ 1703 P4_2_GPIO = 0, /* GPIO controls 'out' */ 1704 P4_2_AMUXA = 4, /* Analog mux bus A */ 1705 P4_2_AMUXB = 5, /* Analog mux bus B */ 1706 P4_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1707 P4_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1708 P4_2_TCPWM1_LINE6 = 8, /* Digital Active - tcpwm[1].line[6]:0 */ 1709 P4_2_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 1710 P4_2_TCPWM1_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[18]:0 */ 1711 P4_2_TCPWM1_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[16]:0 */ 1712 P4_2_PASS0_SAR_EXT_MUX_SEL2 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[2] */ 1713 P4_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:0 */ 1714 P4_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:0 */ 1715 P4_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:0 */ 1716 P4_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:1 */ 1717 P4_2_PERI_TR_IO_INPUT12 = 26, /* Digital Active - peri.tr_io_input[12]:0 */ 1718 1719 /* P4.3 */ 1720 P4_3_GPIO = 0, /* GPIO controls 'out' */ 1721 P4_3_AMUXA = 4, /* Analog mux bus A */ 1722 P4_3_AMUXB = 5, /* Analog mux bus B */ 1723 P4_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1724 P4_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1725 P4_3_TCPWM1_LINE7 = 8, /* Digital Active - tcpwm[1].line[7]:0 */ 1726 P4_3_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 1727 P4_3_TCPWM1_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[21]:0 */ 1728 P4_3_TCPWM1_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[19]:0 */ 1729 P4_3_PASS0_SAR_EXT_MUX_EN0 = 16, /* Digital Active - pass[0].sar_ext_mux_en[0] */ 1730 P4_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:0 */ 1731 P4_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:0 */ 1732 P4_3_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:1 */ 1733 P4_3_PERI_TR_IO_INPUT13 = 26, /* Digital Active - peri.tr_io_input[13]:0 */ 1734 1735 /* P4.4 */ 1736 P4_4_GPIO = 0, /* GPIO controls 'out' */ 1737 P4_4_AMUXA = 4, /* Analog mux bus A */ 1738 P4_4_AMUXB = 5, /* Analog mux bus B */ 1739 P4_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1740 P4_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1741 P4_4_TCPWM1_LINE8 = 8, /* Digital Active - tcpwm[1].line[8]:0 */ 1742 P4_4_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 1743 P4_4_TCPWM1_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[24]:0 */ 1744 P4_4_TCPWM1_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[22]:0 */ 1745 P4_4_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:1 */ 1746 P4_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:0 */ 1747 P4_4_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:1 */ 1748 1749 /* P5.0 */ 1750 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1751 P5_0_AMUXA = 4, /* Analog mux bus A */ 1752 P5_0_AMUXB = 5, /* Analog mux bus B */ 1753 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1754 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1755 P5_0_TCPWM1_LINE9 = 8, /* Digital Active - tcpwm[1].line[9]:0 */ 1756 P5_0_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 1757 P5_0_TCPWM1_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[27]:0 */ 1758 P5_0_TCPWM1_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[25]:0 */ 1759 P5_0_TCPWM1_LINE522 = 16, /* Digital Active - tcpwm[1].line[522]:0 */ 1760 P5_0_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:1 */ 1761 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 1762 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 1763 P5_0_TCPWM0_LINE256 = 22, /* Digital Active - tcpwm[0].line[256] */ 1764 P5_0_PERI_TR_IO_INPUT38 = 26, /* Digital Active - peri.tr_io_input[38]:0 */ 1765 1766 /* P5.1 */ 1767 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1768 P5_1_AMUXA = 4, /* Analog mux bus A */ 1769 P5_1_AMUXB = 5, /* Analog mux bus B */ 1770 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1771 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1772 P5_1_TCPWM1_LINE10 = 8, /* Digital Active - tcpwm[1].line[10]:0 */ 1773 P5_1_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 1774 P5_1_TCPWM1_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[30]:0 */ 1775 P5_1_TCPWM1_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[28]:0 */ 1776 P5_1_TCPWM1_LINE_COMPL522 = 16, /* Digital Active - tcpwm[1].line_compl[522]:0 */ 1777 P5_1_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:1 */ 1778 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 1779 P5_1_TCPWM0_LINE_COMPL256 = 22, /* Digital Active - tcpwm[0].line_compl[256] */ 1780 P5_1_PERI_TR_IO_INPUT39 = 26, /* Digital Active - peri.tr_io_input[39]:0 */ 1781 1782 /* P5.2 */ 1783 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1784 P5_2_AMUXA = 4, /* Analog mux bus A */ 1785 P5_2_AMUXB = 5, /* Analog mux bus B */ 1786 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1787 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1788 P5_2_TCPWM1_LINE11 = 8, /* Digital Active - tcpwm[1].line[11]:0 */ 1789 P5_2_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 1790 P5_2_TCPWM1_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[33]:0 */ 1791 P5_2_TCPWM1_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[31]:0 */ 1792 P5_2_TCPWM1_TR_ONE_CNT_IN1566 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1566]:0 */ 1793 P5_2_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:2 */ 1794 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 1795 P5_2_TCPWM0_TR_ONE_CNT_IN768 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[768] */ 1796 1797 /* P5.3 */ 1798 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1799 P5_3_AMUXA = 4, /* Analog mux bus A */ 1800 P5_3_AMUXB = 5, /* Analog mux bus B */ 1801 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1802 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1803 P5_3_TCPWM1_LINE12 = 8, /* Digital Active - tcpwm[1].line[12]:0 */ 1804 P5_3_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 1805 P5_3_TCPWM1_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[36]:0 */ 1806 P5_3_TCPWM1_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[34]:0 */ 1807 P5_3_TCPWM1_TR_ONE_CNT_IN1567 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1567]:0 */ 1808 P5_3_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:2 */ 1809 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 1810 P5_3_TCPWM0_TR_ONE_CNT_IN769 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[769] */ 1811 1812 /* P5.4 */ 1813 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1814 P5_4_AMUXA = 4, /* Analog mux bus A */ 1815 P5_4_AMUXB = 5, /* Analog mux bus B */ 1816 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1817 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1818 P5_4_TCPWM1_LINE13 = 8, /* Digital Active - tcpwm[1].line[13]:0 */ 1819 P5_4_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1820 P5_4_TCPWM1_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[39]:0 */ 1821 P5_4_TCPWM1_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[37]:0 */ 1822 P5_4_TCPWM1_LINE523 = 16, /* Digital Active - tcpwm[1].line[523]:0 */ 1823 P5_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:0 */ 1824 P5_4_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:1 */ 1825 1826 /* P5.5 */ 1827 P5_5_GPIO = 0, /* GPIO controls 'out' */ 1828 P5_5_AMUXA = 4, /* Analog mux bus A */ 1829 P5_5_AMUXB = 5, /* Analog mux bus B */ 1830 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1831 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1832 P5_5_TCPWM1_LINE14 = 8, /* Digital Active - tcpwm[1].line[14]:0 */ 1833 P5_5_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1834 P5_5_TCPWM1_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[42]:0 */ 1835 P5_5_TCPWM1_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[40]:0 */ 1836 P5_5_TCPWM1_LINE_COMPL523 = 16, /* Digital Active - tcpwm[1].line_compl[523]:0 */ 1837 P5_5_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:0 */ 1838 P5_5_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:1 */ 1839 1840 /* P6.0 */ 1841 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1842 P6_0_AMUXA = 4, /* Analog mux bus A */ 1843 P6_0_AMUXB = 5, /* Analog mux bus B */ 1844 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1845 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1846 P6_0_TCPWM1_LINE256 = 8, /* Digital Active - tcpwm[1].line[256]:0 */ 1847 P6_0_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ 1848 P6_0_TCPWM1_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[768]:0 */ 1849 P6_0_TCPWM1_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[43]:0 */ 1850 P6_0_TCPWM1_TR_ONE_CNT_IN1569 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1569]:0 */ 1851 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 1852 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 1853 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 1854 P6_0_TCPWM0_LINE0 = 22, /* Digital Active - tcpwm[0].line[0] */ 1855 P6_0_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:1 */ 1856 1857 /* P6.1 */ 1858 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1859 P6_1_AMUXA = 4, /* Analog mux bus A */ 1860 P6_1_AMUXB = 5, /* Analog mux bus B */ 1861 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1862 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1863 P6_1_TCPWM1_LINE0 = 8, /* Digital Active - tcpwm[1].line[0]:0 */ 1864 P6_1_TCPWM1_LINE_COMPL256 = 9, /* Digital Active - tcpwm[1].line_compl[256]:0 */ 1865 P6_1_TCPWM1_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[0]:0 */ 1866 P6_1_TCPWM1_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[769]:0 */ 1867 P6_1_TCPWM1_TR_ONE_CNT_IN1570 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1570]:0 */ 1868 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 1869 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 1870 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 1871 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 1872 1873 /* P6.2 */ 1874 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1875 P6_2_AMUXA = 4, /* Analog mux bus A */ 1876 P6_2_AMUXB = 5, /* Analog mux bus B */ 1877 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1878 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1879 P6_2_TCPWM1_LINE257 = 8, /* Digital Active - tcpwm[1].line[257]:0 */ 1880 P6_2_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 1881 P6_2_TCPWM1_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[771]:0 */ 1882 P6_2_TCPWM1_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[1]:0 */ 1883 P6_2_TCPWM1_LINE524 = 16, /* Digital Active - tcpwm[1].line[524]:0 */ 1884 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 1885 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 1886 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 1887 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 1888 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 1889 P6_2_TCPWM0_LINE_COMPL0 = 22, /* Digital Active - tcpwm[0].line_compl[0] */ 1890 P6_2_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:0 */ 1891 1892 /* P6.3 */ 1893 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1894 P6_3_AMUXA = 4, /* Analog mux bus A */ 1895 P6_3_AMUXB = 5, /* Analog mux bus B */ 1896 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1897 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1898 P6_3_TCPWM1_LINE1 = 8, /* Digital Active - tcpwm[1].line[1]:0 */ 1899 P6_3_TCPWM1_LINE_COMPL257 = 9, /* Digital Active - tcpwm[1].line_compl[257]:0 */ 1900 P6_3_TCPWM1_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[3]:0 */ 1901 P6_3_TCPWM1_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[772]:0 */ 1902 P6_3_TCPWM1_LINE_COMPL524 = 16, /* Digital Active - tcpwm[1].line_compl[524]:0 */ 1903 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 1904 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 1905 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 1906 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 1907 P6_3_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:0 */ 1908 P6_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:0 */ 1909 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 1910 1911 /* P6.4 */ 1912 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1913 P6_4_AMUXA = 4, /* Analog mux bus A */ 1914 P6_4_AMUXB = 5, /* Analog mux bus B */ 1915 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1916 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1917 P6_4_TCPWM1_LINE258 = 8, /* Digital Active - tcpwm[1].line[258]:0 */ 1918 P6_4_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 1919 P6_4_TCPWM1_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[774]:0 */ 1920 P6_4_TCPWM1_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[4]:0 */ 1921 P6_4_TCPWM1_TR_ONE_CNT_IN1572 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1572]:0 */ 1922 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 1923 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 1924 P6_4_TCPWM0_TR_ONE_CNT_IN0 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[0] */ 1925 P6_4_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:0 */ 1926 P6_4_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:0 */ 1927 1928 /* P6.5 */ 1929 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1930 P6_5_AMUXA = 4, /* Analog mux bus A */ 1931 P6_5_AMUXB = 5, /* Analog mux bus B */ 1932 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1933 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1934 P6_5_TCPWM1_LINE2 = 8, /* Digital Active - tcpwm[1].line[2]:0 */ 1935 P6_5_TCPWM1_LINE_COMPL258 = 9, /* Digital Active - tcpwm[1].line_compl[258]:0 */ 1936 P6_5_TCPWM1_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[6]:0 */ 1937 P6_5_TCPWM1_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[775]:0 */ 1938 P6_5_TCPWM1_TR_ONE_CNT_IN1573 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1573]:0 */ 1939 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 1940 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 1941 P6_5_TCPWM0_TR_ONE_CNT_IN1 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1] */ 1942 P6_5_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:0 */ 1943 P6_5_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:0 */ 1944 1945 /* P6.6 */ 1946 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1947 P6_6_AMUXA = 4, /* Analog mux bus A */ 1948 P6_6_AMUXB = 5, /* Analog mux bus B */ 1949 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1950 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1951 P6_6_TCPWM1_LINE259 = 8, /* Digital Active - tcpwm[1].line[259]:0 */ 1952 P6_6_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 1953 P6_6_TCPWM1_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[777]:0 */ 1954 P6_6_TCPWM1_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[7]:0 */ 1955 P6_6_SCB4_SPI_SELECT3 = 19, /* Digital Active - scb[4].spi_select3:0 */ 1956 P6_6_PERI_TR_IO_INPUT8 = 26, /* Digital Active - peri.tr_io_input[8]:0 */ 1957 1958 /* P6.7 */ 1959 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1960 P6_7_AMUXA = 4, /* Analog mux bus A */ 1961 P6_7_AMUXB = 5, /* Analog mux bus B */ 1962 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1963 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1964 P6_7_TCPWM1_LINE3 = 8, /* Digital Active - tcpwm[1].line[3]:0 */ 1965 P6_7_TCPWM1_LINE_COMPL259 = 9, /* Digital Active - tcpwm[1].line_compl[259]:0 */ 1966 P6_7_TCPWM1_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[9]:0 */ 1967 P6_7_TCPWM1_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[778]:0 */ 1968 P6_7_PERI_TR_IO_INPUT9 = 26, /* Digital Active - peri.tr_io_input[9]:0 */ 1969 1970 /* P7.0 */ 1971 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1972 P7_0_AMUXA = 4, /* Analog mux bus A */ 1973 P7_0_AMUXB = 5, /* Analog mux bus B */ 1974 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1975 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1976 P7_0_TCPWM1_LINE260 = 8, /* Digital Active - tcpwm[1].line[260]:0 */ 1977 P7_0_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 1978 P7_0_TCPWM1_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[780]:0 */ 1979 P7_0_TCPWM1_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[10]:0 */ 1980 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 1981 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 1982 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 1983 P7_0_TCPWM0_LINE1 = 22, /* Digital Active - tcpwm[0].line[1] */ 1984 P7_0_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:0 */ 1985 P7_0_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:0 */ 1986 1987 /* P7.1 */ 1988 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1989 P7_1_AMUXA = 4, /* Analog mux bus A */ 1990 P7_1_AMUXB = 5, /* Analog mux bus B */ 1991 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1992 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1993 P7_1_TCPWM1_LINE15 = 8, /* Digital Active - tcpwm[1].line[15]:0 */ 1994 P7_1_TCPWM1_LINE_COMPL260 = 9, /* Digital Active - tcpwm[1].line_compl[260]:0 */ 1995 P7_1_TCPWM1_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[45]:0 */ 1996 P7_1_TCPWM1_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[781]:0 */ 1997 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 1998 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 1999 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 2000 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 2001 P7_1_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:0 */ 2002 P7_1_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:0 */ 2003 2004 /* P7.2 */ 2005 P7_2_GPIO = 0, /* GPIO controls 'out' */ 2006 P7_2_AMUXA = 4, /* Analog mux bus A */ 2007 P7_2_AMUXB = 5, /* Analog mux bus B */ 2008 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2009 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2010 P7_2_TCPWM1_LINE261 = 8, /* Digital Active - tcpwm[1].line[261]:0 */ 2011 P7_2_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 2012 P7_2_TCPWM1_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[783]:0 */ 2013 P7_2_TCPWM1_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[46]:0 */ 2014 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 2015 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 2016 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 2017 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 2018 P7_2_TCPWM0_LINE_COMPL1 = 22, /* Digital Active - tcpwm[0].line_compl[1] */ 2019 P7_2_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:0 */ 2020 P7_2_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:0 */ 2021 2022 /* P7.3 */ 2023 P7_3_GPIO = 0, /* GPIO controls 'out' */ 2024 P7_3_AMUXA = 4, /* Analog mux bus A */ 2025 P7_3_AMUXB = 5, /* Analog mux bus B */ 2026 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2027 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2028 P7_3_TCPWM1_LINE16 = 8, /* Digital Active - tcpwm[1].line[16]:0 */ 2029 P7_3_TCPWM1_LINE_COMPL261 = 9, /* Digital Active - tcpwm[1].line_compl[261]:0 */ 2030 P7_3_TCPWM1_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[48]:0 */ 2031 P7_3_TCPWM1_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[784]:0 */ 2032 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 2033 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 2034 P7_3_CANFD0_TTCAN_TX4 = 21, /* Digital Active - canfd[0].ttcan_tx[4]:0 */ 2035 P7_3_TCPWM0_TR_ONE_CNT_IN3 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[3] */ 2036 P7_3_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:0 */ 2037 P7_3_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:0 */ 2038 2039 /* P7.4 */ 2040 P7_4_GPIO = 0, /* GPIO controls 'out' */ 2041 P7_4_AMUXA = 4, /* Analog mux bus A */ 2042 P7_4_AMUXB = 5, /* Analog mux bus B */ 2043 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2044 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2045 P7_4_TCPWM1_LINE262 = 8, /* Digital Active - tcpwm[1].line[262]:0 */ 2046 P7_4_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 2047 P7_4_TCPWM1_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[786]:0 */ 2048 P7_4_TCPWM1_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[49]:0 */ 2049 P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ 2050 P7_4_CANFD0_TTCAN_RX4 = 21, /* Digital Active - canfd[0].ttcan_rx[4]:0 */ 2051 P7_4_TCPWM0_TR_ONE_CNT_IN4 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[4] */ 2052 P7_4_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:0 */ 2053 P7_4_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:0 */ 2054 2055 /* P7.5 */ 2056 P7_5_GPIO = 0, /* GPIO controls 'out' */ 2057 P7_5_AMUXA = 4, /* Analog mux bus A */ 2058 P7_5_AMUXB = 5, /* Analog mux bus B */ 2059 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2060 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2061 P7_5_TCPWM1_LINE17 = 8, /* Digital Active - tcpwm[1].line[17]:0 */ 2062 P7_5_TCPWM1_LINE_COMPL262 = 9, /* Digital Active - tcpwm[1].line_compl[262]:0 */ 2063 P7_5_TCPWM1_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[51]:0 */ 2064 P7_5_TCPWM1_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[787]:0 */ 2065 P7_5_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:0 */ 2066 P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ 2067 P7_5_TCPWM0_LINE514 = 22, /* Digital Active - tcpwm[0].line[514] */ 2068 P7_5_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:0 */ 2069 P7_5_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:0 */ 2070 2071 /* P7.6 */ 2072 P7_6_GPIO = 0, /* GPIO controls 'out' */ 2073 P7_6_AMUXA = 4, /* Analog mux bus A */ 2074 P7_6_AMUXB = 5, /* Analog mux bus B */ 2075 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2076 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2077 P7_6_TCPWM1_LINE263 = 8, /* Digital Active - tcpwm[1].line[263]:0 */ 2078 P7_6_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 2079 P7_6_TCPWM1_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[789]:0 */ 2080 P7_6_TCPWM1_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[52]:0 */ 2081 P7_6_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:0 */ 2082 P7_6_PERI_TR_IO_INPUT16 = 26, /* Digital Active - peri.tr_io_input[16]:0 */ 2083 2084 /* P7.7 */ 2085 P7_7_GPIO = 0, /* GPIO controls 'out' */ 2086 P7_7_AMUXA = 4, /* Analog mux bus A */ 2087 P7_7_AMUXB = 5, /* Analog mux bus B */ 2088 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2089 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2090 P7_7_TCPWM1_LINE18 = 8, /* Digital Active - tcpwm[1].line[18]:0 */ 2091 P7_7_TCPWM1_LINE_COMPL263 = 9, /* Digital Active - tcpwm[1].line_compl[263]:0 */ 2092 P7_7_TCPWM1_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[54]:0 */ 2093 P7_7_TCPWM1_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[790]:0 */ 2094 P7_7_LIN0_LIN_EN10 = 18, /* Digital Active - lin[0].lin_en[10]:0 */ 2095 P7_7_PERI_TR_IO_INPUT17 = 26, /* Digital Active - peri.tr_io_input[17]:0 */ 2096 2097 /* P8.0 */ 2098 P8_0_GPIO = 0, /* GPIO controls 'out' */ 2099 P8_0_AMUXA = 4, /* Analog mux bus A */ 2100 P8_0_AMUXB = 5, /* Analog mux bus B */ 2101 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2102 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2103 P8_0_TCPWM1_LINE19 = 8, /* Digital Active - tcpwm[1].line[19]:0 */ 2104 P8_0_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ 2105 P8_0_TCPWM1_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[57]:0 */ 2106 P8_0_TCPWM1_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[55]:0 */ 2107 P8_0_TCPWM1_LINE520 = 16, /* Digital Active - tcpwm[1].line[520]:1 */ 2108 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 2109 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 2110 P8_0_TCPWM0_LINE_COMPL514 = 22, /* Digital Active - tcpwm[0].line_compl[514] */ 2111 P8_0_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:0 */ 2112 P8_0_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:0 */ 2113 2114 /* P8.1 */ 2115 P8_1_GPIO = 0, /* GPIO controls 'out' */ 2116 P8_1_AMUXA = 4, /* Analog mux bus A */ 2117 P8_1_AMUXB = 5, /* Analog mux bus B */ 2118 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2119 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2120 P8_1_TCPWM1_LINE20 = 8, /* Digital Active - tcpwm[1].line[20]:0 */ 2121 P8_1_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ 2122 P8_1_TCPWM1_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[60]:0 */ 2123 P8_1_TCPWM1_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[58]:0 */ 2124 P8_1_TCPWM1_LINE_COMPL520 = 16, /* Digital Active - tcpwm[1].line_compl[520]:1 */ 2125 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 2126 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 2127 P8_1_TCPWM0_TR_ONE_CNT_IN1542 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1542] */ 2128 P8_1_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:0 */ 2129 P8_1_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:0 */ 2130 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 2131 2132 /* P8.2 */ 2133 P8_2_GPIO = 0, /* GPIO controls 'out' */ 2134 P8_2_AMUXA = 4, /* Analog mux bus A */ 2135 P8_2_AMUXB = 5, /* Analog mux bus B */ 2136 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2137 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2138 P8_2_TCPWM1_LINE21 = 8, /* Digital Active - tcpwm[1].line[21]:0 */ 2139 P8_2_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 2140 P8_2_TCPWM1_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[63]:0 */ 2141 P8_2_TCPWM1_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[61]:0 */ 2142 P8_2_TCPWM1_TR_ONE_CNT_IN1560 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1560]:1 */ 2143 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 2144 P8_2_TCPWM0_TR_ONE_CNT_IN1543 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1543] */ 2145 P8_2_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:0 */ 2146 P8_2_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:0 */ 2147 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 2148 2149 /* P8.3 */ 2150 P8_3_GPIO = 0, /* GPIO controls 'out' */ 2151 P8_3_AMUXA = 4, /* Analog mux bus A */ 2152 P8_3_AMUXB = 5, /* Analog mux bus B */ 2153 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2154 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2155 P8_3_TCPWM1_LINE22 = 8, /* Digital Active - tcpwm[1].line[22]:0 */ 2156 P8_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 2157 P8_3_TCPWM1_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[66]:0 */ 2158 P8_3_TCPWM1_TR_ONE_CNT_IN64 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[64]:0 */ 2159 P8_3_TCPWM1_TR_ONE_CNT_IN1561 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1561]:1 */ 2160 P8_3_LIN0_LIN_RX16 = 20, /* Digital Active - lin[0].lin_rx[16]:1 */ 2161 P8_3_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:1 */ 2162 2163 /* P8.4 */ 2164 P8_4_GPIO = 0, /* GPIO controls 'out' */ 2165 P8_4_AMUXA = 4, /* Analog mux bus A */ 2166 P8_4_AMUXB = 5, /* Analog mux bus B */ 2167 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2168 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2169 P8_4_TCPWM1_LINE23 = 8, /* Digital Active - tcpwm[1].line[23]:0 */ 2170 P8_4_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 2171 P8_4_TCPWM1_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[69]:0 */ 2172 P8_4_TCPWM1_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[67]:0 */ 2173 P8_4_LIN0_LIN_TX16 = 20, /* Digital Active - lin[0].lin_tx[16]:1 */ 2174 P8_4_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:1 */ 2175 2176 /* P9.0 */ 2177 P9_0_GPIO = 0, /* GPIO controls 'out' */ 2178 P9_0_AMUXA = 4, /* Analog mux bus A */ 2179 P9_0_AMUXB = 5, /* Analog mux bus B */ 2180 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2181 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2182 P9_0_TCPWM1_LINE24 = 8, /* Digital Active - tcpwm[1].line[24]:0 */ 2183 P9_0_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 2184 P9_0_TCPWM1_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[72]:0 */ 2185 P9_0_TCPWM1_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[70]:0 */ 2186 P9_0_TCPWM1_LINE521 = 16, /* Digital Active - tcpwm[1].line[521]:1 */ 2187 P9_0_LIN0_LIN_EN16 = 20, /* Digital Active - lin[0].lin_en[16]:1 */ 2188 2189 /* P9.1 */ 2190 P9_1_GPIO = 0, /* GPIO controls 'out' */ 2191 P9_1_AMUXA = 4, /* Analog mux bus A */ 2192 P9_1_AMUXB = 5, /* Analog mux bus B */ 2193 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2194 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2195 P9_1_TCPWM1_LINE25 = 8, /* Digital Active - tcpwm[1].line[25]:0 */ 2196 P9_1_TCPWM1_LINE_COMPL24 = 9, /* Digital Active - tcpwm[1].line_compl[24]:0 */ 2197 P9_1_TCPWM1_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[75]:0 */ 2198 P9_1_TCPWM1_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[73]:0 */ 2199 P9_1_TCPWM1_LINE_COMPL521 = 16, /* Digital Active - tcpwm[1].line_compl[521]:1 */ 2200 P9_1_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:0 */ 2201 2202 /* P9.2 */ 2203 P9_2_GPIO = 0, /* GPIO controls 'out' */ 2204 P9_2_AMUXA = 4, /* Analog mux bus A */ 2205 P9_2_AMUXB = 5, /* Analog mux bus B */ 2206 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2207 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2208 P9_2_TCPWM1_LINE26 = 8, /* Digital Active - tcpwm[1].line[26]:0 */ 2209 P9_2_TCPWM1_LINE_COMPL25 = 9, /* Digital Active - tcpwm[1].line_compl[25]:0 */ 2210 P9_2_TCPWM1_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[78]:0 */ 2211 P9_2_TCPWM1_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[76]:0 */ 2212 P9_2_TCPWM1_TR_ONE_CNT_IN1563 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1563]:1 */ 2213 P9_2_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:0 */ 2214 2215 /* P9.3 */ 2216 P9_3_GPIO = 0, /* GPIO controls 'out' */ 2217 P9_3_AMUXA = 4, /* Analog mux bus A */ 2218 P9_3_AMUXB = 5, /* Analog mux bus B */ 2219 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2220 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2221 P9_3_TCPWM1_LINE27 = 8, /* Digital Active - tcpwm[1].line[27]:0 */ 2222 P9_3_TCPWM1_LINE_COMPL26 = 9, /* Digital Active - tcpwm[1].line_compl[26]:0 */ 2223 P9_3_TCPWM1_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[81]:0 */ 2224 P9_3_TCPWM1_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[79]:0 */ 2225 P9_3_TCPWM1_TR_ONE_CNT_IN1564 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1564]:1 */ 2226 P9_3_LIN0_LIN_EN12 = 21, /* Digital Active - lin[0].lin_en[12]:0 */ 2227 2228 /* P10.0 */ 2229 P10_0_GPIO = 0, /* GPIO controls 'out' */ 2230 P10_0_AMUXA = 4, /* Analog mux bus A */ 2231 P10_0_AMUXB = 5, /* Analog mux bus B */ 2232 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2233 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2234 P10_0_TCPWM1_LINE28 = 8, /* Digital Active - tcpwm[1].line[28]:0 */ 2235 P10_0_TCPWM1_LINE_COMPL27 = 9, /* Digital Active - tcpwm[1].line_compl[27]:0 */ 2236 P10_0_TCPWM1_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[84]:0 */ 2237 P10_0_TCPWM1_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[82]:0 */ 2238 P10_0_TCPWM1_LINE522 = 16, /* Digital Active - tcpwm[1].line[522]:1 */ 2239 P10_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:1 */ 2240 P10_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:1 */ 2241 P10_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:2 */ 2242 P10_0_PERI_TR_IO_INPUT18 = 26, /* Digital Active - peri.tr_io_input[18]:0 */ 2243 2244 /* P10.1 */ 2245 P10_1_GPIO = 0, /* GPIO controls 'out' */ 2246 P10_1_AMUXA = 4, /* Analog mux bus A */ 2247 P10_1_AMUXB = 5, /* Analog mux bus B */ 2248 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2249 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2250 P10_1_TCPWM1_LINE29 = 8, /* Digital Active - tcpwm[1].line[29]:0 */ 2251 P10_1_TCPWM1_LINE_COMPL28 = 9, /* Digital Active - tcpwm[1].line_compl[28]:0 */ 2252 P10_1_TCPWM1_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[87]:0 */ 2253 P10_1_TCPWM1_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[85]:0 */ 2254 P10_1_TCPWM1_LINE_COMPL522 = 16, /* Digital Active - tcpwm[1].line_compl[522]:1 */ 2255 P10_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:1 */ 2256 P10_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:1 */ 2257 P10_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:1 */ 2258 P10_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:2 */ 2259 P10_1_PERI_TR_IO_INPUT19 = 26, /* Digital Active - peri.tr_io_input[19]:0 */ 2260 2261 /* P10.2 */ 2262 P10_2_GPIO = 0, /* GPIO controls 'out' */ 2263 P10_2_AMUXA = 4, /* Analog mux bus A */ 2264 P10_2_AMUXB = 5, /* Analog mux bus B */ 2265 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2266 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2267 P10_2_TCPWM1_LINE30 = 8, /* Digital Active - tcpwm[1].line[30]:0 */ 2268 P10_2_TCPWM1_LINE_COMPL29 = 9, /* Digital Active - tcpwm[1].line_compl[29]:0 */ 2269 P10_2_TCPWM1_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[90]:0 */ 2270 P10_2_TCPWM1_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[88]:0 */ 2271 P10_2_TCPWM1_TR_ONE_CNT_IN1566 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1566]:1 */ 2272 P10_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:1 */ 2273 P10_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:1 */ 2274 P10_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:1 */ 2275 P10_2_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:1 */ 2276 P10_2_FLEXRAY0_RXDA = 26, /* Digital Active - flexray[0].rxda:0 */ 2277 2278 /* P10.3 */ 2279 P10_3_GPIO = 0, /* GPIO controls 'out' */ 2280 P10_3_AMUXA = 4, /* Analog mux bus A */ 2281 P10_3_AMUXB = 5, /* Analog mux bus B */ 2282 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2283 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2284 P10_3_TCPWM1_LINE31 = 8, /* Digital Active - tcpwm[1].line[31]:0 */ 2285 P10_3_TCPWM1_LINE_COMPL30 = 9, /* Digital Active - tcpwm[1].line_compl[30]:0 */ 2286 P10_3_TCPWM1_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[93]:0 */ 2287 P10_3_TCPWM1_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[91]:0 */ 2288 P10_3_TCPWM1_TR_ONE_CNT_IN1567 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1567]:1 */ 2289 P10_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:1 */ 2290 P10_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:1 */ 2291 P10_3_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:1 */ 2292 P10_3_FLEXRAY0_TXDA = 26, /* Digital Active - flexray[0].txda:0 */ 2293 2294 /* P10.4 */ 2295 P10_4_GPIO = 0, /* GPIO controls 'out' */ 2296 P10_4_AMUXA = 4, /* Analog mux bus A */ 2297 P10_4_AMUXB = 5, /* Analog mux bus B */ 2298 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2299 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2300 P10_4_TCPWM1_LINE32 = 8, /* Digital Active - tcpwm[1].line[32]:0 */ 2301 P10_4_TCPWM1_LINE_COMPL31 = 9, /* Digital Active - tcpwm[1].line_compl[31]:0 */ 2302 P10_4_TCPWM1_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[96]:0 */ 2303 P10_4_TCPWM1_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[94]:0 */ 2304 P10_4_TCPWM1_LINE523 = 16, /* Digital Active - tcpwm[1].line[523]:1 */ 2305 P10_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:1 */ 2306 P10_4_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:1 */ 2307 P10_4_FLEXRAY0_TXENA_N = 26, /* Digital Active - flexray[0].txena_n:0 */ 2308 2309 /* P10.5 */ 2310 P10_5_GPIO = 0, /* GPIO controls 'out' */ 2311 P10_5_AMUXA = 4, /* Analog mux bus A */ 2312 P10_5_AMUXB = 5, /* Analog mux bus B */ 2313 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2314 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2315 P10_5_TCPWM1_LINE33 = 8, /* Digital Active - tcpwm[1].line[33]:0 */ 2316 P10_5_TCPWM1_LINE_COMPL32 = 9, /* Digital Active - tcpwm[1].line_compl[32]:0 */ 2317 P10_5_TCPWM1_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[99]:0 */ 2318 P10_5_TCPWM1_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[97]:0 */ 2319 P10_5_TCPWM1_LINE_COMPL523 = 16, /* Digital Active - tcpwm[1].line_compl[523]:1 */ 2320 P10_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:1 */ 2321 P10_5_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:0 */ 2322 P10_5_FLEXRAY0_RXDB = 26, /* Digital Active - flexray[0].rxdb:0 */ 2323 2324 /* P10.6 */ 2325 P10_6_GPIO = 0, /* GPIO controls 'out' */ 2326 P10_6_AMUXA = 4, /* Analog mux bus A */ 2327 P10_6_AMUXB = 5, /* Analog mux bus B */ 2328 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2329 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2330 P10_6_TCPWM1_LINE_COMPL33 = 9, /* Digital Active - tcpwm[1].line_compl[33]:0 */ 2331 P10_6_TCPWM1_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[100]:0 */ 2332 P10_6_TCPWM1_TR_ONE_CNT_IN1569 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1569]:1 */ 2333 P10_6_TCPWM1_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[1].tr_one_cnt_in[102]:0 */ 2334 P10_6_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:0 */ 2335 P10_6_TCPWM1_LINE34 = 22, /* Digital Active - tcpwm[1].line[34]:0 */ 2336 P10_6_FLEXRAY0_TXDB = 26, /* Digital Active - flexray[0].txdb:0 */ 2337 2338 /* P10.7 */ 2339 P10_7_GPIO = 0, /* GPIO controls 'out' */ 2340 P10_7_AMUXA = 4, /* Analog mux bus A */ 2341 P10_7_AMUXB = 5, /* Analog mux bus B */ 2342 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2343 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2344 P10_7_TCPWM1_LINE35 = 8, /* Digital Active - tcpwm[1].line[35]:0 */ 2345 P10_7_TCPWM1_LINE_COMPL34 = 9, /* Digital Active - tcpwm[1].line_compl[34]:0 */ 2346 P10_7_TCPWM1_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[105]:0 */ 2347 P10_7_TCPWM1_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[103]:0 */ 2348 P10_7_TCPWM1_TR_ONE_CNT_IN1570 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1570]:1 */ 2349 P10_7_LIN0_LIN_EN13 = 21, /* Digital Active - lin[0].lin_en[13]:0 */ 2350 P10_7_FLEXRAY0_TXENB_N = 26, /* Digital Active - flexray[0].txenb_n:0 */ 2351 2352 /* P11.0 */ 2353 P11_0_GPIO = 0, /* GPIO controls 'out' */ 2354 P11_0_AMUXA = 4, /* Analog mux bus A */ 2355 P11_0_AMUXB = 5, /* Analog mux bus B */ 2356 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2357 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2358 P11_0_TCPWM1_LINE61 = 8, /* Digital Active - tcpwm[1].line[61]:2 */ 2359 P11_0_TCPWM1_LINE_COMPL62 = 9, /* Digital Active - tcpwm[1].line_compl[62]:2 */ 2360 P11_0_TCPWM1_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[183]:2 */ 2361 P11_0_TCPWM1_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[187]:2 */ 2362 P11_0_AUDIOSS0_MCLK = 25, /* Digital Active - audioss[0].mclk:0 */ 2363 2364 /* P11.1 */ 2365 P11_1_GPIO = 0, /* GPIO controls 'out' */ 2366 P11_1_AMUXA = 4, /* Analog mux bus A */ 2367 P11_1_AMUXB = 5, /* Analog mux bus B */ 2368 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2369 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2370 P11_1_TCPWM1_LINE60 = 8, /* Digital Active - tcpwm[1].line[60]:2 */ 2371 P11_1_TCPWM1_LINE_COMPL61 = 9, /* Digital Active - tcpwm[1].line_compl[61]:2 */ 2372 P11_1_TCPWM1_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[180]:2 */ 2373 P11_1_TCPWM1_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[184]:2 */ 2374 P11_1_AUDIOSS0_TX_SCK = 25, /* Digital Active - audioss[0].tx_sck:0 */ 2375 2376 /* P11.2 */ 2377 P11_2_GPIO = 0, /* GPIO controls 'out' */ 2378 P11_2_AMUXA = 4, /* Analog mux bus A */ 2379 P11_2_AMUXB = 5, /* Analog mux bus B */ 2380 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2381 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2382 P11_2_TCPWM1_LINE59 = 8, /* Digital Active - tcpwm[1].line[59]:2 */ 2383 P11_2_TCPWM1_LINE_COMPL60 = 9, /* Digital Active - tcpwm[1].line_compl[60]:2 */ 2384 P11_2_TCPWM1_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[177]:2 */ 2385 P11_2_TCPWM1_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[181]:2 */ 2386 P11_2_AUDIOSS0_TX_WS = 25, /* Digital Active - audioss[0].tx_ws:0 */ 2387 2388 /* P12.0 */ 2389 P12_0_GPIO = 0, /* GPIO controls 'out' */ 2390 P12_0_AMUXA = 4, /* Analog mux bus A */ 2391 P12_0_AMUXB = 5, /* Analog mux bus B */ 2392 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2393 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2394 P12_0_TCPWM1_LINE36 = 8, /* Digital Active - tcpwm[1].line[36]:0 */ 2395 P12_0_TCPWM1_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[108]:0 */ 2396 P12_0_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:0 */ 2397 P12_0_TCPWM1_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[1].tr_one_cnt_in[106]:0 */ 2398 P12_0_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:0 */ 2399 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 2400 P12_0_TCPWM0_LINE513 = 22, /* Digital Active - tcpwm[0].line[513] */ 2401 P12_0_TCPWM1_LINE_COMPL35 = 23, /* Digital Active - tcpwm[1].line_compl[35]:0 */ 2402 P12_0_AUDIOSS0_TX_SDO = 25, /* Digital Active - audioss[0].tx_sdo:0 */ 2403 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 2404 2405 /* P12.1 */ 2406 P12_1_GPIO = 0, /* GPIO controls 'out' */ 2407 P12_1_AMUXA = 4, /* Analog mux bus A */ 2408 P12_1_AMUXB = 5, /* Analog mux bus B */ 2409 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2410 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2411 P12_1_TCPWM1_LINE37 = 8, /* Digital Active - tcpwm[1].line[37]:0 */ 2412 P12_1_TCPWM1_LINE_COMPL36 = 9, /* Digital Active - tcpwm[1].line_compl[36]:0 */ 2413 P12_1_TCPWM1_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[111]:0 */ 2414 P12_1_TCPWM1_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[109]:0 */ 2415 P12_1_SCB8_UART_TX = 17, /* Digital Active - scb[8].uart_tx:0 */ 2416 P12_1_SCB8_I2C_SDA = 18, /* Digital Active - scb[8].i2c_sda:0 */ 2417 P12_1_SCB8_SPI_MOSI = 19, /* Digital Active - scb[8].spi_mosi:0 */ 2418 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 2419 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 2420 P12_1_TCPWM0_LINE_COMPL513 = 22, /* Digital Active - tcpwm[0].line_compl[513] */ 2421 P12_1_AUDIOSS0_CLK_I2S_IF = 25, /* Digital Active - audioss[0].clk_i2s_if:0 */ 2422 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 2423 2424 /* P12.2 */ 2425 P12_2_GPIO = 0, /* GPIO controls 'out' */ 2426 P12_2_AMUXA = 4, /* Analog mux bus A */ 2427 P12_2_AMUXB = 5, /* Analog mux bus B */ 2428 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2429 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2430 P12_2_TCPWM1_LINE38 = 8, /* Digital Active - tcpwm[1].line[38]:0 */ 2431 P12_2_TCPWM1_LINE_COMPL37 = 9, /* Digital Active - tcpwm[1].line_compl[37]:0 */ 2432 P12_2_TCPWM1_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[114]:0 */ 2433 P12_2_TCPWM1_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[112]:0 */ 2434 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 2435 P12_2_SCB8_UART_RTS = 17, /* Digital Active - scb[8].uart_rts:0 */ 2436 P12_2_SCB8_I2C_SCL = 18, /* Digital Active - scb[8].i2c_scl:0 */ 2437 P12_2_SCB8_SPI_CLK = 19, /* Digital Active - scb[8].spi_clk:0 */ 2438 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 2439 P12_2_TCPWM0_TR_ONE_CNT_IN1539 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539] */ 2440 P12_2_AUDIOSS0_RX_SCK = 25, /* Digital Active - audioss[0].rx_sck:0 */ 2441 2442 /* P12.3 */ 2443 P12_3_GPIO = 0, /* GPIO controls 'out' */ 2444 P12_3_AMUXA = 4, /* Analog mux bus A */ 2445 P12_3_AMUXB = 5, /* Analog mux bus B */ 2446 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2447 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2448 P12_3_TCPWM1_LINE39 = 8, /* Digital Active - tcpwm[1].line[39]:0 */ 2449 P12_3_TCPWM1_LINE_COMPL38 = 9, /* Digital Active - tcpwm[1].line_compl[38]:0 */ 2450 P12_3_TCPWM1_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[117]:0 */ 2451 P12_3_TCPWM1_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[115]:0 */ 2452 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 2453 P12_3_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:0 */ 2454 P12_3_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:0 */ 2455 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 2456 P12_3_TCPWM0_TR_ONE_CNT_IN1540 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540] */ 2457 P12_3_AUDIOSS0_RX_WS = 25, /* Digital Active - audioss[0].rx_ws:0 */ 2458 2459 /* P12.4 */ 2460 P12_4_GPIO = 0, /* GPIO controls 'out' */ 2461 P12_4_AMUXA = 4, /* Analog mux bus A */ 2462 P12_4_AMUXB = 5, /* Analog mux bus B */ 2463 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2464 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2465 P12_4_TCPWM1_LINE40 = 8, /* Digital Active - tcpwm[1].line[40]:0 */ 2466 P12_4_TCPWM1_LINE_COMPL39 = 9, /* Digital Active - tcpwm[1].line_compl[39]:0 */ 2467 P12_4_TCPWM1_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[120]:0 */ 2468 P12_4_TCPWM1_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[118]:0 */ 2469 P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 2470 P12_4_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:0 */ 2471 P12_4_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:2 */ 2472 P12_4_TCPWM0_TR_ONE_CNT_IN7 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[7] */ 2473 P12_4_AUDIOSS0_RX_SDI = 25, /* Digital Active - audioss[0].rx_sdi:0 */ 2474 2475 /* P12.5 */ 2476 P12_5_GPIO = 0, /* GPIO controls 'out' */ 2477 P12_5_AMUXA = 4, /* Analog mux bus A */ 2478 P12_5_AMUXB = 5, /* Analog mux bus B */ 2479 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2480 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2481 P12_5_TCPWM1_LINE41 = 8, /* Digital Active - tcpwm[1].line[41]:0 */ 2482 P12_5_TCPWM1_LINE_COMPL40 = 9, /* Digital Active - tcpwm[1].line_compl[40]:0 */ 2483 P12_5_TCPWM1_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[123]:0 */ 2484 P12_5_TCPWM1_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[121]:0 */ 2485 P12_5_PASS0_SAR_EXT_MUX_SEL5 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[5] */ 2486 P12_5_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:2 */ 2487 2488 /* P12.6 */ 2489 P12_6_GPIO = 0, /* GPIO controls 'out' */ 2490 P12_6_AMUXA = 4, /* Analog mux bus A */ 2491 P12_6_AMUXB = 5, /* Analog mux bus B */ 2492 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2493 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2494 P12_6_TCPWM1_LINE42 = 8, /* Digital Active - tcpwm[1].line[42]:0 */ 2495 P12_6_TCPWM1_LINE_COMPL41 = 9, /* Digital Active - tcpwm[1].line_compl[41]:0 */ 2496 P12_6_TCPWM1_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[126]:0 */ 2497 P12_6_TCPWM1_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[124]:0 */ 2498 2499 /* P12.7 */ 2500 P12_7_GPIO = 0, /* GPIO controls 'out' */ 2501 P12_7_AMUXA = 4, /* Analog mux bus A */ 2502 P12_7_AMUXB = 5, /* Analog mux bus B */ 2503 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2504 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2505 P12_7_TCPWM1_LINE43 = 8, /* Digital Active - tcpwm[1].line[43]:0 */ 2506 P12_7_TCPWM1_LINE_COMPL42 = 9, /* Digital Active - tcpwm[1].line_compl[42]:0 */ 2507 P12_7_TCPWM1_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[129]:0 */ 2508 P12_7_TCPWM1_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[127]:0 */ 2509 2510 /* P13.0 */ 2511 P13_0_GPIO = 0, /* GPIO controls 'out' */ 2512 P13_0_AMUXA = 4, /* Analog mux bus A */ 2513 P13_0_AMUXB = 5, /* Analog mux bus B */ 2514 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2515 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2516 P13_0_TCPWM1_LINE264 = 8, /* Digital Active - tcpwm[1].line[264]:0 */ 2517 P13_0_TCPWM1_LINE_COMPL43 = 9, /* Digital Active - tcpwm[1].line_compl[43]:0 */ 2518 P13_0_TCPWM1_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[792]:0 */ 2519 P13_0_TCPWM1_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[130]:0 */ 2520 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 2521 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 2522 P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ 2523 P13_0_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:0 */ 2524 P13_0_TCPWM0_TR_ONE_CNT_IN6 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[6] */ 2525 P13_0_AUDIOSS1_MCLK = 25, /* Digital Active - audioss[1].mclk:0 */ 2526 2527 /* P13.1 */ 2528 P13_1_GPIO = 0, /* GPIO controls 'out' */ 2529 P13_1_AMUXA = 4, /* Analog mux bus A */ 2530 P13_1_AMUXB = 5, /* Analog mux bus B */ 2531 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2532 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2533 P13_1_TCPWM1_LINE44 = 8, /* Digital Active - tcpwm[1].line[44]:0 */ 2534 P13_1_TCPWM1_LINE_COMPL264 = 9, /* Digital Active - tcpwm[1].line_compl[264]:0 */ 2535 P13_1_TCPWM1_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[132]:0 */ 2536 P13_1_TCPWM1_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[793]:0 */ 2537 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 2538 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 2539 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 2540 P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ 2541 P13_1_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:0 */ 2542 P13_1_TCPWM0_LINE_COMPL2 = 22, /* Digital Active - tcpwm[0].line_compl[2] */ 2543 P13_1_AUDIOSS1_TX_SCK = 25, /* Digital Active - audioss[1].tx_sck:0 */ 2544 2545 /* P13.2 */ 2546 P13_2_GPIO = 0, /* GPIO controls 'out' */ 2547 P13_2_AMUXA = 4, /* Analog mux bus A */ 2548 P13_2_AMUXB = 5, /* Analog mux bus B */ 2549 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2550 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2551 P13_2_TCPWM1_LINE265 = 8, /* Digital Active - tcpwm[1].line[265]:0 */ 2552 P13_2_TCPWM1_LINE_COMPL44 = 9, /* Digital Active - tcpwm[1].line_compl[44]:0 */ 2553 P13_2_TCPWM1_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[795]:0 */ 2554 P13_2_TCPWM1_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[133]:0 */ 2555 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 2556 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 2557 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 2558 P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ 2559 P13_2_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:0 */ 2560 P13_2_TCPWM0_LINE2 = 22, /* Digital Active - tcpwm[0].line[2] */ 2561 P13_2_AUDIOSS1_TX_WS = 25, /* Digital Active - audioss[1].tx_ws:0 */ 2562 2563 /* P13.3 */ 2564 P13_3_GPIO = 0, /* GPIO controls 'out' */ 2565 P13_3_AMUXA = 4, /* Analog mux bus A */ 2566 P13_3_AMUXB = 5, /* Analog mux bus B */ 2567 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2568 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2569 P13_3_TCPWM1_LINE45 = 8, /* Digital Active - tcpwm[1].line[45]:0 */ 2570 P13_3_TCPWM1_LINE_COMPL265 = 9, /* Digital Active - tcpwm[1].line_compl[265]:0 */ 2571 P13_3_TCPWM1_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[135]:0 */ 2572 P13_3_TCPWM1_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[796]:0 */ 2573 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 2574 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 2575 P13_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:2 */ 2576 P13_3_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:0 */ 2577 P13_3_AUDIOSS1_TX_SDO = 25, /* Digital Active - audioss[1].tx_sdo:0 */ 2578 2579 /* P13.4 */ 2580 P13_4_GPIO = 0, /* GPIO controls 'out' */ 2581 P13_4_AMUXA = 4, /* Analog mux bus A */ 2582 P13_4_AMUXB = 5, /* Analog mux bus B */ 2583 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2584 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2585 P13_4_TCPWM1_LINE266 = 8, /* Digital Active - tcpwm[1].line[266]:0 */ 2586 P13_4_TCPWM1_LINE_COMPL45 = 9, /* Digital Active - tcpwm[1].line_compl[45]:0 */ 2587 P13_4_TCPWM1_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[798]:0 */ 2588 P13_4_TCPWM1_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[136]:0 */ 2589 P13_4_TCPWM1_LINE516 = 16, /* Digital Active - tcpwm[1].line[516]:1 */ 2590 P13_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:2 */ 2591 P13_4_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:0 */ 2592 P13_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:0 */ 2593 P13_4_AUDIOSS1_CLK_I2S_IF = 25, /* Digital Active - audioss[1].clk_i2s_if:0 */ 2594 2595 /* P13.5 */ 2596 P13_5_GPIO = 0, /* GPIO controls 'out' */ 2597 P13_5_AMUXA = 4, /* Analog mux bus A */ 2598 P13_5_AMUXB = 5, /* Analog mux bus B */ 2599 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2600 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2601 P13_5_TCPWM1_LINE46 = 8, /* Digital Active - tcpwm[1].line[46]:0 */ 2602 P13_5_TCPWM1_LINE_COMPL266 = 9, /* Digital Active - tcpwm[1].line_compl[266]:0 */ 2603 P13_5_TCPWM1_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[138]:0 */ 2604 P13_5_TCPWM1_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[799]:0 */ 2605 P13_5_TCPWM1_LINE_COMPL516 = 16, /* Digital Active - tcpwm[1].line_compl[516]:1 */ 2606 P13_5_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:0 */ 2607 P13_5_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:0 */ 2608 P13_5_AUDIOSS1_RX_SCK = 25, /* Digital Active - audioss[1].rx_sck:0 */ 2609 2610 /* P13.6 */ 2611 P13_6_GPIO = 0, /* GPIO controls 'out' */ 2612 P13_6_AMUXA = 4, /* Analog mux bus A */ 2613 P13_6_AMUXB = 5, /* Analog mux bus B */ 2614 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2615 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2616 P13_6_TCPWM1_LINE267 = 8, /* Digital Active - tcpwm[1].line[267]:0 */ 2617 P13_6_TCPWM1_LINE_COMPL46 = 9, /* Digital Active - tcpwm[1].line_compl[46]:0 */ 2618 P13_6_TCPWM1_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[801]:0 */ 2619 P13_6_TCPWM1_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[139]:0 */ 2620 P13_6_TCPWM1_LINE517 = 16, /* Digital Active - tcpwm[1].line[517]:1 */ 2621 P13_6_SCB3_SPI_SELECT3 = 21, /* Digital Active - scb[3].spi_select3:0 */ 2622 P13_6_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:0 */ 2623 P13_6_AUDIOSS1_RX_WS = 25, /* Digital Active - audioss[1].rx_ws:0 */ 2624 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 2625 2626 /* P13.7 */ 2627 P13_7_GPIO = 0, /* GPIO controls 'out' */ 2628 P13_7_AMUXA = 4, /* Analog mux bus A */ 2629 P13_7_AMUXB = 5, /* Analog mux bus B */ 2630 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2631 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2632 P13_7_TCPWM1_LINE47 = 8, /* Digital Active - tcpwm[1].line[47]:0 */ 2633 P13_7_TCPWM1_LINE_COMPL267 = 9, /* Digital Active - tcpwm[1].line_compl[267]:0 */ 2634 P13_7_TCPWM1_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[141]:0 */ 2635 P13_7_TCPWM1_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[802]:0 */ 2636 P13_7_TCPWM1_LINE_COMPL517 = 16, /* Digital Active - tcpwm[1].line_compl[517]:1 */ 2637 P13_7_AUDIOSS1_RX_SDI = 25, /* Digital Active - audioss[1].rx_sdi:0 */ 2638 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 2639 2640 /* P14.0 */ 2641 P14_0_GPIO = 0, /* GPIO controls 'out' */ 2642 P14_0_AMUXA = 4, /* Analog mux bus A */ 2643 P14_0_AMUXB = 5, /* Analog mux bus B */ 2644 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2645 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2646 P14_0_TCPWM1_LINE48 = 8, /* Digital Active - tcpwm[1].line[48]:0 */ 2647 P14_0_TCPWM1_LINE_COMPL47 = 9, /* Digital Active - tcpwm[1].line_compl[47]:0 */ 2648 P14_0_TCPWM1_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[144]:0 */ 2649 P14_0_TCPWM1_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[142]:0 */ 2650 P14_0_TCPWM1_LINE518 = 16, /* Digital Active - tcpwm[1].line[518]:1 */ 2651 P14_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:0 */ 2652 P14_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:0 */ 2653 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 2654 P14_0_TCPWM0_LINE257 = 22, /* Digital Active - tcpwm[0].line[257] */ 2655 P14_0_AUDIOSS2_MCLK = 25, /* Digital Active - audioss[2].mclk:0 */ 2656 2657 /* P14.1 */ 2658 P14_1_GPIO = 0, /* GPIO controls 'out' */ 2659 P14_1_AMUXA = 4, /* Analog mux bus A */ 2660 P14_1_AMUXB = 5, /* Analog mux bus B */ 2661 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2662 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2663 P14_1_TCPWM1_LINE49 = 8, /* Digital Active - tcpwm[1].line[49]:0 */ 2664 P14_1_TCPWM1_LINE_COMPL48 = 9, /* Digital Active - tcpwm[1].line_compl[48]:0 */ 2665 P14_1_TCPWM1_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[147]:0 */ 2666 P14_1_TCPWM1_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[145]:0 */ 2667 P14_1_TCPWM1_LINE_COMPL518 = 16, /* Digital Active - tcpwm[1].line_compl[518]:1 */ 2668 P14_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:0 */ 2669 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 2670 P14_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:0 */ 2671 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 2672 P14_1_TCPWM0_LINE_COMPL257 = 22, /* Digital Active - tcpwm[0].line_compl[257] */ 2673 P14_1_AUDIOSS2_TX_SCK = 25, /* Digital Active - audioss[2].tx_sck:0 */ 2674 2675 /* P14.2 */ 2676 P14_2_GPIO = 0, /* GPIO controls 'out' */ 2677 P14_2_AMUXA = 4, /* Analog mux bus A */ 2678 P14_2_AMUXB = 5, /* Analog mux bus B */ 2679 P14_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2680 P14_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2681 P14_2_TCPWM1_LINE50 = 8, /* Digital Active - tcpwm[1].line[50]:0 */ 2682 P14_2_TCPWM1_LINE_COMPL49 = 9, /* Digital Active - tcpwm[1].line_compl[49]:0 */ 2683 P14_2_TCPWM1_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[150]:0 */ 2684 P14_2_TCPWM1_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[148]:0 */ 2685 P14_2_TCPWM1_LINE519 = 16, /* Digital Active - tcpwm[1].line[519]:1 */ 2686 P14_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:0 */ 2687 P14_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:0 */ 2688 P14_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:0 */ 2689 P14_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:1 */ 2690 P14_2_TCPWM0_TR_ONE_CNT_IN771 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[771] */ 2691 2692 /* P14.3 */ 2693 P14_3_GPIO = 0, /* GPIO controls 'out' */ 2694 P14_3_AMUXA = 4, /* Analog mux bus A */ 2695 P14_3_AMUXB = 5, /* Analog mux bus B */ 2696 P14_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2697 P14_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2698 P14_3_TCPWM1_LINE51 = 8, /* Digital Active - tcpwm[1].line[51]:0 */ 2699 P14_3_TCPWM1_LINE_COMPL50 = 9, /* Digital Active - tcpwm[1].line_compl[50]:0 */ 2700 P14_3_TCPWM1_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[153]:0 */ 2701 P14_3_TCPWM1_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[151]:0 */ 2702 P14_3_TCPWM1_LINE_COMPL519 = 16, /* Digital Active - tcpwm[1].line_compl[519]:1 */ 2703 P14_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:0 */ 2704 P14_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:0 */ 2705 P14_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:1 */ 2706 P14_3_TCPWM0_TR_ONE_CNT_IN772 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[772] */ 2707 2708 /* P14.4 */ 2709 P14_4_GPIO = 0, /* GPIO controls 'out' */ 2710 P14_4_AMUXA = 4, /* Analog mux bus A */ 2711 P14_4_AMUXB = 5, /* Analog mux bus B */ 2712 P14_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2713 P14_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2714 P14_4_TCPWM1_LINE52 = 8, /* Digital Active - tcpwm[1].line[52]:0 */ 2715 P14_4_TCPWM1_LINE_COMPL51 = 9, /* Digital Active - tcpwm[1].line_compl[51]:0 */ 2716 P14_4_TCPWM1_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[156]:0 */ 2717 P14_4_TCPWM1_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[154]:0 */ 2718 P14_4_TCPWM1_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1548]:1 */ 2719 P14_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:0 */ 2720 P14_4_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:1 */ 2721 P14_4_AUDIOSS2_TX_WS = 25, /* Digital Active - audioss[2].tx_ws:0 */ 2722 2723 /* P14.5 */ 2724 P14_5_GPIO = 0, /* GPIO controls 'out' */ 2725 P14_5_AMUXA = 4, /* Analog mux bus A */ 2726 P14_5_AMUXB = 5, /* Analog mux bus B */ 2727 P14_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2728 P14_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2729 P14_5_TCPWM1_LINE53 = 8, /* Digital Active - tcpwm[1].line[53]:0 */ 2730 P14_5_TCPWM1_LINE_COMPL52 = 9, /* Digital Active - tcpwm[1].line_compl[52]:0 */ 2731 P14_5_TCPWM1_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[159]:0 */ 2732 P14_5_TCPWM1_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[157]:0 */ 2733 P14_5_TCPWM1_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1549]:1 */ 2734 P14_5_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:0 */ 2735 P14_5_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:0 */ 2736 P14_5_AUDIOSS2_TX_SDO = 25, /* Digital Active - audioss[2].tx_sdo:0 */ 2737 2738 /* P14.6 */ 2739 P14_6_GPIO = 0, /* GPIO controls 'out' */ 2740 P14_6_AMUXA = 4, /* Analog mux bus A */ 2741 P14_6_AMUXB = 5, /* Analog mux bus B */ 2742 P14_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2743 P14_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2744 P14_6_TCPWM1_LINE54 = 8, /* Digital Active - tcpwm[1].line[54]:0 */ 2745 P14_6_TCPWM1_LINE_COMPL53 = 9, /* Digital Active - tcpwm[1].line_compl[53]:0 */ 2746 P14_6_TCPWM1_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[162]:0 */ 2747 P14_6_TCPWM1_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[160]:0 */ 2748 P14_6_TCPWM1_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1551]:1 */ 2749 P14_6_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:0 */ 2750 P14_6_PERI_TR_IO_INPUT24 = 26, /* Digital Active - peri.tr_io_input[24]:0 */ 2751 2752 /* P14.7 */ 2753 P14_7_GPIO = 0, /* GPIO controls 'out' */ 2754 P14_7_AMUXA = 4, /* Analog mux bus A */ 2755 P14_7_AMUXB = 5, /* Analog mux bus B */ 2756 P14_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2757 P14_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2758 P14_7_TCPWM1_LINE55 = 8, /* Digital Active - tcpwm[1].line[55]:0 */ 2759 P14_7_TCPWM1_LINE_COMPL54 = 9, /* Digital Active - tcpwm[1].line_compl[54]:0 */ 2760 P14_7_TCPWM1_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[165]:0 */ 2761 P14_7_TCPWM1_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[163]:0 */ 2762 P14_7_TCPWM1_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1552]:1 */ 2763 P14_7_LIN0_LIN_EN14 = 18, /* Digital Active - lin[0].lin_en[14]:0 */ 2764 P14_7_PERI_TR_IO_INPUT25 = 26, /* Digital Active - peri.tr_io_input[25]:0 */ 2765 2766 /* P15.0 */ 2767 P15_0_GPIO = 0, /* GPIO controls 'out' */ 2768 P15_0_AMUXA = 4, /* Analog mux bus A */ 2769 P15_0_AMUXB = 5, /* Analog mux bus B */ 2770 P15_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2771 P15_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2772 P15_0_TCPWM1_LINE56 = 8, /* Digital Active - tcpwm[1].line[56]:0 */ 2773 P15_0_TCPWM1_LINE_COMPL55 = 9, /* Digital Active - tcpwm[1].line_compl[55]:0 */ 2774 P15_0_TCPWM1_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[168]:0 */ 2775 P15_0_TCPWM1_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[166]:0 */ 2776 P15_0_TCPWM1_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1554]:1 */ 2777 P15_0_SCB9_UART_RX = 17, /* Digital Active - scb[9].uart_rx:0 */ 2778 P15_0_SCB9_SPI_MISO = 19, /* Digital Active - scb[9].spi_miso:0 */ 2779 P15_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:1 */ 2780 P15_0_AUDIOSS2_CLK_I2S_IF = 25, /* Digital Active - audioss[2].clk_i2s_if:0 */ 2781 2782 /* P15.1 */ 2783 P15_1_GPIO = 0, /* GPIO controls 'out' */ 2784 P15_1_AMUXA = 4, /* Analog mux bus A */ 2785 P15_1_AMUXB = 5, /* Analog mux bus B */ 2786 P15_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2787 P15_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2788 P15_1_TCPWM1_LINE57 = 8, /* Digital Active - tcpwm[1].line[57]:0 */ 2789 P15_1_TCPWM1_LINE_COMPL56 = 9, /* Digital Active - tcpwm[1].line_compl[56]:0 */ 2790 P15_1_TCPWM1_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[171]:0 */ 2791 P15_1_TCPWM1_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[169]:0 */ 2792 P15_1_TCPWM1_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1555]:1 */ 2793 P15_1_SCB9_UART_TX = 17, /* Digital Active - scb[9].uart_tx:0 */ 2794 P15_1_SCB9_I2C_SDA = 18, /* Digital Active - scb[9].i2c_sda:0 */ 2795 P15_1_SCB9_SPI_MOSI = 19, /* Digital Active - scb[9].spi_mosi:0 */ 2796 P15_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:1 */ 2797 P15_1_AUDIOSS2_RX_SCK = 25, /* Digital Active - audioss[2].rx_sck:0 */ 2798 2799 /* P15.2 */ 2800 P15_2_GPIO = 0, /* GPIO controls 'out' */ 2801 P15_2_AMUXA = 4, /* Analog mux bus A */ 2802 P15_2_AMUXB = 5, /* Analog mux bus B */ 2803 P15_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2804 P15_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2805 P15_2_TCPWM1_LINE58 = 8, /* Digital Active - tcpwm[1].line[58]:0 */ 2806 P15_2_TCPWM1_LINE_COMPL57 = 9, /* Digital Active - tcpwm[1].line_compl[57]:0 */ 2807 P15_2_TCPWM1_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[174]:0 */ 2808 P15_2_TCPWM1_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[172]:0 */ 2809 P15_2_TCPWM1_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1557]:1 */ 2810 P15_2_SCB9_UART_RTS = 17, /* Digital Active - scb[9].uart_rts:0 */ 2811 P15_2_SCB9_I2C_SCL = 18, /* Digital Active - scb[9].i2c_scl:0 */ 2812 P15_2_SCB9_SPI_CLK = 19, /* Digital Active - scb[9].spi_clk:0 */ 2813 P15_2_AUDIOSS2_RX_WS = 25, /* Digital Active - audioss[2].rx_ws:0 */ 2814 2815 /* P15.3 */ 2816 P15_3_GPIO = 0, /* GPIO controls 'out' */ 2817 P15_3_AMUXA = 4, /* Analog mux bus A */ 2818 P15_3_AMUXB = 5, /* Analog mux bus B */ 2819 P15_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2820 P15_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2821 P15_3_TCPWM1_LINE59 = 8, /* Digital Active - tcpwm[1].line[59]:0 */ 2822 P15_3_TCPWM1_LINE_COMPL58 = 9, /* Digital Active - tcpwm[1].line_compl[58]:0 */ 2823 P15_3_TCPWM1_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[177]:0 */ 2824 P15_3_TCPWM1_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[175]:0 */ 2825 P15_3_TCPWM1_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1558]:1 */ 2826 P15_3_SCB9_UART_CTS = 17, /* Digital Active - scb[9].uart_cts:0 */ 2827 P15_3_SCB9_SPI_SELECT0 = 19, /* Digital Active - scb[9].spi_select0:0 */ 2828 P15_3_AUDIOSS2_RX_SDI = 25, /* Digital Active - audioss[2].rx_sdi:0 */ 2829 2830 /* P16.0 */ 2831 P16_0_GPIO = 0, /* GPIO controls 'out' */ 2832 P16_0_AMUXA = 4, /* Analog mux bus A */ 2833 P16_0_AMUXB = 5, /* Analog mux bus B */ 2834 P16_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2835 P16_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2836 P16_0_TCPWM1_LINE60 = 8, /* Digital Active - tcpwm[1].line[60]:0 */ 2837 P16_0_TCPWM1_LINE_COMPL59 = 9, /* Digital Active - tcpwm[1].line_compl[59]:0 */ 2838 P16_0_TCPWM1_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[180]:0 */ 2839 P16_0_TCPWM1_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[178]:0 */ 2840 P16_0_TCPWM1_LINE512 = 16, /* Digital Active - tcpwm[1].line[512]:1 */ 2841 P16_0_SCB9_SPI_SELECT1 = 19, /* Digital Active - scb[9].spi_select1:0 */ 2842 P16_0_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:0 */ 2843 2844 /* P16.1 */ 2845 P16_1_GPIO = 0, /* GPIO controls 'out' */ 2846 P16_1_AMUXA = 4, /* Analog mux bus A */ 2847 P16_1_AMUXB = 5, /* Analog mux bus B */ 2848 P16_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2849 P16_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2850 P16_1_TCPWM1_LINE61 = 8, /* Digital Active - tcpwm[1].line[61]:0 */ 2851 P16_1_TCPWM1_LINE_COMPL60 = 9, /* Digital Active - tcpwm[1].line_compl[60]:0 */ 2852 P16_1_TCPWM1_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[183]:0 */ 2853 P16_1_TCPWM1_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[181]:0 */ 2854 P16_1_TCPWM1_LINE_COMPL512 = 16, /* Digital Active - tcpwm[1].line_compl[512]:1 */ 2855 P16_1_SCB9_SPI_SELECT2 = 19, /* Digital Active - scb[9].spi_select2:0 */ 2856 P16_1_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:0 */ 2857 2858 /* P16.2 */ 2859 P16_2_GPIO = 0, /* GPIO controls 'out' */ 2860 P16_2_AMUXA = 4, /* Analog mux bus A */ 2861 P16_2_AMUXB = 5, /* Analog mux bus B */ 2862 P16_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2863 P16_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2864 P16_2_TCPWM1_LINE62 = 8, /* Digital Active - tcpwm[1].line[62]:0 */ 2865 P16_2_TCPWM1_LINE_COMPL61 = 9, /* Digital Active - tcpwm[1].line_compl[61]:0 */ 2866 P16_2_TCPWM1_TR_ONE_CNT_IN186 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[186]:0 */ 2867 P16_2_TCPWM1_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[184]:0 */ 2868 P16_2_TCPWM1_LINE513 = 16, /* Digital Active - tcpwm[1].line[513]:1 */ 2869 P16_2_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:0 */ 2870 P16_2_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:0 */ 2871 2872 /* P16.3 */ 2873 P16_3_GPIO = 0, /* GPIO controls 'out' */ 2874 P16_3_AMUXA = 4, /* Analog mux bus A */ 2875 P16_3_AMUXB = 5, /* Analog mux bus B */ 2876 P16_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2877 P16_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2878 P16_3_TCPWM1_LINE62 = 8, /* Digital Active - tcpwm[1].line[62]:1 */ 2879 P16_3_TCPWM1_LINE_COMPL62 = 9, /* Digital Active - tcpwm[1].line_compl[62]:0 */ 2880 P16_3_TCPWM1_TR_ONE_CNT_IN186 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[186]:1 */ 2881 P16_3_TCPWM1_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[187]:0 */ 2882 P16_3_TCPWM1_LINE_COMPL513 = 16, /* Digital Active - tcpwm[1].line_compl[513]:1 */ 2883 2884 /* P16.4 */ 2885 P16_4_GPIO = 0, /* GPIO controls 'out' */ 2886 P16_4_AMUXA = 4, /* Analog mux bus A */ 2887 P16_4_AMUXB = 5, /* Analog mux bus B */ 2888 P16_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2889 P16_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2890 P16_4_TCPWM1_LINE68 = 8, /* Digital Active - tcpwm[1].line[68]:1 */ 2891 P16_4_TCPWM1_LINE_COMPL69 = 9, /* Digital Active - tcpwm[1].line_compl[69]:1 */ 2892 P16_4_TCPWM1_TR_ONE_CNT_IN204 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[204]:1 */ 2893 P16_4_TCPWM1_TR_ONE_CNT_IN208 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[208]:1 */ 2894 2895 /* P16.5 */ 2896 P16_5_GPIO = 0, /* GPIO controls 'out' */ 2897 P16_5_AMUXA = 4, /* Analog mux bus A */ 2898 P16_5_AMUXB = 5, /* Analog mux bus B */ 2899 P16_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2900 P16_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2901 P16_5_TCPWM1_LINE67 = 8, /* Digital Active - tcpwm[1].line[67]:1 */ 2902 P16_5_TCPWM1_LINE_COMPL68 = 9, /* Digital Active - tcpwm[1].line_compl[68]:1 */ 2903 P16_5_TCPWM1_TR_ONE_CNT_IN201 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[201]:1 */ 2904 P16_5_TCPWM1_TR_ONE_CNT_IN205 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[205]:1 */ 2905 2906 /* P16.6 */ 2907 P16_6_GPIO = 0, /* GPIO controls 'out' */ 2908 P16_6_AMUXA = 4, /* Analog mux bus A */ 2909 P16_6_AMUXB = 5, /* Analog mux bus B */ 2910 P16_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2911 P16_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2912 P16_6_TCPWM1_LINE66 = 8, /* Digital Active - tcpwm[1].line[66]:1 */ 2913 P16_6_TCPWM1_LINE_COMPL67 = 9, /* Digital Active - tcpwm[1].line_compl[67]:1 */ 2914 P16_6_TCPWM1_TR_ONE_CNT_IN198 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[198]:1 */ 2915 P16_6_TCPWM1_TR_ONE_CNT_IN202 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[202]:1 */ 2916 2917 /* P16.7 */ 2918 P16_7_GPIO = 0, /* GPIO controls 'out' */ 2919 P16_7_AMUXA = 4, /* Analog mux bus A */ 2920 P16_7_AMUXB = 5, /* Analog mux bus B */ 2921 P16_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2922 P16_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2923 P16_7_TCPWM1_LINE65 = 8, /* Digital Active - tcpwm[1].line[65]:1 */ 2924 P16_7_TCPWM1_LINE_COMPL66 = 9, /* Digital Active - tcpwm[1].line_compl[66]:1 */ 2925 P16_7_TCPWM1_TR_ONE_CNT_IN195 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[195]:1 */ 2926 P16_7_TCPWM1_TR_ONE_CNT_IN199 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[199]:1 */ 2927 2928 /* P17.0 */ 2929 P17_0_GPIO = 0, /* GPIO controls 'out' */ 2930 P17_0_AMUXA = 4, /* Analog mux bus A */ 2931 P17_0_AMUXB = 5, /* Analog mux bus B */ 2932 P17_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2933 P17_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2934 P17_0_TCPWM1_LINE61 = 8, /* Digital Active - tcpwm[1].line[61]:1 */ 2935 P17_0_TCPWM1_LINE_COMPL62 = 9, /* Digital Active - tcpwm[1].line_compl[62]:1 */ 2936 P17_0_TCPWM1_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[183]:1 */ 2937 P17_0_TCPWM1_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[187]:1 */ 2938 P17_0_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:2 */ 2939 P17_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:0 */ 2940 2941 /* P17.1 */ 2942 P17_1_GPIO = 0, /* GPIO controls 'out' */ 2943 P17_1_AMUXA = 4, /* Analog mux bus A */ 2944 P17_1_AMUXB = 5, /* Analog mux bus B */ 2945 P17_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2946 P17_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2947 P17_1_TCPWM1_LINE60 = 8, /* Digital Active - tcpwm[1].line[60]:1 */ 2948 P17_1_TCPWM1_LINE_COMPL61 = 9, /* Digital Active - tcpwm[1].line_compl[61]:1 */ 2949 P17_1_TCPWM1_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[180]:1 */ 2950 P17_1_TCPWM1_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[184]:1 */ 2951 P17_1_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:1 */ 2952 P17_1_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:2 */ 2953 P17_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:0 */ 2954 2955 /* P17.2 */ 2956 P17_2_GPIO = 0, /* GPIO controls 'out' */ 2957 P17_2_AMUXA = 4, /* Analog mux bus A */ 2958 P17_2_AMUXB = 5, /* Analog mux bus B */ 2959 P17_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2960 P17_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2961 P17_2_TCPWM1_LINE59 = 8, /* Digital Active - tcpwm[1].line[59]:1 */ 2962 P17_2_TCPWM1_LINE_COMPL60 = 9, /* Digital Active - tcpwm[1].line_compl[60]:1 */ 2963 P17_2_TCPWM1_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[177]:1 */ 2964 P17_2_TCPWM1_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[181]:1 */ 2965 P17_2_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:1 */ 2966 P17_2_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:1 */ 2967 P17_2_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:2 */ 2968 2969 /* P17.3 */ 2970 P17_3_GPIO = 0, /* GPIO controls 'out' */ 2971 P17_3_AMUXA = 4, /* Analog mux bus A */ 2972 P17_3_AMUXB = 5, /* Analog mux bus B */ 2973 P17_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2974 P17_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2975 P17_3_TCPWM1_LINE58 = 8, /* Digital Active - tcpwm[1].line[58]:1 */ 2976 P17_3_TCPWM1_LINE_COMPL59 = 9, /* Digital Active - tcpwm[1].line_compl[59]:1 */ 2977 P17_3_TCPWM1_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[174]:1 */ 2978 P17_3_TCPWM1_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[178]:1 */ 2979 P17_3_TCPWM1_LINE515 = 16, /* Digital Active - tcpwm[1].line[515]:1 */ 2980 P17_3_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:1 */ 2981 P17_3_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:1 */ 2982 P17_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:1 */ 2983 P17_3_PERI_TR_IO_INPUT26 = 26, /* Digital Active - peri.tr_io_input[26]:0 */ 2984 2985 /* P17.4 */ 2986 P17_4_GPIO = 0, /* GPIO controls 'out' */ 2987 P17_4_AMUXA = 4, /* Analog mux bus A */ 2988 P17_4_AMUXB = 5, /* Analog mux bus B */ 2989 P17_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2990 P17_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2991 P17_4_TCPWM1_LINE57 = 8, /* Digital Active - tcpwm[1].line[57]:1 */ 2992 P17_4_TCPWM1_LINE_COMPL58 = 9, /* Digital Active - tcpwm[1].line_compl[58]:1 */ 2993 P17_4_TCPWM1_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[171]:1 */ 2994 P17_4_TCPWM1_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[175]:1 */ 2995 P17_4_TCPWM1_LINE_COMPL515 = 16, /* Digital Active - tcpwm[1].line_compl[515]:1 */ 2996 P17_4_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:1 */ 2997 P17_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:1 */ 2998 P17_4_PERI_TR_IO_INPUT27 = 26, /* Digital Active - peri.tr_io_input[27]:0 */ 2999 3000 /* P17.5 */ 3001 P17_5_GPIO = 0, /* GPIO controls 'out' */ 3002 P17_5_AMUXA = 4, /* Analog mux bus A */ 3003 P17_5_AMUXB = 5, /* Analog mux bus B */ 3004 P17_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3005 P17_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3006 P17_5_TCPWM1_LINE56 = 8, /* Digital Active - tcpwm[1].line[56]:1 */ 3007 P17_5_TCPWM1_LINE_COMPL57 = 9, /* Digital Active - tcpwm[1].line_compl[57]:1 */ 3008 P17_5_TCPWM1_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[168]:1 */ 3009 P17_5_TCPWM1_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[172]:1 */ 3010 P17_5_TCPWM1_LINE514 = 16, /* Digital Active - tcpwm[1].line[514]:1 */ 3011 P17_5_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:0 */ 3012 P17_5_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:1 */ 3013 3014 /* P17.6 */ 3015 P17_6_GPIO = 0, /* GPIO controls 'out' */ 3016 P17_6_AMUXA = 4, /* Analog mux bus A */ 3017 P17_6_AMUXB = 5, /* Analog mux bus B */ 3018 P17_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3019 P17_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3020 P17_6_TCPWM1_LINE260 = 8, /* Digital Active - tcpwm[1].line[260]:1 */ 3021 P17_6_TCPWM1_LINE_COMPL56 = 9, /* Digital Active - tcpwm[1].line_compl[56]:1 */ 3022 P17_6_TCPWM1_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[780]:1 */ 3023 P17_6_TCPWM1_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[169]:1 */ 3024 P17_6_TCPWM1_LINE_COMPL514 = 16, /* Digital Active - tcpwm[1].line_compl[514]:1 */ 3025 P17_6_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:0 */ 3026 P17_6_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:1 */ 3027 3028 /* P17.7 */ 3029 P17_7_GPIO = 0, /* GPIO controls 'out' */ 3030 P17_7_AMUXA = 4, /* Analog mux bus A */ 3031 P17_7_AMUXB = 5, /* Analog mux bus B */ 3032 P17_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3033 P17_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3034 P17_7_TCPWM1_LINE261 = 8, /* Digital Active - tcpwm[1].line[261]:1 */ 3035 P17_7_TCPWM1_LINE_COMPL260 = 9, /* Digital Active - tcpwm[1].line_compl[260]:1 */ 3036 P17_7_TCPWM1_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[783]:1 */ 3037 P17_7_TCPWM1_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[781]:1 */ 3038 P17_7_LIN0_LIN_EN15 = 18, /* Digital Active - lin[0].lin_en[15]:0 */ 3039 P17_7_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:1 */ 3040 3041 /* P18.0 */ 3042 P18_0_GPIO = 0, /* GPIO controls 'out' */ 3043 P18_0_AMUXA = 4, /* Analog mux bus A */ 3044 P18_0_AMUXB = 5, /* Analog mux bus B */ 3045 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3046 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3047 P18_0_TCPWM1_LINE262 = 8, /* Digital Active - tcpwm[1].line[262]:1 */ 3048 P18_0_TCPWM1_LINE_COMPL261 = 9, /* Digital Active - tcpwm[1].line_compl[261]:1 */ 3049 P18_0_TCPWM1_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[786]:1 */ 3050 P18_0_TCPWM1_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[784]:1 */ 3051 P18_0_TCPWM1_LINE512 = 16, /* Digital Active - tcpwm[1].line[512]:0 */ 3052 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 3053 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 3054 P18_0_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:1 */ 3055 P18_0_ETH0_REF_CLK = 24, /* Digital Active - eth[0].ref_clk:0 */ 3056 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 3057 3058 /* P18.1 */ 3059 P18_1_GPIO = 0, /* GPIO controls 'out' */ 3060 P18_1_AMUXA = 4, /* Analog mux bus A */ 3061 P18_1_AMUXB = 5, /* Analog mux bus B */ 3062 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3063 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3064 P18_1_TCPWM1_LINE263 = 8, /* Digital Active - tcpwm[1].line[263]:1 */ 3065 P18_1_TCPWM1_LINE_COMPL262 = 9, /* Digital Active - tcpwm[1].line_compl[262]:1 */ 3066 P18_1_TCPWM1_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[789]:1 */ 3067 P18_1_TCPWM1_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[787]:1 */ 3068 P18_1_TCPWM1_LINE_COMPL512 = 16, /* Digital Active - tcpwm[1].line_compl[512]:0 */ 3069 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 3070 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 3071 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 3072 P18_1_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:1 */ 3073 P18_1_ETH0_TX_CTL = 24, /* Digital Active - eth[0].tx_ctl:0 */ 3074 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 3075 3076 /* P18.2 */ 3077 P18_2_GPIO = 0, /* GPIO controls 'out' */ 3078 P18_2_AMUXA = 4, /* Analog mux bus A */ 3079 P18_2_AMUXB = 5, /* Analog mux bus B */ 3080 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3081 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3082 P18_2_TCPWM1_LINE55 = 8, /* Digital Active - tcpwm[1].line[55]:1 */ 3083 P18_2_TCPWM1_LINE_COMPL263 = 9, /* Digital Active - tcpwm[1].line_compl[263]:1 */ 3084 P18_2_TCPWM1_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[165]:1 */ 3085 P18_2_TCPWM1_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[790]:1 */ 3086 P18_2_TCPWM1_LINE513 = 16, /* Digital Active - tcpwm[1].line[513]:0 */ 3087 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 3088 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 3089 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 3090 P18_2_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:1 */ 3091 P18_2_ETH0_TX_ER = 24, /* Digital Active - eth[0].tx_er:0 */ 3092 3093 /* P18.3 */ 3094 P18_3_GPIO = 0, /* GPIO controls 'out' */ 3095 P18_3_AMUXA = 4, /* Analog mux bus A */ 3096 P18_3_AMUXB = 5, /* Analog mux bus B */ 3097 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3098 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3099 P18_3_TCPWM1_LINE54 = 8, /* Digital Active - tcpwm[1].line[54]:1 */ 3100 P18_3_TCPWM1_LINE_COMPL55 = 9, /* Digital Active - tcpwm[1].line_compl[55]:1 */ 3101 P18_3_TCPWM1_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[162]:1 */ 3102 P18_3_TCPWM1_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[166]:1 */ 3103 P18_3_TCPWM1_LINE_COMPL513 = 16, /* Digital Active - tcpwm[1].line_compl[513]:0 */ 3104 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 3105 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 3106 P18_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:2 */ 3107 P18_3_ETH0_TX_CLK = 24, /* Digital Active - eth[0].tx_clk:0 */ 3108 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 3109 3110 /* P18.4 */ 3111 P18_4_GPIO = 0, /* GPIO controls 'out' */ 3112 P18_4_AMUXA = 4, /* Analog mux bus A */ 3113 P18_4_AMUXB = 5, /* Analog mux bus B */ 3114 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3115 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3116 P18_4_TCPWM1_LINE53 = 8, /* Digital Active - tcpwm[1].line[53]:1 */ 3117 P18_4_TCPWM1_LINE_COMPL54 = 9, /* Digital Active - tcpwm[1].line_compl[54]:1 */ 3118 P18_4_TCPWM1_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[159]:1 */ 3119 P18_4_TCPWM1_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[163]:1 */ 3120 P18_4_TCPWM1_LINE514 = 16, /* Digital Active - tcpwm[1].line[514]:0 */ 3121 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 3122 P18_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:2 */ 3123 P18_4_TCPWM0_LINE258 = 22, /* Digital Active - tcpwm[0].line[258] */ 3124 P18_4_ETH0_TXD0 = 24, /* Digital Active - eth[0].txd[0]:0 */ 3125 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 3126 3127 /* P18.5 */ 3128 P18_5_GPIO = 0, /* GPIO controls 'out' */ 3129 P18_5_AMUXA = 4, /* Analog mux bus A */ 3130 P18_5_AMUXB = 5, /* Analog mux bus B */ 3131 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3132 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3133 P18_5_TCPWM1_LINE52 = 8, /* Digital Active - tcpwm[1].line[52]:1 */ 3134 P18_5_TCPWM1_LINE_COMPL53 = 9, /* Digital Active - tcpwm[1].line_compl[53]:1 */ 3135 P18_5_TCPWM1_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[156]:1 */ 3136 P18_5_TCPWM1_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[160]:1 */ 3137 P18_5_TCPWM1_LINE_COMPL514 = 16, /* Digital Active - tcpwm[1].line_compl[514]:0 */ 3138 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 3139 P18_5_TCPWM0_LINE_COMPL258 = 22, /* Digital Active - tcpwm[0].line_compl[258] */ 3140 P18_5_ETH0_TXD1 = 24, /* Digital Active - eth[0].txd[1]:0 */ 3141 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 3142 3143 /* P18.6 */ 3144 P18_6_GPIO = 0, /* GPIO controls 'out' */ 3145 P18_6_AMUXA = 4, /* Analog mux bus A */ 3146 P18_6_AMUXB = 5, /* Analog mux bus B */ 3147 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3148 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3149 P18_6_TCPWM1_LINE51 = 8, /* Digital Active - tcpwm[1].line[51]:1 */ 3150 P18_6_TCPWM1_LINE_COMPL52 = 9, /* Digital Active - tcpwm[1].line_compl[52]:1 */ 3151 P18_6_TCPWM1_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[153]:1 */ 3152 P18_6_TCPWM1_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[157]:1 */ 3153 P18_6_TCPWM1_LINE515 = 16, /* Digital Active - tcpwm[1].line[515]:0 */ 3154 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 3155 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 3156 P18_6_TCPWM0_TR_ONE_CNT_IN774 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[774] */ 3157 P18_6_ETH0_TXD2 = 24, /* Digital Active - eth[0].txd[2]:0 */ 3158 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 3159 3160 /* P18.7 */ 3161 P18_7_GPIO = 0, /* GPIO controls 'out' */ 3162 P18_7_AMUXA = 4, /* Analog mux bus A */ 3163 P18_7_AMUXB = 5, /* Analog mux bus B */ 3164 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3165 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3166 P18_7_TCPWM1_LINE50 = 8, /* Digital Active - tcpwm[1].line[50]:1 */ 3167 P18_7_TCPWM1_LINE_COMPL51 = 9, /* Digital Active - tcpwm[1].line_compl[51]:1 */ 3168 P18_7_TCPWM1_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[150]:1 */ 3169 P18_7_TCPWM1_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[154]:1 */ 3170 P18_7_TCPWM1_LINE_COMPL515 = 16, /* Digital Active - tcpwm[1].line_compl[515]:0 */ 3171 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 3172 P18_7_TCPWM0_TR_ONE_CNT_IN775 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[775] */ 3173 P18_7_ETH0_TXD3 = 24, /* Digital Active - eth[0].txd[3]:0 */ 3174 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 3175 3176 /* P19.0 */ 3177 P19_0_GPIO = 0, /* GPIO controls 'out' */ 3178 P19_0_AMUXA = 4, /* Analog mux bus A */ 3179 P19_0_AMUXB = 5, /* Analog mux bus B */ 3180 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3181 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3182 P19_0_TCPWM1_LINE259 = 8, /* Digital Active - tcpwm[1].line[259]:2 */ 3183 P19_0_TCPWM1_LINE_COMPL50 = 9, /* Digital Active - tcpwm[1].line_compl[50]:1 */ 3184 P19_0_TCPWM1_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[777]:2 */ 3185 P19_0_TCPWM1_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[151]:1 */ 3186 P19_0_TCPWM1_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1536]:0 */ 3187 P19_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:1 */ 3188 P19_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:1 */ 3189 P19_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:0 */ 3190 P19_0_ETH0_RXD0 = 24, /* Digital Active - eth[0].rxd[0]:0 */ 3191 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 3192 3193 /* P19.1 */ 3194 P19_1_GPIO = 0, /* GPIO controls 'out' */ 3195 P19_1_AMUXA = 4, /* Analog mux bus A */ 3196 P19_1_AMUXB = 5, /* Analog mux bus B */ 3197 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3198 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3199 P19_1_TCPWM1_LINE26 = 8, /* Digital Active - tcpwm[1].line[26]:1 */ 3200 P19_1_TCPWM1_LINE_COMPL259 = 9, /* Digital Active - tcpwm[1].line_compl[259]:2 */ 3201 P19_1_TCPWM1_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[78]:1 */ 3202 P19_1_TCPWM1_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[778]:2 */ 3203 P19_1_TCPWM1_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1537]:0 */ 3204 P19_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:1 */ 3205 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 3206 P19_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:1 */ 3207 P19_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:0 */ 3208 P19_1_ETH0_RXD1 = 24, /* Digital Active - eth[0].rxd[1]:0 */ 3209 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 3210 3211 /* P19.2 */ 3212 P19_2_GPIO = 0, /* GPIO controls 'out' */ 3213 P19_2_AMUXA = 4, /* Analog mux bus A */ 3214 P19_2_AMUXB = 5, /* Analog mux bus B */ 3215 P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3216 P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3217 P19_2_TCPWM1_LINE27 = 8, /* Digital Active - tcpwm[1].line[27]:2 */ 3218 P19_2_TCPWM1_LINE_COMPL26 = 9, /* Digital Active - tcpwm[1].line_compl[26]:1 */ 3219 P19_2_TCPWM1_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[81]:2 */ 3220 P19_2_TCPWM1_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[79]:1 */ 3221 P19_2_TCPWM1_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1539]:0 */ 3222 P19_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:1 */ 3223 P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ 3224 P19_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:1 */ 3225 P19_2_ETH0_RXD2 = 24, /* Digital Active - eth[0].rxd[2]:0 */ 3226 P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ 3227 3228 /* P19.3 */ 3229 P19_3_GPIO = 0, /* GPIO controls 'out' */ 3230 P19_3_AMUXA = 4, /* Analog mux bus A */ 3231 P19_3_AMUXB = 5, /* Analog mux bus B */ 3232 P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3233 P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3234 P19_3_TCPWM1_LINE28 = 8, /* Digital Active - tcpwm[1].line[28]:2 */ 3235 P19_3_TCPWM1_LINE_COMPL27 = 9, /* Digital Active - tcpwm[1].line_compl[27]:2 */ 3236 P19_3_TCPWM1_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[84]:2 */ 3237 P19_3_TCPWM1_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[82]:2 */ 3238 P19_3_TCPWM1_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1540]:0 */ 3239 P19_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:1 */ 3240 P19_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:1 */ 3241 P19_3_ETH0_RXD3 = 24, /* Digital Active - eth[0].rxd[3]:0 */ 3242 P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ 3243 3244 /* P19.4 */ 3245 P19_4_GPIO = 0, /* GPIO controls 'out' */ 3246 P19_4_AMUXA = 4, /* Analog mux bus A */ 3247 P19_4_AMUXB = 5, /* Analog mux bus B */ 3248 P19_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3249 P19_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3250 P19_4_TCPWM1_LINE29 = 8, /* Digital Active - tcpwm[1].line[29]:2 */ 3251 P19_4_TCPWM1_LINE_COMPL28 = 9, /* Digital Active - tcpwm[1].line_compl[28]:2 */ 3252 P19_4_TCPWM1_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[87]:2 */ 3253 P19_4_TCPWM1_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[85]:2 */ 3254 P19_4_TCPWM1_TR_ONE_CNT_IN1542 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1542]:0 */ 3255 P19_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:1 */ 3256 3257 /* P20.0 */ 3258 P20_0_GPIO = 0, /* GPIO controls 'out' */ 3259 P20_0_AMUXA = 4, /* Analog mux bus A */ 3260 P20_0_AMUXB = 5, /* Analog mux bus B */ 3261 P20_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3262 P20_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3263 P20_0_TCPWM1_LINE30 = 8, /* Digital Active - tcpwm[1].line[30]:2 */ 3264 P20_0_TCPWM1_LINE_COMPL29 = 9, /* Digital Active - tcpwm[1].line_compl[29]:2 */ 3265 P20_0_TCPWM1_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[90]:2 */ 3266 P20_0_TCPWM1_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[88]:2 */ 3267 P20_0_TCPWM1_TR_ONE_CNT_IN1543 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1543]:0 */ 3268 P20_0_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:1 */ 3269 P20_0_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:0 */ 3270 3271 /* P20.1 */ 3272 P20_1_GPIO = 0, /* GPIO controls 'out' */ 3273 P20_1_AMUXA = 4, /* Analog mux bus A */ 3274 P20_1_AMUXB = 5, /* Analog mux bus B */ 3275 P20_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3276 P20_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3277 P20_1_TCPWM1_LINE49 = 8, /* Digital Active - tcpwm[1].line[49]:1 */ 3278 P20_1_TCPWM1_LINE_COMPL30 = 9, /* Digital Active - tcpwm[1].line_compl[30]:2 */ 3279 P20_1_TCPWM1_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[147]:1 */ 3280 P20_1_TCPWM1_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[91]:2 */ 3281 P20_1_TCPWM1_TR_ONE_CNT_IN1545 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1545]:0 */ 3282 P20_1_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:0 */ 3283 3284 /* P20.2 */ 3285 P20_2_GPIO = 0, /* GPIO controls 'out' */ 3286 P20_2_AMUXA = 4, /* Analog mux bus A */ 3287 P20_2_AMUXB = 5, /* Analog mux bus B */ 3288 P20_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3289 P20_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3290 P20_2_TCPWM1_LINE48 = 8, /* Digital Active - tcpwm[1].line[48]:1 */ 3291 P20_2_TCPWM1_LINE_COMPL49 = 9, /* Digital Active - tcpwm[1].line_compl[49]:1 */ 3292 P20_2_TCPWM1_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[144]:1 */ 3293 P20_2_TCPWM1_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[148]:1 */ 3294 P20_2_TCPWM1_TR_ONE_CNT_IN1546 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1546]:0 */ 3295 P20_2_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:0 */ 3296 3297 /* P20.3 */ 3298 P20_3_GPIO = 0, /* GPIO controls 'out' */ 3299 P20_3_AMUXA = 4, /* Analog mux bus A */ 3300 P20_3_AMUXB = 5, /* Analog mux bus B */ 3301 P20_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3302 P20_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3303 P20_3_TCPWM1_LINE47 = 8, /* Digital Active - tcpwm[1].line[47]:1 */ 3304 P20_3_TCPWM1_LINE_COMPL48 = 9, /* Digital Active - tcpwm[1].line_compl[48]:1 */ 3305 P20_3_TCPWM1_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[141]:1 */ 3306 P20_3_TCPWM1_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[145]:1 */ 3307 P20_3_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:1 */ 3308 P20_3_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:1 */ 3309 P20_3_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:1 */ 3310 3311 /* P20.4 */ 3312 P20_4_GPIO = 0, /* GPIO controls 'out' */ 3313 P20_4_AMUXA = 4, /* Analog mux bus A */ 3314 P20_4_AMUXB = 5, /* Analog mux bus B */ 3315 P20_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3316 P20_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3317 P20_4_TCPWM1_LINE46 = 8, /* Digital Active - tcpwm[1].line[46]:1 */ 3318 P20_4_TCPWM1_LINE_COMPL47 = 9, /* Digital Active - tcpwm[1].line_compl[47]:1 */ 3319 P20_4_TCPWM1_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[138]:1 */ 3320 P20_4_TCPWM1_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[142]:1 */ 3321 P20_4_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:1 */ 3322 P20_4_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:1 */ 3323 P20_4_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:1 */ 3324 P20_4_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:1 */ 3325 3326 /* P20.5 */ 3327 P20_5_GPIO = 0, /* GPIO controls 'out' */ 3328 P20_5_AMUXA = 4, /* Analog mux bus A */ 3329 P20_5_AMUXB = 5, /* Analog mux bus B */ 3330 P20_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3331 P20_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3332 P20_5_TCPWM1_LINE45 = 8, /* Digital Active - tcpwm[1].line[45]:1 */ 3333 P20_5_TCPWM1_LINE_COMPL46 = 9, /* Digital Active - tcpwm[1].line_compl[46]:1 */ 3334 P20_5_TCPWM1_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[135]:1 */ 3335 P20_5_TCPWM1_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[139]:1 */ 3336 P20_5_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:1 */ 3337 P20_5_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:1 */ 3338 P20_5_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:1 */ 3339 3340 /* P20.6 */ 3341 P20_6_GPIO = 0, /* GPIO controls 'out' */ 3342 P20_6_AMUXA = 4, /* Analog mux bus A */ 3343 P20_6_AMUXB = 5, /* Analog mux bus B */ 3344 P20_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3345 P20_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3346 P20_6_TCPWM1_LINE44 = 8, /* Digital Active - tcpwm[1].line[44]:1 */ 3347 P20_6_TCPWM1_LINE_COMPL45 = 9, /* Digital Active - tcpwm[1].line_compl[45]:1 */ 3348 P20_6_TCPWM1_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[132]:1 */ 3349 P20_6_TCPWM1_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[136]:1 */ 3350 P20_6_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:1 */ 3351 P20_6_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:1 */ 3352 P20_6_CANFD1_TTCAN_TX4 = 21, /* Digital Active - canfd[1].ttcan_tx[4]:0 */ 3353 3354 /* P20.7 */ 3355 P20_7_GPIO = 0, /* GPIO controls 'out' */ 3356 P20_7_AMUXA = 4, /* Analog mux bus A */ 3357 P20_7_AMUXB = 5, /* Analog mux bus B */ 3358 P20_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3359 P20_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3360 P20_7_TCPWM1_LINE43 = 8, /* Digital Active - tcpwm[1].line[43]:1 */ 3361 P20_7_TCPWM1_LINE_COMPL44 = 9, /* Digital Active - tcpwm[1].line_compl[44]:1 */ 3362 P20_7_TCPWM1_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[129]:1 */ 3363 P20_7_TCPWM1_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[133]:1 */ 3364 P20_7_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:1 */ 3365 P20_7_CANFD1_TTCAN_RX4 = 21, /* Digital Active - canfd[1].ttcan_rx[4]:0 */ 3366 3367 /* P21.0 */ 3368 P21_0_GPIO = 0, /* GPIO controls 'out' */ 3369 P21_0_AMUXA = 4, /* Analog mux bus A */ 3370 P21_0_AMUXB = 5, /* Analog mux bus B */ 3371 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3372 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3373 P21_0_TCPWM1_LINE42 = 8, /* Digital Active - tcpwm[1].line[42]:1 */ 3374 P21_0_TCPWM1_LINE_COMPL43 = 9, /* Digital Active - tcpwm[1].line_compl[43]:1 */ 3375 P21_0_TCPWM1_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[126]:1 */ 3376 P21_0_TCPWM1_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[130]:1 */ 3377 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 3378 3379 /* P21.1 */ 3380 P21_1_GPIO = 0, /* GPIO controls 'out' */ 3381 P21_1_AMUXA = 4, /* Analog mux bus A */ 3382 P21_1_AMUXB = 5, /* Analog mux bus B */ 3383 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3384 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3385 P21_1_TCPWM1_LINE41 = 8, /* Digital Active - tcpwm[1].line[41]:1 */ 3386 P21_1_TCPWM1_LINE_COMPL42 = 9, /* Digital Active - tcpwm[1].line_compl[42]:1 */ 3387 P21_1_TCPWM1_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[123]:1 */ 3388 P21_1_TCPWM1_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[127]:1 */ 3389 3390 /* P21.2 */ 3391 P21_2_GPIO = 0, /* GPIO controls 'out' */ 3392 P21_2_AMUXA = 4, /* Analog mux bus A */ 3393 P21_2_AMUXB = 5, /* Analog mux bus B */ 3394 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3395 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3396 P21_2_TCPWM1_LINE40 = 8, /* Digital Active - tcpwm[1].line[40]:1 */ 3397 P21_2_TCPWM1_LINE_COMPL41 = 9, /* Digital Active - tcpwm[1].line_compl[41]:1 */ 3398 P21_2_TCPWM1_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[120]:1 */ 3399 P21_2_TCPWM1_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[124]:1 */ 3400 P21_2_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:0 */ 3401 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 3402 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 3403 3404 /* P21.3 */ 3405 P21_3_GPIO = 0, /* GPIO controls 'out' */ 3406 P21_3_AMUXA = 4, /* Analog mux bus A */ 3407 P21_3_AMUXB = 5, /* Analog mux bus B */ 3408 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3409 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3410 P21_3_TCPWM1_LINE39 = 8, /* Digital Active - tcpwm[1].line[39]:1 */ 3411 P21_3_TCPWM1_LINE_COMPL40 = 9, /* Digital Active - tcpwm[1].line_compl[40]:1 */ 3412 P21_3_TCPWM1_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[117]:1 */ 3413 P21_3_TCPWM1_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[121]:1 */ 3414 3415 /* P21.4 */ 3416 P21_4_GPIO = 0, /* GPIO controls 'out' */ 3417 P21_4_AMUXA = 4, /* Analog mux bus A */ 3418 P21_4_AMUXB = 5, /* Analog mux bus B */ 3419 P21_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3420 P21_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3421 P21_4_TCPWM1_LINE38 = 8, /* Digital Active - tcpwm[1].line[38]:1 */ 3422 P21_4_TCPWM1_LINE_COMPL39 = 9, /* Digital Active - tcpwm[1].line_compl[39]:1 */ 3423 P21_4_TCPWM1_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[114]:1 */ 3424 P21_4_TCPWM1_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[118]:1 */ 3425 3426 /* P21.5 */ 3427 P21_5_GPIO = 0, /* GPIO controls 'out' */ 3428 P21_5_AMUXA = 4, /* Analog mux bus A */ 3429 P21_5_AMUXB = 5, /* Analog mux bus B */ 3430 P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3431 P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3432 P21_5_TCPWM1_LINE37 = 8, /* Digital Active - tcpwm[1].line[37]:1 */ 3433 P21_5_TCPWM1_LINE_COMPL38 = 9, /* Digital Active - tcpwm[1].line_compl[38]:1 */ 3434 P21_5_TCPWM1_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[111]:1 */ 3435 P21_5_TCPWM1_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[115]:1 */ 3436 P21_5_TCPWM1_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[1].tr_one_cnt_in[106]:1 */ 3437 P21_5_TCPWM1_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[1].tr_one_cnt_in[102]:1 */ 3438 P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ 3439 P21_5_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 3440 P21_5_TCPWM1_LINE34 = 22, /* Digital Active - tcpwm[1].line[34]:1 */ 3441 P21_5_TCPWM1_LINE_COMPL35 = 23, /* Digital Active - tcpwm[1].line_compl[35]:1 */ 3442 P21_5_ETH0_RX_CTL = 24, /* Digital Active - eth[0].rx_ctl:0 */ 3443 P21_5_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 3444 3445 /* P21.6 */ 3446 P21_6_GPIO = 0, /* GPIO controls 'out' */ 3447 P21_6_AMUXA = 4, /* Analog mux bus A */ 3448 P21_6_AMUXB = 5, /* Analog mux bus B */ 3449 P21_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3450 P21_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3451 P21_6_TCPWM1_LINE36 = 8, /* Digital Active - tcpwm[1].line[36]:1 */ 3452 P21_6_TCPWM1_LINE_COMPL37 = 9, /* Digital Active - tcpwm[1].line_compl[37]:1 */ 3453 P21_6_TCPWM1_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[108]:1 */ 3454 P21_6_TCPWM1_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[112]:1 */ 3455 P21_6_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:1 */ 3456 P21_6_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:1 */ 3457 P21_6_CPUSS_CLK_FM_PUMP = 26, /* Digital Active - cpuss.clk_fm_pump */ 3458 3459 /* P21.7 */ 3460 P21_7_GPIO = 0, /* GPIO controls 'out' */ 3461 P21_7_AMUXA = 4, /* Analog mux bus A */ 3462 P21_7_AMUXB = 5, /* Analog mux bus B */ 3463 P21_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3464 P21_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3465 P21_7_TCPWM1_LINE35 = 8, /* Digital Active - tcpwm[1].line[35]:1 */ 3466 P21_7_TCPWM1_LINE_COMPL36 = 9, /* Digital Active - tcpwm[1].line_compl[36]:1 */ 3467 P21_7_TCPWM1_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[105]:1 */ 3468 P21_7_TCPWM1_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[109]:1 */ 3469 P21_7_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ 3470 P21_7_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ 3471 P21_7_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:1 */ 3472 P21_7_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:1 */ 3473 P21_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:1 */ 3474 P21_7_SRSS_CAL_WAVE = 29, /* Digital Deep Sleep - srss.cal_wave:0 */ 3475 3476 /* P22.1 */ 3477 P22_1_GPIO = 0, /* GPIO controls 'out' */ 3478 P22_1_AMUXA = 4, /* Analog mux bus A */ 3479 P22_1_AMUXB = 5, /* Analog mux bus B */ 3480 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3481 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3482 P22_1_TCPWM1_LINE33 = 8, /* Digital Active - tcpwm[1].line[33]:1 */ 3483 P22_1_TCPWM1_LINE_COMPL34 = 9, /* Digital Active - tcpwm[1].line_compl[34]:1 */ 3484 P22_1_TCPWM1_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[99]:1 */ 3485 P22_1_TCPWM1_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[103]:1 */ 3486 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 3487 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 3488 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 3489 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 3490 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 3491 3492 /* P22.2 */ 3493 P22_2_GPIO = 0, /* GPIO controls 'out' */ 3494 P22_2_AMUXA = 4, /* Analog mux bus A */ 3495 P22_2_AMUXB = 5, /* Analog mux bus B */ 3496 P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3497 P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3498 P22_2_TCPWM1_LINE32 = 8, /* Digital Active - tcpwm[1].line[32]:1 */ 3499 P22_2_TCPWM1_LINE_COMPL33 = 9, /* Digital Active - tcpwm[1].line_compl[33]:1 */ 3500 P22_2_TCPWM1_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[96]:1 */ 3501 P22_2_TCPWM1_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[100]:1 */ 3502 P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ 3503 P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ 3504 P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ 3505 P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 3506 3507 /* P22.3 */ 3508 P22_3_GPIO = 0, /* GPIO controls 'out' */ 3509 P22_3_AMUXA = 4, /* Analog mux bus A */ 3510 P22_3_AMUXB = 5, /* Analog mux bus B */ 3511 P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3512 P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3513 P22_3_TCPWM1_LINE31 = 8, /* Digital Active - tcpwm[1].line[31]:1 */ 3514 P22_3_TCPWM1_LINE_COMPL32 = 9, /* Digital Active - tcpwm[1].line_compl[32]:1 */ 3515 P22_3_TCPWM1_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[93]:1 */ 3516 P22_3_TCPWM1_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[97]:1 */ 3517 P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ 3518 P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ 3519 P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 3520 3521 /* P22.4 */ 3522 P22_4_GPIO = 0, /* GPIO controls 'out' */ 3523 P22_4_AMUXA = 4, /* Analog mux bus A */ 3524 P22_4_AMUXB = 5, /* Analog mux bus B */ 3525 P22_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3526 P22_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3527 P22_4_TCPWM1_LINE30 = 8, /* Digital Active - tcpwm[1].line[30]:1 */ 3528 P22_4_TCPWM1_LINE_COMPL31 = 9, /* Digital Active - tcpwm[1].line_compl[31]:1 */ 3529 P22_4_TCPWM1_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[90]:1 */ 3530 P22_4_TCPWM1_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[94]:1 */ 3531 P22_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:1 */ 3532 P22_4_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:1 */ 3533 3534 /* P22.5 */ 3535 P22_5_GPIO = 0, /* GPIO controls 'out' */ 3536 P22_5_AMUXA = 4, /* Analog mux bus A */ 3537 P22_5_AMUXB = 5, /* Analog mux bus B */ 3538 P22_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3539 P22_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3540 P22_5_TCPWM1_LINE29 = 8, /* Digital Active - tcpwm[1].line[29]:1 */ 3541 P22_5_TCPWM1_LINE_COMPL30 = 9, /* Digital Active - tcpwm[1].line_compl[30]:1 */ 3542 P22_5_TCPWM1_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[87]:1 */ 3543 P22_5_TCPWM1_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[91]:1 */ 3544 P22_5_TCPWM1_LINE520 = 16, /* Digital Active - tcpwm[1].line[520]:0 */ 3545 P22_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:1 */ 3546 P22_5_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:1 */ 3547 3548 /* P22.6 */ 3549 P22_6_GPIO = 0, /* GPIO controls 'out' */ 3550 P22_6_AMUXA = 4, /* Analog mux bus A */ 3551 P22_6_AMUXB = 5, /* Analog mux bus B */ 3552 P22_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3553 P22_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3554 P22_6_TCPWM1_LINE28 = 8, /* Digital Active - tcpwm[1].line[28]:1 */ 3555 P22_6_TCPWM1_LINE_COMPL29 = 9, /* Digital Active - tcpwm[1].line_compl[29]:1 */ 3556 P22_6_TCPWM1_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[84]:1 */ 3557 P22_6_TCPWM1_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[88]:1 */ 3558 P22_6_TCPWM1_LINE_COMPL520 = 16, /* Digital Active - tcpwm[1].line_compl[520]:0 */ 3559 P22_6_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:1 */ 3560 3561 /* P22.7 */ 3562 P22_7_GPIO = 0, /* GPIO controls 'out' */ 3563 P22_7_AMUXA = 4, /* Analog mux bus A */ 3564 P22_7_AMUXB = 5, /* Analog mux bus B */ 3565 P22_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3566 P22_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3567 P22_7_TCPWM1_LINE27 = 8, /* Digital Active - tcpwm[1].line[27]:1 */ 3568 P22_7_TCPWM1_LINE_COMPL28 = 9, /* Digital Active - tcpwm[1].line_compl[28]:1 */ 3569 P22_7_TCPWM1_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[81]:1 */ 3570 P22_7_TCPWM1_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[85]:1 */ 3571 P22_7_TCPWM1_TR_ONE_CNT_IN1560 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1560]:0 */ 3572 P22_7_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:1 */ 3573 P22_7_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:1 */ 3574 3575 /* P23.0 */ 3576 P23_0_GPIO = 0, /* GPIO controls 'out' */ 3577 P23_0_AMUXA = 4, /* Analog mux bus A */ 3578 P23_0_AMUXB = 5, /* Analog mux bus B */ 3579 P23_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3580 P23_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3581 P23_0_TCPWM1_LINE264 = 8, /* Digital Active - tcpwm[1].line[264]:1 */ 3582 P23_0_TCPWM1_LINE_COMPL27 = 9, /* Digital Active - tcpwm[1].line_compl[27]:1 */ 3583 P23_0_TCPWM1_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[792]:1 */ 3584 P23_0_TCPWM1_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[82]:1 */ 3585 P23_0_TCPWM1_TR_ONE_CNT_IN1561 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1561]:0 */ 3586 P23_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:1 */ 3587 P23_0_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:1 */ 3588 P23_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:1 */ 3589 P23_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:1 */ 3590 P23_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:1 */ 3591 3592 /* P23.1 */ 3593 P23_1_GPIO = 0, /* GPIO controls 'out' */ 3594 P23_1_AMUXA = 4, /* Analog mux bus A */ 3595 P23_1_AMUXB = 5, /* Analog mux bus B */ 3596 P23_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3597 P23_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3598 P23_1_TCPWM1_LINE265 = 8, /* Digital Active - tcpwm[1].line[265]:1 */ 3599 P23_1_TCPWM1_LINE_COMPL264 = 9, /* Digital Active - tcpwm[1].line_compl[264]:1 */ 3600 P23_1_TCPWM1_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[795]:1 */ 3601 P23_1_TCPWM1_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[793]:1 */ 3602 P23_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:1 */ 3603 P23_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:1 */ 3604 P23_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:1 */ 3605 P23_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:1 */ 3606 P23_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:1 */ 3607 3608 /* P23.2 */ 3609 P23_2_GPIO = 0, /* GPIO controls 'out' */ 3610 P23_2_AMUXA = 4, /* Analog mux bus A */ 3611 P23_2_AMUXB = 5, /* Analog mux bus B */ 3612 P23_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3613 P23_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3614 P23_2_TCPWM1_LINE266 = 8, /* Digital Active - tcpwm[1].line[266]:1 */ 3615 P23_2_TCPWM1_LINE_COMPL265 = 9, /* Digital Active - tcpwm[1].line_compl[265]:1 */ 3616 P23_2_TCPWM1_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[798]:1 */ 3617 P23_2_TCPWM1_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[796]:1 */ 3618 P23_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:1 */ 3619 P23_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:1 */ 3620 P23_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:1 */ 3621 P23_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:2 */ 3622 P23_2_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:1 */ 3623 3624 /* P23.3 */ 3625 P23_3_GPIO = 0, /* GPIO controls 'out' */ 3626 P23_3_AMUXA = 4, /* Analog mux bus A */ 3627 P23_3_AMUXB = 5, /* Analog mux bus B */ 3628 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3629 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3630 P23_3_TCPWM1_LINE267 = 8, /* Digital Active - tcpwm[1].line[267]:1 */ 3631 P23_3_TCPWM1_LINE_COMPL266 = 9, /* Digital Active - tcpwm[1].line_compl[266]:1 */ 3632 P23_3_TCPWM1_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[801]:1 */ 3633 P23_3_TCPWM1_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[799]:1 */ 3634 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 3635 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 3636 P23_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:2 */ 3637 P23_3_ETH0_RX_CLK = 24, /* Digital Active - eth[0].rx_clk:0 */ 3638 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 3639 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 3640 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 3641 3642 /* P23.4 */ 3643 P23_4_GPIO = 0, /* GPIO controls 'out' */ 3644 P23_4_AMUXA = 4, /* Analog mux bus A */ 3645 P23_4_AMUXB = 5, /* Analog mux bus B */ 3646 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3647 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3648 P23_4_TCPWM1_LINE25 = 8, /* Digital Active - tcpwm[1].line[25]:1 */ 3649 P23_4_TCPWM1_LINE_COMPL267 = 9, /* Digital Active - tcpwm[1].line_compl[267]:1 */ 3650 P23_4_TCPWM1_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[75]:1 */ 3651 P23_4_TCPWM1_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[802]:1 */ 3652 P23_4_TCPWM1_LINE521 = 16, /* Digital Active - tcpwm[1].line[521]:0 */ 3653 P23_4_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:2 */ 3654 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 3655 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 3656 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 3657 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 3658 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 3659 3660 /* P23.5 */ 3661 P23_5_GPIO = 0, /* GPIO controls 'out' */ 3662 P23_5_AMUXA = 4, /* Analog mux bus A */ 3663 P23_5_AMUXB = 5, /* Analog mux bus B */ 3664 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3665 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3666 P23_5_TCPWM1_LINE24 = 8, /* Digital Active - tcpwm[1].line[24]:1 */ 3667 P23_5_TCPWM1_LINE_COMPL25 = 9, /* Digital Active - tcpwm[1].line_compl[25]:1 */ 3668 P23_5_TCPWM1_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[72]:1 */ 3669 P23_5_TCPWM1_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[76]:1 */ 3670 P23_5_TCPWM1_LINE_COMPL521 = 16, /* Digital Active - tcpwm[1].line_compl[521]:0 */ 3671 P23_5_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:2 */ 3672 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 3673 P23_5_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:0 */ 3674 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 3675 3676 /* P23.6 */ 3677 P23_6_GPIO = 0, /* GPIO controls 'out' */ 3678 P23_6_AMUXA = 4, /* Analog mux bus A */ 3679 P23_6_AMUXB = 5, /* Analog mux bus B */ 3680 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3681 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3682 P23_6_TCPWM1_LINE23 = 8, /* Digital Active - tcpwm[1].line[23]:1 */ 3683 P23_6_TCPWM1_LINE_COMPL24 = 9, /* Digital Active - tcpwm[1].line_compl[24]:1 */ 3684 P23_6_TCPWM1_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[69]:1 */ 3685 P23_6_TCPWM1_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[73]:1 */ 3686 P23_6_TCPWM1_TR_ONE_CNT_IN1563 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1563]:0 */ 3687 P23_6_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:2 */ 3688 P23_6_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:0 */ 3689 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 3690 3691 /* P23.7 */ 3692 P23_7_GPIO = 0, /* GPIO controls 'out' */ 3693 P23_7_AMUXA = 4, /* Analog mux bus A */ 3694 P23_7_AMUXB = 5, /* Analog mux bus B */ 3695 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3696 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3697 P23_7_TCPWM1_LINE22 = 8, /* Digital Active - tcpwm[1].line[22]:1 */ 3698 P23_7_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:1 */ 3699 P23_7_TCPWM1_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[66]:1 */ 3700 P23_7_TCPWM1_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[70]:1 */ 3701 P23_7_TCPWM1_TR_ONE_CNT_IN1564 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1564]:0 */ 3702 P23_7_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:2 */ 3703 P23_7_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:1 */ 3704 P23_7_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:0 */ 3705 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 3706 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 3707 P23_7_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 3708 3709 /* P24.0 */ 3710 P24_0_GPIO = 0, /* GPIO controls 'out' */ 3711 P24_0_AMUXA = 4, /* Analog mux bus A */ 3712 P24_0_AMUXB = 5, /* Analog mux bus B */ 3713 P24_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3714 P24_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3715 P24_0_LIN0_LIN_RX16 = 20, /* Digital Active - lin[0].lin_rx[16]:0 */ 3716 P24_0_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:2 */ 3717 P24_0_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:1 */ 3718 3719 /* P24.1 */ 3720 P24_1_GPIO = 0, /* GPIO controls 'out' */ 3721 P24_1_AMUXA = 4, /* Analog mux bus A */ 3722 P24_1_AMUXB = 5, /* Analog mux bus B */ 3723 P24_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3724 P24_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3725 P24_1_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:1 */ 3726 P24_1_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:1 */ 3727 3728 /* P24.2 */ 3729 P24_2_GPIO = 0, /* GPIO controls 'out' */ 3730 P24_2_AMUXA = 4, /* Analog mux bus A */ 3731 P24_2_AMUXB = 5, /* Analog mux bus B */ 3732 P24_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3733 P24_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3734 P24_2_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:1 */ 3735 P24_2_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:1 */ 3736 3737 /* P24.3 */ 3738 P24_3_GPIO = 0, /* GPIO controls 'out' */ 3739 P24_3_AMUXA = 4, /* Analog mux bus A */ 3740 P24_3_AMUXB = 5, /* Analog mux bus B */ 3741 P24_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3742 P24_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3743 P24_3_LIN0_LIN_TX16 = 20, /* Digital Active - lin[0].lin_tx[16]:0 */ 3744 P24_3_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:1 */ 3745 P24_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:1 */ 3746 3747 /* P24.4 */ 3748 P24_4_GPIO = 0, /* GPIO controls 'out' */ 3749 P24_4_AMUXA = 4, /* Analog mux bus A */ 3750 P24_4_AMUXB = 5, /* Analog mux bus B */ 3751 P24_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3752 P24_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3753 P24_4_LIN0_LIN_EN16 = 20, /* Digital Active - lin[0].lin_en[16]:0 */ 3754 P24_4_SRSS_DDFT_CLK_DIRECT = 22, /* Digital Active - srss.ddft_clk_direct */ 3755 P24_4_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:1 */ 3756 P24_4_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:1 */ 3757 3758 /* P25.0 */ 3759 P25_0_GPIO = 0, /* GPIO controls 'out' */ 3760 P25_0_AMUXA = 4, /* Analog mux bus A */ 3761 P25_0_AMUXB = 5, /* Analog mux bus B */ 3762 P25_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3763 P25_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3764 P25_0_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:1 */ 3765 P25_0_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:1 */ 3766 3767 /* P25.1 */ 3768 P25_1_GPIO = 0, /* GPIO controls 'out' */ 3769 P25_1_AMUXA = 4, /* Analog mux bus A */ 3770 P25_1_AMUXB = 5, /* Analog mux bus B */ 3771 P25_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3772 P25_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3773 P25_1_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:1 */ 3774 P25_1_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:1 */ 3775 3776 /* P25.2 */ 3777 P25_2_GPIO = 0, /* GPIO controls 'out' */ 3778 P25_2_AMUXA = 4, /* Analog mux bus A */ 3779 P25_2_AMUXB = 5, /* Analog mux bus B */ 3780 P25_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3781 P25_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3782 P25_2_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:1 */ 3783 P25_2_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:1 */ 3784 3785 /* P25.3 */ 3786 P25_3_GPIO = 0, /* GPIO controls 'out' */ 3787 P25_3_AMUXA = 4, /* Analog mux bus A */ 3788 P25_3_AMUXB = 5, /* Analog mux bus B */ 3789 P25_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3790 P25_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3791 P25_3_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:1 */ 3792 P25_3_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:1 */ 3793 3794 /* P25.4 */ 3795 P25_4_GPIO = 0, /* GPIO controls 'out' */ 3796 P25_4_AMUXA = 4, /* Analog mux bus A */ 3797 P25_4_AMUXB = 5, /* Analog mux bus B */ 3798 P25_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3799 P25_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3800 P25_4_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:1 */ 3801 P25_4_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:1 */ 3802 3803 /* P25.5 */ 3804 P25_5_GPIO = 0, /* GPIO controls 'out' */ 3805 P25_5_AMUXA = 4, /* Analog mux bus A */ 3806 P25_5_AMUXB = 5, /* Analog mux bus B */ 3807 P25_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3808 P25_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3809 P25_5_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:1 */ 3810 P25_5_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:1 */ 3811 3812 /* P25.6 */ 3813 P25_6_GPIO = 0, /* GPIO controls 'out' */ 3814 P25_6_AMUXA = 4, /* Analog mux bus A */ 3815 P25_6_AMUXB = 5, /* Analog mux bus B */ 3816 P25_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3817 P25_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3818 P25_6_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:1 */ 3819 P25_6_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:1 */ 3820 3821 /* P25.7 */ 3822 P25_7_GPIO = 0, /* GPIO controls 'out' */ 3823 P25_7_AMUXA = 4, /* Analog mux bus A */ 3824 P25_7_AMUXB = 5, /* Analog mux bus B */ 3825 P25_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3826 P25_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3827 P25_7_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:1 */ 3828 P25_7_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:1 */ 3829 3830 /* P26.0 */ 3831 P26_0_GPIO = 0, /* GPIO controls 'out' */ 3832 P26_0_AMUXA = 4, /* Analog mux bus A */ 3833 P26_0_AMUXB = 5, /* Analog mux bus B */ 3834 P26_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3835 P26_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3836 P26_0_ETH1_REF_CLK = 27, /* Digital Active - eth[1].ref_clk:0 */ 3837 3838 /* P26.1 */ 3839 P26_1_GPIO = 0, /* GPIO controls 'out' */ 3840 P26_1_AMUXA = 4, /* Analog mux bus A */ 3841 P26_1_AMUXB = 5, /* Analog mux bus B */ 3842 P26_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3843 P26_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3844 P26_1_ETH1_TX_CTL = 27, /* Digital Active - eth[1].tx_ctl:0 */ 3845 3846 /* P26.2 */ 3847 P26_2_GPIO = 0, /* GPIO controls 'out' */ 3848 P26_2_AMUXA = 4, /* Analog mux bus A */ 3849 P26_2_AMUXB = 5, /* Analog mux bus B */ 3850 P26_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3851 P26_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3852 P26_2_ETH1_TX_CLK = 27, /* Digital Active - eth[1].tx_clk:0 */ 3853 3854 /* P26.3 */ 3855 P26_3_GPIO = 0, /* GPIO controls 'out' */ 3856 P26_3_AMUXA = 4, /* Analog mux bus A */ 3857 P26_3_AMUXB = 5, /* Analog mux bus B */ 3858 P26_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3859 P26_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3860 P26_3_ETH1_TXD0 = 27, /* Digital Active - eth[1].txd[0]:0 */ 3861 3862 /* P26.4 */ 3863 P26_4_GPIO = 0, /* GPIO controls 'out' */ 3864 P26_4_AMUXA = 4, /* Analog mux bus A */ 3865 P26_4_AMUXB = 5, /* Analog mux bus B */ 3866 P26_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3867 P26_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3868 P26_4_ETH1_TXD1 = 27, /* Digital Active - eth[1].txd[1]:0 */ 3869 3870 /* P26.5 */ 3871 P26_5_GPIO = 0, /* GPIO controls 'out' */ 3872 P26_5_AMUXA = 4, /* Analog mux bus A */ 3873 P26_5_AMUXB = 5, /* Analog mux bus B */ 3874 P26_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3875 P26_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3876 P26_5_ETH1_TXD2 = 27, /* Digital Active - eth[1].txd[2]:0 */ 3877 3878 /* P26.6 */ 3879 P26_6_GPIO = 0, /* GPIO controls 'out' */ 3880 P26_6_AMUXA = 4, /* Analog mux bus A */ 3881 P26_6_AMUXB = 5, /* Analog mux bus B */ 3882 P26_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3883 P26_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3884 P26_6_ETH1_TXD3 = 27, /* Digital Active - eth[1].txd[3]:0 */ 3885 3886 /* P26.7 */ 3887 P26_7_GPIO = 0, /* GPIO controls 'out' */ 3888 P26_7_AMUXA = 4, /* Analog mux bus A */ 3889 P26_7_AMUXB = 5, /* Analog mux bus B */ 3890 P26_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3891 P26_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3892 P26_7_ETH1_RXD0 = 27, /* Digital Active - eth[1].rxd[0]:0 */ 3893 3894 /* P27.0 */ 3895 P27_0_GPIO = 0, /* GPIO controls 'out' */ 3896 P27_0_AMUXA = 4, /* Analog mux bus A */ 3897 P27_0_AMUXB = 5, /* Analog mux bus B */ 3898 P27_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3899 P27_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3900 P27_0_ETH1_RXD1 = 27, /* Digital Active - eth[1].rxd[1]:0 */ 3901 3902 /* P27.1 */ 3903 P27_1_GPIO = 0, /* GPIO controls 'out' */ 3904 P27_1_AMUXA = 4, /* Analog mux bus A */ 3905 P27_1_AMUXB = 5, /* Analog mux bus B */ 3906 P27_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3907 P27_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3908 P27_1_ETH1_RXD2 = 27, /* Digital Active - eth[1].rxd[2]:0 */ 3909 3910 /* P27.2 */ 3911 P27_2_GPIO = 0, /* GPIO controls 'out' */ 3912 P27_2_AMUXA = 4, /* Analog mux bus A */ 3913 P27_2_AMUXB = 5, /* Analog mux bus B */ 3914 P27_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3915 P27_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3916 P27_2_ETH1_RXD3 = 27, /* Digital Active - eth[1].rxd[3]:0 */ 3917 3918 /* P27.3 */ 3919 P27_3_GPIO = 0, /* GPIO controls 'out' */ 3920 P27_3_AMUXA = 4, /* Analog mux bus A */ 3921 P27_3_AMUXB = 5, /* Analog mux bus B */ 3922 P27_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3923 P27_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3924 P27_3_ETH1_RX_CTL = 27, /* Digital Active - eth[1].rx_ctl:0 */ 3925 3926 /* P27.4 */ 3927 P27_4_GPIO = 0, /* GPIO controls 'out' */ 3928 P27_4_AMUXA = 4, /* Analog mux bus A */ 3929 P27_4_AMUXB = 5, /* Analog mux bus B */ 3930 P27_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3931 P27_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3932 P27_4_ETH1_RX_CLK = 27, /* Digital Active - eth[1].rx_clk:0 */ 3933 3934 /* P27.5 */ 3935 P27_5_GPIO = 0, /* GPIO controls 'out' */ 3936 P27_5_AMUXA = 4, /* Analog mux bus A */ 3937 P27_5_AMUXB = 5, /* Analog mux bus B */ 3938 P27_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3939 P27_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3940 P27_5_ETH1_MDIO = 27, /* Digital Active - eth[1].mdio:0 */ 3941 3942 /* P27.6 */ 3943 P27_6_GPIO = 0, /* GPIO controls 'out' */ 3944 P27_6_AMUXA = 4, /* Analog mux bus A */ 3945 P27_6_AMUXB = 5, /* Analog mux bus B */ 3946 P27_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3947 P27_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3948 P27_6_ETH1_MDC = 27, /* Digital Active - eth[1].mdc:0 */ 3949 3950 /* P27.7 */ 3951 P27_7_GPIO = 0, /* GPIO controls 'out' */ 3952 P27_7_AMUXA = 4, /* Analog mux bus A */ 3953 P27_7_AMUXB = 5, /* Analog mux bus B */ 3954 P27_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3955 P27_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3956 P27_7_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:1 */ 3957 P27_7_ETH1_ETH_TSU_TIMER_CMP_VAL = 27, /* Digital Active - eth[1].eth_tsu_timer_cmp_val:0 */ 3958 3959 /* P28.0 */ 3960 P28_0_GPIO = 0, /* GPIO controls 'out' */ 3961 P28_0_AMUXA = 4, /* Analog mux bus A */ 3962 P28_0_AMUXB = 5, /* Analog mux bus B */ 3963 P28_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3964 P28_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3965 P28_0_TCPWM1_LINE63 = 8, /* Digital Active - tcpwm[1].line[63]:0 */ 3966 P28_0_TCPWM1_LINE_COMPL65 = 9, /* Digital Active - tcpwm[1].line_compl[65]:1 */ 3967 P28_0_TCPWM1_TR_ONE_CNT_IN189 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[189]:0 */ 3968 P28_0_TCPWM1_TR_ONE_CNT_IN196 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[196]:1 */ 3969 P28_0_TCPWM1_LINE524 = 16, /* Digital Active - tcpwm[1].line[524]:1 */ 3970 P28_0_SCB10_UART_RX = 17, /* Digital Active - scb[10].uart_rx:0 */ 3971 P28_0_SCB10_SPI_MISO = 19, /* Digital Active - scb[10].spi_miso:0 */ 3972 3973 /* P28.1 */ 3974 P28_1_GPIO = 0, /* GPIO controls 'out' */ 3975 P28_1_AMUXA = 4, /* Analog mux bus A */ 3976 P28_1_AMUXB = 5, /* Analog mux bus B */ 3977 P28_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3978 P28_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3979 P28_1_TCPWM1_LINE64 = 8, /* Digital Active - tcpwm[1].line[64]:0 */ 3980 P28_1_TCPWM1_LINE_COMPL63 = 9, /* Digital Active - tcpwm[1].line_compl[63]:0 */ 3981 P28_1_TCPWM1_TR_ONE_CNT_IN192 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[192]:0 */ 3982 P28_1_TCPWM1_TR_ONE_CNT_IN190 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[190]:0 */ 3983 P28_1_TCPWM1_LINE_COMPL524 = 16, /* Digital Active - tcpwm[1].line_compl[524]:1 */ 3984 P28_1_SCB10_UART_TX = 17, /* Digital Active - scb[10].uart_tx:0 */ 3985 P28_1_SCB10_I2C_SDA = 18, /* Digital Active - scb[10].i2c_sda:0 */ 3986 P28_1_SCB10_SPI_MOSI = 19, /* Digital Active - scb[10].spi_mosi:0 */ 3987 P28_1_LIN0_LIN_RX17 = 20, /* Digital Active - lin[0].lin_rx[17]:0 */ 3988 3989 /* P28.2 */ 3990 P28_2_GPIO = 0, /* GPIO controls 'out' */ 3991 P28_2_AMUXA = 4, /* Analog mux bus A */ 3992 P28_2_AMUXB = 5, /* Analog mux bus B */ 3993 P28_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3994 P28_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3995 P28_2_TCPWM1_LINE65 = 8, /* Digital Active - tcpwm[1].line[65]:0 */ 3996 P28_2_TCPWM1_LINE_COMPL64 = 9, /* Digital Active - tcpwm[1].line_compl[64]:0 */ 3997 P28_2_TCPWM1_TR_ONE_CNT_IN195 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[195]:0 */ 3998 P28_2_TCPWM1_TR_ONE_CNT_IN193 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[193]:0 */ 3999 P28_2_TCPWM1_TR_ONE_CNT_IN1572 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1572]:1 */ 4000 P28_2_SCB10_UART_RTS = 17, /* Digital Active - scb[10].uart_rts:0 */ 4001 P28_2_SCB10_I2C_SCL = 18, /* Digital Active - scb[10].i2c_scl:0 */ 4002 P28_2_SCB10_SPI_CLK = 19, /* Digital Active - scb[10].spi_clk:0 */ 4003 P28_2_LIN0_LIN_TX17 = 20, /* Digital Active - lin[0].lin_tx[17]:0 */ 4004 4005 /* P28.3 */ 4006 P28_3_GPIO = 0, /* GPIO controls 'out' */ 4007 P28_3_AMUXA = 4, /* Analog mux bus A */ 4008 P28_3_AMUXB = 5, /* Analog mux bus B */ 4009 P28_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4010 P28_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4011 P28_3_TCPWM1_LINE66 = 8, /* Digital Active - tcpwm[1].line[66]:0 */ 4012 P28_3_TCPWM1_LINE_COMPL65 = 9, /* Digital Active - tcpwm[1].line_compl[65]:0 */ 4013 P28_3_TCPWM1_TR_ONE_CNT_IN198 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[198]:0 */ 4014 P28_3_TCPWM1_TR_ONE_CNT_IN196 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[196]:0 */ 4015 P28_3_TCPWM1_TR_ONE_CNT_IN1573 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1573]:1 */ 4016 P28_3_SCB10_UART_CTS = 17, /* Digital Active - scb[10].uart_cts:0 */ 4017 P28_3_SCB10_SPI_SELECT0 = 19, /* Digital Active - scb[10].spi_select0:0 */ 4018 P28_3_LIN0_LIN_EN17 = 20, /* Digital Active - lin[0].lin_en[17]:0 */ 4019 4020 /* P28.4 */ 4021 P28_4_GPIO = 0, /* GPIO controls 'out' */ 4022 P28_4_AMUXA = 4, /* Analog mux bus A */ 4023 P28_4_AMUXB = 5, /* Analog mux bus B */ 4024 P28_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4025 P28_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4026 P28_4_TCPWM1_LINE67 = 8, /* Digital Active - tcpwm[1].line[67]:0 */ 4027 P28_4_TCPWM1_LINE_COMPL66 = 9, /* Digital Active - tcpwm[1].line_compl[66]:0 */ 4028 P28_4_TCPWM1_TR_ONE_CNT_IN201 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[201]:0 */ 4029 P28_4_TCPWM1_TR_ONE_CNT_IN199 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[199]:0 */ 4030 P28_4_SCB10_SPI_SELECT1 = 19, /* Digital Active - scb[10].spi_select1:0 */ 4031 P28_4_LIN0_LIN_RX18 = 20, /* Digital Active - lin[0].lin_rx[18]:0 */ 4032 4033 /* P28.5 */ 4034 P28_5_GPIO = 0, /* GPIO controls 'out' */ 4035 P28_5_AMUXA = 4, /* Analog mux bus A */ 4036 P28_5_AMUXB = 5, /* Analog mux bus B */ 4037 P28_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4038 P28_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4039 P28_5_TCPWM1_LINE68 = 8, /* Digital Active - tcpwm[1].line[68]:0 */ 4040 P28_5_TCPWM1_LINE_COMPL67 = 9, /* Digital Active - tcpwm[1].line_compl[67]:0 */ 4041 P28_5_TCPWM1_TR_ONE_CNT_IN204 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[204]:0 */ 4042 P28_5_TCPWM1_TR_ONE_CNT_IN202 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[202]:0 */ 4043 P28_5_SCB10_SPI_SELECT2 = 19, /* Digital Active - scb[10].spi_select2:0 */ 4044 P28_5_LIN0_LIN_TX18 = 20, /* Digital Active - lin[0].lin_tx[18]:0 */ 4045 4046 /* P28.6 */ 4047 P28_6_GPIO = 0, /* GPIO controls 'out' */ 4048 P28_6_AMUXA = 4, /* Analog mux bus A */ 4049 P28_6_AMUXB = 5, /* Analog mux bus B */ 4050 P28_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4051 P28_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4052 P28_6_TCPWM1_LINE69 = 8, /* Digital Active - tcpwm[1].line[69]:0 */ 4053 P28_6_TCPWM1_LINE_COMPL68 = 9, /* Digital Active - tcpwm[1].line_compl[68]:0 */ 4054 P28_6_TCPWM1_TR_ONE_CNT_IN207 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[207]:0 */ 4055 P28_6_TCPWM1_TR_ONE_CNT_IN205 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[205]:0 */ 4056 P28_6_SCB10_SPI_SELECT3 = 19, /* Digital Active - scb[10].spi_select3:0 */ 4057 P28_6_LIN0_LIN_EN18 = 20, /* Digital Active - lin[0].lin_en[18]:0 */ 4058 4059 /* P28.7 */ 4060 P28_7_GPIO = 0, /* GPIO controls 'out' */ 4061 P28_7_AMUXA = 4, /* Analog mux bus A */ 4062 P28_7_AMUXB = 5, /* Analog mux bus B */ 4063 P28_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4064 P28_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4065 P28_7_TCPWM1_LINE70 = 8, /* Digital Active - tcpwm[1].line[70]:0 */ 4066 P28_7_TCPWM1_LINE_COMPL69 = 9, /* Digital Active - tcpwm[1].line_compl[69]:0 */ 4067 P28_7_TCPWM1_TR_ONE_CNT_IN210 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[210]:0 */ 4068 P28_7_TCPWM1_TR_ONE_CNT_IN208 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[208]:0 */ 4069 P28_7_LIN0_LIN_RX19 = 20, /* Digital Active - lin[0].lin_rx[19]:0 */ 4070 4071 /* P29.0 */ 4072 P29_0_GPIO = 0, /* GPIO controls 'out' */ 4073 P29_0_AMUXA = 4, /* Analog mux bus A */ 4074 P29_0_AMUXB = 5, /* Analog mux bus B */ 4075 P29_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4076 P29_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4077 P29_0_TCPWM1_LINE76 = 8, /* Digital Active - tcpwm[1].line[76]:0 */ 4078 P29_0_TCPWM1_LINE_COMPL75 = 9, /* Digital Active - tcpwm[1].line_compl[75]:0 */ 4079 P29_0_TCPWM1_TR_ONE_CNT_IN228 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[228]:0 */ 4080 P29_0_TCPWM1_TR_ONE_CNT_IN226 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[226]:0 */ 4081 P29_0_LIN0_LIN_TX19 = 20, /* Digital Active - lin[0].lin_tx[19]:0 */ 4082 4083 /* P29.1 */ 4084 P29_1_GPIO = 0, /* GPIO controls 'out' */ 4085 P29_1_AMUXA = 4, /* Analog mux bus A */ 4086 P29_1_AMUXB = 5, /* Analog mux bus B */ 4087 P29_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4088 P29_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4089 P29_1_TCPWM1_LINE77 = 8, /* Digital Active - tcpwm[1].line[77]:0 */ 4090 P29_1_TCPWM1_LINE_COMPL76 = 9, /* Digital Active - tcpwm[1].line_compl[76]:0 */ 4091 P29_1_TCPWM1_TR_ONE_CNT_IN231 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[231]:0 */ 4092 P29_1_TCPWM1_TR_ONE_CNT_IN229 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[229]:0 */ 4093 P29_1_LIN0_LIN_EN19 = 20, /* Digital Active - lin[0].lin_en[19]:0 */ 4094 4095 /* P29.2 */ 4096 P29_2_GPIO = 0, /* GPIO controls 'out' */ 4097 P29_2_AMUXA = 4, /* Analog mux bus A */ 4098 P29_2_AMUXB = 5, /* Analog mux bus B */ 4099 P29_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4100 P29_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4101 P29_2_TCPWM1_LINE78 = 8, /* Digital Active - tcpwm[1].line[78]:0 */ 4102 P29_2_TCPWM1_LINE_COMPL77 = 9, /* Digital Active - tcpwm[1].line_compl[77]:0 */ 4103 P29_2_TCPWM1_TR_ONE_CNT_IN234 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[234]:0 */ 4104 P29_2_TCPWM1_TR_ONE_CNT_IN232 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[232]:0 */ 4105 4106 /* P29.3 */ 4107 P29_3_GPIO = 0, /* GPIO controls 'out' */ 4108 P29_3_AMUXA = 4, /* Analog mux bus A */ 4109 P29_3_AMUXB = 5, /* Analog mux bus B */ 4110 P29_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4111 P29_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4112 P29_3_TCPWM1_LINE79 = 8, /* Digital Active - tcpwm[1].line[79]:0 */ 4113 P29_3_TCPWM1_LINE_COMPL78 = 9, /* Digital Active - tcpwm[1].line_compl[78]:0 */ 4114 P29_3_TCPWM1_TR_ONE_CNT_IN237 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[237]:0 */ 4115 P29_3_TCPWM1_TR_ONE_CNT_IN235 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[235]:0 */ 4116 4117 /* P29.4 */ 4118 P29_4_GPIO = 0, /* GPIO controls 'out' */ 4119 P29_4_AMUXA = 4, /* Analog mux bus A */ 4120 P29_4_AMUXB = 5, /* Analog mux bus B */ 4121 P29_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4122 P29_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4123 P29_4_TCPWM1_LINE80 = 8, /* Digital Active - tcpwm[1].line[80]:0 */ 4124 P29_4_TCPWM1_LINE_COMPL79 = 9, /* Digital Active - tcpwm[1].line_compl[79]:0 */ 4125 P29_4_TCPWM1_TR_ONE_CNT_IN240 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[240]:0 */ 4126 P29_4_TCPWM1_TR_ONE_CNT_IN238 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[238]:0 */ 4127 4128 /* P29.5 */ 4129 P29_5_GPIO = 0, /* GPIO controls 'out' */ 4130 P29_5_AMUXA = 4, /* Analog mux bus A */ 4131 P29_5_AMUXB = 5, /* Analog mux bus B */ 4132 P29_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4133 P29_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4134 P29_5_TCPWM1_LINE81 = 8, /* Digital Active - tcpwm[1].line[81]:0 */ 4135 P29_5_TCPWM1_LINE_COMPL80 = 9, /* Digital Active - tcpwm[1].line_compl[80]:0 */ 4136 P29_5_TCPWM1_TR_ONE_CNT_IN243 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[243]:0 */ 4137 P29_5_TCPWM1_TR_ONE_CNT_IN241 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[241]:0 */ 4138 4139 /* P29.6 */ 4140 P29_6_GPIO = 0, /* GPIO controls 'out' */ 4141 P29_6_AMUXA = 4, /* Analog mux bus A */ 4142 P29_6_AMUXB = 5, /* Analog mux bus B */ 4143 P29_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4144 P29_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4145 P29_6_TCPWM1_LINE82 = 8, /* Digital Active - tcpwm[1].line[82]:0 */ 4146 P29_6_TCPWM1_LINE_COMPL81 = 9, /* Digital Active - tcpwm[1].line_compl[81]:0 */ 4147 P29_6_TCPWM1_TR_ONE_CNT_IN246 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[246]:0 */ 4148 P29_6_TCPWM1_TR_ONE_CNT_IN244 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[244]:0 */ 4149 4150 /* P29.7 */ 4151 P29_7_GPIO = 0, /* GPIO controls 'out' */ 4152 P29_7_AMUXA = 4, /* Analog mux bus A */ 4153 P29_7_AMUXB = 5, /* Analog mux bus B */ 4154 P29_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4155 P29_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4156 P29_7_TCPWM1_LINE83 = 8, /* Digital Active - tcpwm[1].line[83]:0 */ 4157 P29_7_TCPWM1_LINE_COMPL82 = 9, /* Digital Active - tcpwm[1].line_compl[82]:0 */ 4158 P29_7_TCPWM1_TR_ONE_CNT_IN249 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[249]:0 */ 4159 P29_7_TCPWM1_TR_ONE_CNT_IN247 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[247]:0 */ 4160 4161 /* P30.0 */ 4162 P30_0_GPIO = 0, /* GPIO controls 'out' */ 4163 P30_0_AMUXA = 4, /* Analog mux bus A */ 4164 P30_0_AMUXB = 5, /* Analog mux bus B */ 4165 P30_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4166 P30_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4167 P30_0_TCPWM1_LINE83 = 8, /* Digital Active - tcpwm[1].line[83]:1 */ 4168 P30_0_TCPWM1_LINE_COMPL83 = 9, /* Digital Active - tcpwm[1].line_compl[83]:0 */ 4169 P30_0_TCPWM1_TR_ONE_CNT_IN249 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[249]:1 */ 4170 P30_0_TCPWM1_TR_ONE_CNT_IN250 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[250]:0 */ 4171 P30_0_SCB9_UART_RTS = 17, /* Digital Active - scb[9].uart_rts:1 */ 4172 P30_0_SCB9_I2C_SCL = 18, /* Digital Active - scb[9].i2c_scl:1 */ 4173 P30_0_SCB9_SPI_CLK = 19, /* Digital Active - scb[9].spi_clk:1 */ 4174 P30_0_PERI_TR_IO_INPUT34 = 26, /* Digital Active - peri.tr_io_input[34]:0 */ 4175 4176 /* P30.1 */ 4177 P30_1_GPIO = 0, /* GPIO controls 'out' */ 4178 P30_1_AMUXA = 4, /* Analog mux bus A */ 4179 P30_1_AMUXB = 5, /* Analog mux bus B */ 4180 P30_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4181 P30_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4182 P30_1_TCPWM1_LINE82 = 8, /* Digital Active - tcpwm[1].line[82]:1 */ 4183 P30_1_TCPWM1_LINE_COMPL83 = 9, /* Digital Active - tcpwm[1].line_compl[83]:1 */ 4184 P30_1_TCPWM1_TR_ONE_CNT_IN246 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[246]:1 */ 4185 P30_1_TCPWM1_TR_ONE_CNT_IN250 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[250]:1 */ 4186 P30_1_SCB9_UART_CTS = 17, /* Digital Active - scb[9].uart_cts:1 */ 4187 P30_1_SCB9_SPI_SELECT0 = 19, /* Digital Active - scb[9].spi_select0:1 */ 4188 P30_1_LIN0_LIN_RX16 = 20, /* Digital Active - lin[0].lin_rx[16]:2 */ 4189 P30_1_PERI_TR_IO_INPUT35 = 26, /* Digital Active - peri.tr_io_input[35]:0 */ 4190 4191 /* P30.2 */ 4192 P30_2_GPIO = 0, /* GPIO controls 'out' */ 4193 P30_2_AMUXA = 4, /* Analog mux bus A */ 4194 P30_2_AMUXB = 5, /* Analog mux bus B */ 4195 P30_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4196 P30_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4197 P30_2_TCPWM1_LINE81 = 8, /* Digital Active - tcpwm[1].line[81]:1 */ 4198 P30_2_TCPWM1_LINE_COMPL82 = 9, /* Digital Active - tcpwm[1].line_compl[82]:1 */ 4199 P30_2_TCPWM1_TR_ONE_CNT_IN243 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[243]:1 */ 4200 P30_2_TCPWM1_TR_ONE_CNT_IN247 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[247]:1 */ 4201 P30_2_SCB9_SPI_SELECT1 = 19, /* Digital Active - scb[9].spi_select1:1 */ 4202 P30_2_LIN0_LIN_TX16 = 20, /* Digital Active - lin[0].lin_tx[16]:2 */ 4203 P30_2_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:2 */ 4204 P30_2_PERI_TR_IO_INPUT36 = 26, /* Digital Active - peri.tr_io_input[36]:0 */ 4205 4206 /* P30.3 */ 4207 P30_3_GPIO = 0, /* GPIO controls 'out' */ 4208 P30_3_AMUXA = 4, /* Analog mux bus A */ 4209 P30_3_AMUXB = 5, /* Analog mux bus B */ 4210 P30_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4211 P30_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4212 P30_3_TCPWM1_LINE80 = 8, /* Digital Active - tcpwm[1].line[80]:1 */ 4213 P30_3_TCPWM1_LINE_COMPL81 = 9, /* Digital Active - tcpwm[1].line_compl[81]:1 */ 4214 P30_3_TCPWM1_TR_ONE_CNT_IN240 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[240]:1 */ 4215 P30_3_TCPWM1_TR_ONE_CNT_IN244 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[244]:1 */ 4216 P30_3_SCB9_SPI_SELECT2 = 19, /* Digital Active - scb[9].spi_select2:1 */ 4217 P30_3_LIN0_LIN_EN16 = 20, /* Digital Active - lin[0].lin_en[16]:2 */ 4218 P30_3_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:2 */ 4219 P30_3_PERI_TR_IO_INPUT37 = 26, /* Digital Active - peri.tr_io_input[37]:0 */ 4220 4221 /* P31.0 */ 4222 P31_0_GPIO = 0, /* GPIO controls 'out' */ 4223 P31_0_AMUXA = 4, /* Analog mux bus A */ 4224 P31_0_AMUXB = 5, /* Analog mux bus B */ 4225 P31_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4226 P31_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4227 P31_0_TCPWM1_LINE79 = 8, /* Digital Active - tcpwm[1].line[79]:1 */ 4228 P31_0_TCPWM1_LINE_COMPL80 = 9, /* Digital Active - tcpwm[1].line_compl[80]:1 */ 4229 P31_0_TCPWM1_TR_ONE_CNT_IN237 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[237]:1 */ 4230 P31_0_TCPWM1_TR_ONE_CNT_IN241 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[241]:1 */ 4231 P31_0_LIN0_LIN_RX17 = 20, /* Digital Active - lin[0].lin_rx[17]:1 */ 4232 4233 /* P31.1 */ 4234 P31_1_GPIO = 0, /* GPIO controls 'out' */ 4235 P31_1_AMUXA = 4, /* Analog mux bus A */ 4236 P31_1_AMUXB = 5, /* Analog mux bus B */ 4237 P31_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4238 P31_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4239 P31_1_TCPWM1_LINE78 = 8, /* Digital Active - tcpwm[1].line[78]:1 */ 4240 P31_1_TCPWM1_LINE_COMPL79 = 9, /* Digital Active - tcpwm[1].line_compl[79]:1 */ 4241 P31_1_TCPWM1_TR_ONE_CNT_IN234 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[234]:1 */ 4242 P31_1_TCPWM1_TR_ONE_CNT_IN238 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[238]:1 */ 4243 P31_1_LIN0_LIN_TX17 = 20, /* Digital Active - lin[0].lin_tx[17]:1 */ 4244 4245 /* P31.2 */ 4246 P31_2_GPIO = 0, /* GPIO controls 'out' */ 4247 P31_2_AMUXA = 4, /* Analog mux bus A */ 4248 P31_2_AMUXB = 5, /* Analog mux bus B */ 4249 P31_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4250 P31_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4251 P31_2_TCPWM1_LINE77 = 8, /* Digital Active - tcpwm[1].line[77]:1 */ 4252 P31_2_TCPWM1_LINE_COMPL78 = 9, /* Digital Active - tcpwm[1].line_compl[78]:1 */ 4253 P31_2_TCPWM1_TR_ONE_CNT_IN231 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[231]:1 */ 4254 P31_2_TCPWM1_TR_ONE_CNT_IN235 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[235]:1 */ 4255 P31_2_LIN0_LIN_EN17 = 20, /* Digital Active - lin[0].lin_en[17]:1 */ 4256 4257 /* P32.0 */ 4258 P32_0_GPIO = 0, /* GPIO controls 'out' */ 4259 P32_0_AMUXA = 4, /* Analog mux bus A */ 4260 P32_0_AMUXB = 5, /* Analog mux bus B */ 4261 P32_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4262 P32_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4263 P32_0_TCPWM1_LINE76 = 8, /* Digital Active - tcpwm[1].line[76]:1 */ 4264 P32_0_TCPWM1_LINE_COMPL77 = 9, /* Digital Active - tcpwm[1].line_compl[77]:1 */ 4265 P32_0_TCPWM1_TR_ONE_CNT_IN228 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[228]:1 */ 4266 P32_0_TCPWM1_TR_ONE_CNT_IN232 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[232]:1 */ 4267 P32_0_SCB10_UART_RX = 17, /* Digital Active - scb[10].uart_rx:1 */ 4268 P32_0_SCB10_SPI_MISO = 19, /* Digital Active - scb[10].spi_miso:1 */ 4269 P32_0_PERI_TR_IO_INPUT40 = 26, /* Digital Active - peri.tr_io_input[40]:0 */ 4270 4271 /* P32.1 */ 4272 P32_1_GPIO = 0, /* GPIO controls 'out' */ 4273 P32_1_AMUXA = 4, /* Analog mux bus A */ 4274 P32_1_AMUXB = 5, /* Analog mux bus B */ 4275 P32_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4276 P32_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4277 P32_1_TCPWM1_LINE75 = 8, /* Digital Active - tcpwm[1].line[75]:1 */ 4278 P32_1_TCPWM1_LINE_COMPL76 = 9, /* Digital Active - tcpwm[1].line_compl[76]:1 */ 4279 P32_1_TCPWM1_TR_ONE_CNT_IN225 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[225]:1 */ 4280 P32_1_TCPWM1_TR_ONE_CNT_IN229 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[229]:1 */ 4281 P32_1_SCB10_UART_TX = 17, /* Digital Active - scb[10].uart_tx:1 */ 4282 P32_1_SCB10_I2C_SDA = 18, /* Digital Active - scb[10].i2c_sda:1 */ 4283 P32_1_SCB10_SPI_MOSI = 19, /* Digital Active - scb[10].spi_mosi:1 */ 4284 P32_1_PERI_TR_IO_INPUT41 = 26, /* Digital Active - peri.tr_io_input[41]:0 */ 4285 4286 /* P32.2 */ 4287 P32_2_GPIO = 0, /* GPIO controls 'out' */ 4288 P32_2_AMUXA = 4, /* Analog mux bus A */ 4289 P32_2_AMUXB = 5, /* Analog mux bus B */ 4290 P32_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4291 P32_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4292 P32_2_TCPWM1_LINE74 = 8, /* Digital Active - tcpwm[1].line[74]:1 */ 4293 P32_2_TCPWM1_LINE_COMPL75 = 9, /* Digital Active - tcpwm[1].line_compl[75]:1 */ 4294 P32_2_TCPWM1_TR_ONE_CNT_IN222 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[222]:1 */ 4295 P32_2_TCPWM1_TR_ONE_CNT_IN226 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[226]:1 */ 4296 P32_2_SCB10_UART_RTS = 17, /* Digital Active - scb[10].uart_rts:1 */ 4297 P32_2_SCB10_I2C_SCL = 18, /* Digital Active - scb[10].i2c_scl:1 */ 4298 P32_2_SCB10_SPI_CLK = 19, /* Digital Active - scb[10].spi_clk:1 */ 4299 P32_2_LIN0_LIN_RX18 = 20, /* Digital Active - lin[0].lin_rx[18]:1 */ 4300 P32_2_PERI_TR_IO_INPUT42 = 26, /* Digital Active - peri.tr_io_input[42]:0 */ 4301 4302 /* P32.3 */ 4303 P32_3_GPIO = 0, /* GPIO controls 'out' */ 4304 P32_3_AMUXA = 4, /* Analog mux bus A */ 4305 P32_3_AMUXB = 5, /* Analog mux bus B */ 4306 P32_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4307 P32_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4308 P32_3_TCPWM1_LINE73 = 8, /* Digital Active - tcpwm[1].line[73]:1 */ 4309 P32_3_TCPWM1_LINE_COMPL74 = 9, /* Digital Active - tcpwm[1].line_compl[74]:1 */ 4310 P32_3_TCPWM1_TR_ONE_CNT_IN219 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[219]:1 */ 4311 P32_3_TCPWM1_TR_ONE_CNT_IN223 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[223]:1 */ 4312 P32_3_SCB10_UART_CTS = 17, /* Digital Active - scb[10].uart_cts:1 */ 4313 P32_3_SCB10_SPI_SELECT0 = 19, /* Digital Active - scb[10].spi_select0:1 */ 4314 P32_3_LIN0_LIN_TX18 = 20, /* Digital Active - lin[0].lin_tx[18]:1 */ 4315 P32_3_PERI_TR_IO_INPUT43 = 26, /* Digital Active - peri.tr_io_input[43]:0 */ 4316 4317 /* P32.4 */ 4318 P32_4_GPIO = 0, /* GPIO controls 'out' */ 4319 P32_4_AMUXA = 4, /* Analog mux bus A */ 4320 P32_4_AMUXB = 5, /* Analog mux bus B */ 4321 P32_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4322 P32_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4323 P32_4_TCPWM1_LINE72 = 8, /* Digital Active - tcpwm[1].line[72]:1 */ 4324 P32_4_TCPWM1_LINE_COMPL73 = 9, /* Digital Active - tcpwm[1].line_compl[73]:1 */ 4325 P32_4_TCPWM1_TR_ONE_CNT_IN216 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[216]:1 */ 4326 P32_4_TCPWM1_TR_ONE_CNT_IN220 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[220]:1 */ 4327 P32_4_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:1 */ 4328 P32_4_SCB10_SPI_SELECT1 = 19, /* Digital Active - scb[10].spi_select1:1 */ 4329 P32_4_LIN0_LIN_EN18 = 20, /* Digital Active - lin[0].lin_en[18]:1 */ 4330 P32_4_PERI_TR_IO_INPUT44 = 26, /* Digital Active - peri.tr_io_input[44]:0 */ 4331 4332 /* P32.5 */ 4333 P32_5_GPIO = 0, /* GPIO controls 'out' */ 4334 P32_5_AMUXA = 4, /* Analog mux bus A */ 4335 P32_5_AMUXB = 5, /* Analog mux bus B */ 4336 P32_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4337 P32_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4338 P32_5_TCPWM1_LINE71 = 8, /* Digital Active - tcpwm[1].line[71]:1 */ 4339 P32_5_TCPWM1_LINE_COMPL72 = 9, /* Digital Active - tcpwm[1].line_compl[72]:1 */ 4340 P32_5_TCPWM1_TR_ONE_CNT_IN213 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[213]:1 */ 4341 P32_5_TCPWM1_TR_ONE_CNT_IN217 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[217]:1 */ 4342 P32_5_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:1 */ 4343 P32_5_SCB10_SPI_SELECT2 = 19, /* Digital Active - scb[10].spi_select2:1 */ 4344 P32_5_LIN0_LIN_RX19 = 20, /* Digital Active - lin[0].lin_rx[19]:1 */ 4345 P32_5_PERI_TR_IO_INPUT45 = 26, /* Digital Active - peri.tr_io_input[45]:0 */ 4346 4347 /* P32.6 */ 4348 P32_6_GPIO = 0, /* GPIO controls 'out' */ 4349 P32_6_AMUXA = 4, /* Analog mux bus A */ 4350 P32_6_AMUXB = 5, /* Analog mux bus B */ 4351 P32_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4352 P32_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4353 P32_6_TCPWM1_LINE70 = 8, /* Digital Active - tcpwm[1].line[70]:1 */ 4354 P32_6_TCPWM1_LINE_COMPL71 = 9, /* Digital Active - tcpwm[1].line_compl[71]:1 */ 4355 P32_6_TCPWM1_TR_ONE_CNT_IN210 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[210]:1 */ 4356 P32_6_TCPWM1_TR_ONE_CNT_IN214 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[214]:1 */ 4357 P32_6_LIN0_LIN_EN10 = 18, /* Digital Active - lin[0].lin_en[10]:1 */ 4358 P32_6_SCB10_SPI_SELECT3 = 19, /* Digital Active - scb[10].spi_select3:1 */ 4359 P32_6_LIN0_LIN_TX19 = 20, /* Digital Active - lin[0].lin_tx[19]:1 */ 4360 P32_6_CANFD1_TTCAN_TX4 = 21, /* Digital Active - canfd[1].ttcan_tx[4]:1 */ 4361 P32_6_PERI_TR_IO_INPUT46 = 26, /* Digital Active - peri.tr_io_input[46]:0 */ 4362 4363 /* P32.7 */ 4364 P32_7_GPIO = 0, /* GPIO controls 'out' */ 4365 P32_7_AMUXA = 4, /* Analog mux bus A */ 4366 P32_7_AMUXB = 5, /* Analog mux bus B */ 4367 P32_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4368 P32_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4369 P32_7_TCPWM1_LINE69 = 8, /* Digital Active - tcpwm[1].line[69]:1 */ 4370 P32_7_TCPWM1_LINE_COMPL70 = 9, /* Digital Active - tcpwm[1].line_compl[70]:1 */ 4371 P32_7_TCPWM1_TR_ONE_CNT_IN207 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[207]:1 */ 4372 P32_7_TCPWM1_TR_ONE_CNT_IN211 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[211]:1 */ 4373 P32_7_LIN0_LIN_EN19 = 20, /* Digital Active - lin[0].lin_en[19]:1 */ 4374 P32_7_CANFD1_TTCAN_RX4 = 21, /* Digital Active - canfd[1].ttcan_rx[4]:1 */ 4375 P32_7_PERI_TR_IO_INPUT47 = 26 /* Digital Active - peri.tr_io_input[47]:0 */ 4376 } en_hsiom_sel_t; 4377 4378 #endif /* _GPIO_XMC7200_272_BGA_H_ */ 4379 4380 4381 /* [] END OF FILE */ 4382
