1 /***************************************************************************//** 2 * \file gpio_xmc7100_272_bga.h 3 * 4 * \brief 5 * XMC7100 device GPIO header for 272-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_XMC7100_272_BGA_H_ 28 #define _GPIO_XMC7100_272_BGA_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA 44 #define CY_GPIO_PIN_COUNT 272u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_MAIN, 50 AMUXBUS_REGHC_ISENSE, 51 AMUXBUS_TEST, 52 AMUXBUS_TESTECT, 53 AMUXBUS_TESTSRSS, 54 }; 55 56 /* AMUX Splitter Controls */ 57 typedef enum 58 { 59 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_REGHC_ISENSE */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 0 (GPIO) */ 66 #define P0_0_PORT GPIO_PRT0 67 #define P0_0_PIN 0u 68 #define P0_0_NUM 0u 69 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 70 #define P0_1_PORT GPIO_PRT0 71 #define P0_1_PIN 1u 72 #define P0_1_NUM 1u 73 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 78 #define P0_3_PORT GPIO_PRT0 79 #define P0_3_PIN 3u 80 #define P0_3_NUM 3u 81 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 82 83 /* PORT 1 (GPIO) */ 84 #define P1_0_PORT GPIO_PRT1 85 #define P1_0_PIN 0u 86 #define P1_0_NUM 0u 87 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 88 #define P1_1_PORT GPIO_PRT1 89 #define P1_1_PIN 1u 90 #define P1_1_NUM 1u 91 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 92 #define P1_2_PORT GPIO_PRT1 93 #define P1_2_PIN 2u 94 #define P1_2_NUM 2u 95 #define P1_2_AMUXSEGMENT AMUXBUS_MAIN 96 #define P1_3_PORT GPIO_PRT1 97 #define P1_3_PIN 3u 98 #define P1_3_NUM 3u 99 #define P1_3_AMUXSEGMENT AMUXBUS_MAIN 100 #define P1_4_PORT GPIO_PRT1 101 #define P1_4_PIN 4u 102 #define P1_4_NUM 4u 103 #define P1_4_AMUXSEGMENT AMUXBUS_MAIN 104 105 /* PORT 2 (GPIO) */ 106 #define P2_0_PORT GPIO_PRT2 107 #define P2_0_PIN 0u 108 #define P2_0_NUM 0u 109 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 110 #define P2_1_PORT GPIO_PRT2 111 #define P2_1_PIN 1u 112 #define P2_1_NUM 1u 113 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 114 #define P2_2_PORT GPIO_PRT2 115 #define P2_2_PIN 2u 116 #define P2_2_NUM 2u 117 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 118 #define P2_3_PORT GPIO_PRT2 119 #define P2_3_PIN 3u 120 #define P2_3_NUM 3u 121 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 122 #define P2_4_PORT GPIO_PRT2 123 #define P2_4_PIN 4u 124 #define P2_4_NUM 4u 125 #define P2_4_AMUXSEGMENT AMUXBUS_MAIN 126 #define P2_5_PORT GPIO_PRT2 127 #define P2_5_PIN 5u 128 #define P2_5_NUM 5u 129 #define P2_5_AMUXSEGMENT AMUXBUS_MAIN 130 #define P2_6_PORT GPIO_PRT2 131 #define P2_6_PIN 6u 132 #define P2_6_NUM 6u 133 #define P2_6_AMUXSEGMENT AMUXBUS_MAIN 134 #define P2_7_PORT GPIO_PRT2 135 #define P2_7_PIN 7u 136 #define P2_7_NUM 7u 137 #define P2_7_AMUXSEGMENT AMUXBUS_MAIN 138 139 /* PORT 3 (GPIO) */ 140 #define P3_0_PORT GPIO_PRT3 141 #define P3_0_PIN 0u 142 #define P3_0_NUM 0u 143 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 144 #define P3_1_PORT GPIO_PRT3 145 #define P3_1_PIN 1u 146 #define P3_1_NUM 1u 147 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 148 #define P3_2_PORT GPIO_PRT3 149 #define P3_2_PIN 2u 150 #define P3_2_NUM 2u 151 #define P3_2_AMUXSEGMENT AMUXBUS_MAIN 152 #define P3_3_PORT GPIO_PRT3 153 #define P3_3_PIN 3u 154 #define P3_3_NUM 3u 155 #define P3_3_AMUXSEGMENT AMUXBUS_MAIN 156 #define P3_4_PORT GPIO_PRT3 157 #define P3_4_PIN 4u 158 #define P3_4_NUM 4u 159 #define P3_4_AMUXSEGMENT AMUXBUS_MAIN 160 #define P3_5_PORT GPIO_PRT3 161 #define P3_5_PIN 5u 162 #define P3_5_NUM 5u 163 #define P3_5_AMUXSEGMENT AMUXBUS_MAIN 164 #define P3_6_PORT GPIO_PRT3 165 #define P3_6_PIN 6u 166 #define P3_6_NUM 6u 167 #define P3_6_AMUXSEGMENT AMUXBUS_MAIN 168 #define P3_7_PORT GPIO_PRT3 169 #define P3_7_PIN 7u 170 #define P3_7_NUM 7u 171 #define P3_7_AMUXSEGMENT AMUXBUS_MAIN 172 173 /* PORT 4 (GPIO) */ 174 #define P4_0_PORT GPIO_PRT4 175 #define P4_0_PIN 0u 176 #define P4_0_NUM 0u 177 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 178 #define P4_1_PORT GPIO_PRT4 179 #define P4_1_PIN 1u 180 #define P4_1_NUM 1u 181 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 182 #define P4_2_PORT GPIO_PRT4 183 #define P4_2_PIN 2u 184 #define P4_2_NUM 2u 185 #define P4_2_AMUXSEGMENT AMUXBUS_MAIN 186 #define P4_3_PORT GPIO_PRT4 187 #define P4_3_PIN 3u 188 #define P4_3_NUM 3u 189 #define P4_3_AMUXSEGMENT AMUXBUS_MAIN 190 #define P4_4_PORT GPIO_PRT4 191 #define P4_4_PIN 4u 192 #define P4_4_NUM 4u 193 #define P4_4_AMUXSEGMENT AMUXBUS_MAIN 194 195 /* PORT 5 (GPIO) */ 196 #define P5_0_PORT GPIO_PRT5 197 #define P5_0_PIN 0u 198 #define P5_0_NUM 0u 199 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 200 #define P5_1_PORT GPIO_PRT5 201 #define P5_1_PIN 1u 202 #define P5_1_NUM 1u 203 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 204 #define P5_2_PORT GPIO_PRT5 205 #define P5_2_PIN 2u 206 #define P5_2_NUM 2u 207 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 208 #define P5_3_PORT GPIO_PRT5 209 #define P5_3_PIN 3u 210 #define P5_3_NUM 3u 211 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 212 #define P5_4_PORT GPIO_PRT5 213 #define P5_4_PIN 4u 214 #define P5_4_NUM 4u 215 #define P5_4_AMUXSEGMENT AMUXBUS_MAIN 216 #define P5_5_PORT GPIO_PRT5 217 #define P5_5_PIN 5u 218 #define P5_5_NUM 5u 219 #define P5_5_AMUXSEGMENT AMUXBUS_MAIN 220 221 /* PORT 6 (GPIO) */ 222 #define P6_0_PORT GPIO_PRT6 223 #define P6_0_PIN 0u 224 #define P6_0_NUM 0u 225 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 226 #define P6_1_PORT GPIO_PRT6 227 #define P6_1_PIN 1u 228 #define P6_1_NUM 1u 229 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 230 #define P6_2_PORT GPIO_PRT6 231 #define P6_2_PIN 2u 232 #define P6_2_NUM 2u 233 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 234 #define P6_3_PORT GPIO_PRT6 235 #define P6_3_PIN 3u 236 #define P6_3_NUM 3u 237 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 238 #define P6_4_PORT GPIO_PRT6 239 #define P6_4_PIN 4u 240 #define P6_4_NUM 4u 241 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 242 #define P6_5_PORT GPIO_PRT6 243 #define P6_5_PIN 5u 244 #define P6_5_NUM 5u 245 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 246 #define P6_6_PORT GPIO_PRT6 247 #define P6_6_PIN 6u 248 #define P6_6_NUM 6u 249 #define P6_6_AMUXSEGMENT AMUXBUS_MAIN 250 #define P6_7_PORT GPIO_PRT6 251 #define P6_7_PIN 7u 252 #define P6_7_NUM 7u 253 #define P6_7_AMUXSEGMENT AMUXBUS_MAIN 254 255 /* PORT 7 (GPIO) */ 256 #define P7_0_PORT GPIO_PRT7 257 #define P7_0_PIN 0u 258 #define P7_0_NUM 0u 259 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 260 #define P7_1_PORT GPIO_PRT7 261 #define P7_1_PIN 1u 262 #define P7_1_NUM 1u 263 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 264 #define P7_2_PORT GPIO_PRT7 265 #define P7_2_PIN 2u 266 #define P7_2_NUM 2u 267 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 268 #define P7_3_PORT GPIO_PRT7 269 #define P7_3_PIN 3u 270 #define P7_3_NUM 3u 271 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 272 #define P7_4_PORT GPIO_PRT7 273 #define P7_4_PIN 4u 274 #define P7_4_NUM 4u 275 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 276 #define P7_5_PORT GPIO_PRT7 277 #define P7_5_PIN 5u 278 #define P7_5_NUM 5u 279 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 280 #define P7_6_PORT GPIO_PRT7 281 #define P7_6_PIN 6u 282 #define P7_6_NUM 6u 283 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 284 #define P7_7_PORT GPIO_PRT7 285 #define P7_7_PIN 7u 286 #define P7_7_NUM 7u 287 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 288 289 /* PORT 8 (GPIO) */ 290 #define P8_0_PORT GPIO_PRT8 291 #define P8_0_PIN 0u 292 #define P8_0_NUM 0u 293 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 294 #define P8_1_PORT GPIO_PRT8 295 #define P8_1_PIN 1u 296 #define P8_1_NUM 1u 297 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 298 #define P8_2_PORT GPIO_PRT8 299 #define P8_2_PIN 2u 300 #define P8_2_NUM 2u 301 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 302 #define P8_3_PORT GPIO_PRT8 303 #define P8_3_PIN 3u 304 #define P8_3_NUM 3u 305 #define P8_3_AMUXSEGMENT AMUXBUS_MAIN 306 #define P8_4_PORT GPIO_PRT8 307 #define P8_4_PIN 4u 308 #define P8_4_NUM 4u 309 #define P8_4_AMUXSEGMENT AMUXBUS_MAIN 310 311 /* PORT 9 (GPIO) */ 312 #define P9_0_PORT GPIO_PRT9 313 #define P9_0_PIN 0u 314 #define P9_0_NUM 0u 315 #define P9_0_AMUXSEGMENT AMUXBUS_MAIN 316 #define P9_1_PORT GPIO_PRT9 317 #define P9_1_PIN 1u 318 #define P9_1_NUM 1u 319 #define P9_1_AMUXSEGMENT AMUXBUS_MAIN 320 #define P9_2_PORT GPIO_PRT9 321 #define P9_2_PIN 2u 322 #define P9_2_NUM 2u 323 #define P9_2_AMUXSEGMENT AMUXBUS_MAIN 324 #define P9_3_PORT GPIO_PRT9 325 #define P9_3_PIN 3u 326 #define P9_3_NUM 3u 327 #define P9_3_AMUXSEGMENT AMUXBUS_MAIN 328 329 /* PORT 10 (GPIO) */ 330 #define P10_0_PORT GPIO_PRT10 331 #define P10_0_PIN 0u 332 #define P10_0_NUM 0u 333 #define P10_0_AMUXSEGMENT AMUXBUS_MAIN 334 #define P10_1_PORT GPIO_PRT10 335 #define P10_1_PIN 1u 336 #define P10_1_NUM 1u 337 #define P10_1_AMUXSEGMENT AMUXBUS_MAIN 338 #define P10_2_PORT GPIO_PRT10 339 #define P10_2_PIN 2u 340 #define P10_2_NUM 2u 341 #define P10_2_AMUXSEGMENT AMUXBUS_MAIN 342 #define P10_3_PORT GPIO_PRT10 343 #define P10_3_PIN 3u 344 #define P10_3_NUM 3u 345 #define P10_3_AMUXSEGMENT AMUXBUS_MAIN 346 #define P10_4_PORT GPIO_PRT10 347 #define P10_4_PIN 4u 348 #define P10_4_NUM 4u 349 #define P10_4_AMUXSEGMENT AMUXBUS_MAIN 350 #define P10_5_PORT GPIO_PRT10 351 #define P10_5_PIN 5u 352 #define P10_5_NUM 5u 353 #define P10_5_AMUXSEGMENT AMUXBUS_MAIN 354 #define P10_6_PORT GPIO_PRT10 355 #define P10_6_PIN 6u 356 #define P10_6_NUM 6u 357 #define P10_6_AMUXSEGMENT AMUXBUS_MAIN 358 #define P10_7_PORT GPIO_PRT10 359 #define P10_7_PIN 7u 360 #define P10_7_NUM 7u 361 #define P10_7_AMUXSEGMENT AMUXBUS_MAIN 362 363 /* PORT 11 (GPIO) */ 364 #define P11_0_PORT GPIO_PRT11 365 #define P11_0_PIN 0u 366 #define P11_0_NUM 0u 367 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 368 #define P11_1_PORT GPIO_PRT11 369 #define P11_1_PIN 1u 370 #define P11_1_NUM 1u 371 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 372 #define P11_2_PORT GPIO_PRT11 373 #define P11_2_PIN 2u 374 #define P11_2_NUM 2u 375 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 376 377 /* PORT 12 (GPIO) */ 378 #define P12_0_PORT GPIO_PRT12 379 #define P12_0_PIN 0u 380 #define P12_0_NUM 0u 381 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 382 #define P12_1_PORT GPIO_PRT12 383 #define P12_1_PIN 1u 384 #define P12_1_NUM 1u 385 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 386 #define P12_2_PORT GPIO_PRT12 387 #define P12_2_PIN 2u 388 #define P12_2_NUM 2u 389 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 390 #define P12_3_PORT GPIO_PRT12 391 #define P12_3_PIN 3u 392 #define P12_3_NUM 3u 393 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 394 #define P12_4_PORT GPIO_PRT12 395 #define P12_4_PIN 4u 396 #define P12_4_NUM 4u 397 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 398 #define P12_5_PORT GPIO_PRT12 399 #define P12_5_PIN 5u 400 #define P12_5_NUM 5u 401 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 402 #define P12_6_PORT GPIO_PRT12 403 #define P12_6_PIN 6u 404 #define P12_6_NUM 6u 405 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 406 #define P12_7_PORT GPIO_PRT12 407 #define P12_7_PIN 7u 408 #define P12_7_NUM 7u 409 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 410 411 /* PORT 13 (GPIO) */ 412 #define P13_0_PORT GPIO_PRT13 413 #define P13_0_PIN 0u 414 #define P13_0_NUM 0u 415 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 416 #define P13_1_PORT GPIO_PRT13 417 #define P13_1_PIN 1u 418 #define P13_1_NUM 1u 419 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 420 #define P13_2_PORT GPIO_PRT13 421 #define P13_2_PIN 2u 422 #define P13_2_NUM 2u 423 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 424 #define P13_3_PORT GPIO_PRT13 425 #define P13_3_PIN 3u 426 #define P13_3_NUM 3u 427 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 428 #define P13_4_PORT GPIO_PRT13 429 #define P13_4_PIN 4u 430 #define P13_4_NUM 4u 431 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 432 #define P13_5_PORT GPIO_PRT13 433 #define P13_5_PIN 5u 434 #define P13_5_NUM 5u 435 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 436 #define P13_6_PORT GPIO_PRT13 437 #define P13_6_PIN 6u 438 #define P13_6_NUM 6u 439 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 440 #define P13_7_PORT GPIO_PRT13 441 #define P13_7_PIN 7u 442 #define P13_7_NUM 7u 443 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 444 445 /* PORT 14 (GPIO) */ 446 #define P14_0_PORT GPIO_PRT14 447 #define P14_0_PIN 0u 448 #define P14_0_NUM 0u 449 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 450 #define P14_1_PORT GPIO_PRT14 451 #define P14_1_PIN 1u 452 #define P14_1_NUM 1u 453 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 454 #define P14_2_PORT GPIO_PRT14 455 #define P14_2_PIN 2u 456 #define P14_2_NUM 2u 457 #define P14_2_AMUXSEGMENT AMUXBUS_MAIN 458 #define P14_3_PORT GPIO_PRT14 459 #define P14_3_PIN 3u 460 #define P14_3_NUM 3u 461 #define P14_3_AMUXSEGMENT AMUXBUS_MAIN 462 #define P14_4_PORT GPIO_PRT14 463 #define P14_4_PIN 4u 464 #define P14_4_NUM 4u 465 #define P14_4_AMUXSEGMENT AMUXBUS_MAIN 466 #define P14_5_PORT GPIO_PRT14 467 #define P14_5_PIN 5u 468 #define P14_5_NUM 5u 469 #define P14_5_AMUXSEGMENT AMUXBUS_MAIN 470 #define P14_6_PORT GPIO_PRT14 471 #define P14_6_PIN 6u 472 #define P14_6_NUM 6u 473 #define P14_6_AMUXSEGMENT AMUXBUS_MAIN 474 #define P14_7_PORT GPIO_PRT14 475 #define P14_7_PIN 7u 476 #define P14_7_NUM 7u 477 #define P14_7_AMUXSEGMENT AMUXBUS_MAIN 478 479 /* PORT 15 (GPIO) */ 480 #define P15_0_PORT GPIO_PRT15 481 #define P15_0_PIN 0u 482 #define P15_0_NUM 0u 483 #define P15_0_AMUXSEGMENT AMUXBUS_MAIN 484 #define P15_1_PORT GPIO_PRT15 485 #define P15_1_PIN 1u 486 #define P15_1_NUM 1u 487 #define P15_1_AMUXSEGMENT AMUXBUS_MAIN 488 #define P15_2_PORT GPIO_PRT15 489 #define P15_2_PIN 2u 490 #define P15_2_NUM 2u 491 #define P15_2_AMUXSEGMENT AMUXBUS_MAIN 492 #define P15_3_PORT GPIO_PRT15 493 #define P15_3_PIN 3u 494 #define P15_3_NUM 3u 495 #define P15_3_AMUXSEGMENT AMUXBUS_MAIN 496 497 /* PORT 16 (GPIO) */ 498 #define P16_0_PORT GPIO_PRT16 499 #define P16_0_PIN 0u 500 #define P16_0_NUM 0u 501 #define P16_0_AMUXSEGMENT AMUXBUS_MAIN 502 #define P16_1_PORT GPIO_PRT16 503 #define P16_1_PIN 1u 504 #define P16_1_NUM 1u 505 #define P16_1_AMUXSEGMENT AMUXBUS_MAIN 506 #define P16_2_PORT GPIO_PRT16 507 #define P16_2_PIN 2u 508 #define P16_2_NUM 2u 509 #define P16_2_AMUXSEGMENT AMUXBUS_MAIN 510 #define P16_3_PORT GPIO_PRT16 511 #define P16_3_PIN 3u 512 #define P16_3_NUM 3u 513 #define P16_3_AMUXSEGMENT AMUXBUS_MAIN 514 #define P16_4_PORT GPIO_PRT16 515 #define P16_4_PIN 4u 516 #define P16_4_NUM 4u 517 #define P16_4_AMUXSEGMENT AMUXBUS_MAIN 518 #define P16_5_PORT GPIO_PRT16 519 #define P16_5_PIN 5u 520 #define P16_5_NUM 5u 521 #define P16_5_AMUXSEGMENT AMUXBUS_MAIN 522 #define P16_6_PORT GPIO_PRT16 523 #define P16_6_PIN 6u 524 #define P16_6_NUM 6u 525 #define P16_6_AMUXSEGMENT AMUXBUS_MAIN 526 #define P16_7_PORT GPIO_PRT16 527 #define P16_7_PIN 7u 528 #define P16_7_NUM 7u 529 #define P16_7_AMUXSEGMENT AMUXBUS_MAIN 530 531 /* PORT 17 (GPIO) */ 532 #define P17_0_PORT GPIO_PRT17 533 #define P17_0_PIN 0u 534 #define P17_0_NUM 0u 535 #define P17_0_AMUXSEGMENT AMUXBUS_MAIN 536 #define P17_1_PORT GPIO_PRT17 537 #define P17_1_PIN 1u 538 #define P17_1_NUM 1u 539 #define P17_1_AMUXSEGMENT AMUXBUS_MAIN 540 #define P17_2_PORT GPIO_PRT17 541 #define P17_2_PIN 2u 542 #define P17_2_NUM 2u 543 #define P17_2_AMUXSEGMENT AMUXBUS_MAIN 544 #define P17_3_PORT GPIO_PRT17 545 #define P17_3_PIN 3u 546 #define P17_3_NUM 3u 547 #define P17_3_AMUXSEGMENT AMUXBUS_MAIN 548 #define P17_4_PORT GPIO_PRT17 549 #define P17_4_PIN 4u 550 #define P17_4_NUM 4u 551 #define P17_4_AMUXSEGMENT AMUXBUS_MAIN 552 #define P17_5_PORT GPIO_PRT17 553 #define P17_5_PIN 5u 554 #define P17_5_NUM 5u 555 #define P17_5_AMUXSEGMENT AMUXBUS_MAIN 556 #define P17_6_PORT GPIO_PRT17 557 #define P17_6_PIN 6u 558 #define P17_6_NUM 6u 559 #define P17_6_AMUXSEGMENT AMUXBUS_MAIN 560 #define P17_7_PORT GPIO_PRT17 561 #define P17_7_PIN 7u 562 #define P17_7_NUM 7u 563 #define P17_7_AMUXSEGMENT AMUXBUS_MAIN 564 565 /* PORT 18 (GPIO) */ 566 #define P18_0_PORT GPIO_PRT18 567 #define P18_0_PIN 0u 568 #define P18_0_NUM 0u 569 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 570 #define P18_1_PORT GPIO_PRT18 571 #define P18_1_PIN 1u 572 #define P18_1_NUM 1u 573 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 574 #define P18_2_PORT GPIO_PRT18 575 #define P18_2_PIN 2u 576 #define P18_2_NUM 2u 577 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 578 #define P18_3_PORT GPIO_PRT18 579 #define P18_3_PIN 3u 580 #define P18_3_NUM 3u 581 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 582 #define P18_4_PORT GPIO_PRT18 583 #define P18_4_PIN 4u 584 #define P18_4_NUM 4u 585 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 586 #define P18_5_PORT GPIO_PRT18 587 #define P18_5_PIN 5u 588 #define P18_5_NUM 5u 589 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 590 #define P18_6_PORT GPIO_PRT18 591 #define P18_6_PIN 6u 592 #define P18_6_NUM 6u 593 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 594 #define P18_7_PORT GPIO_PRT18 595 #define P18_7_PIN 7u 596 #define P18_7_NUM 7u 597 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 598 599 /* PORT 19 (GPIO) */ 600 #define P19_0_PORT GPIO_PRT19 601 #define P19_0_PIN 0u 602 #define P19_0_NUM 0u 603 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 604 #define P19_1_PORT GPIO_PRT19 605 #define P19_1_PIN 1u 606 #define P19_1_NUM 1u 607 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 608 #define P19_2_PORT GPIO_PRT19 609 #define P19_2_PIN 2u 610 #define P19_2_NUM 2u 611 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 612 #define P19_3_PORT GPIO_PRT19 613 #define P19_3_PIN 3u 614 #define P19_3_NUM 3u 615 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 616 #define P19_4_PORT GPIO_PRT19 617 #define P19_4_PIN 4u 618 #define P19_4_NUM 4u 619 #define P19_4_AMUXSEGMENT AMUXBUS_MAIN 620 621 /* PORT 20 (GPIO) */ 622 #define P20_0_PORT GPIO_PRT20 623 #define P20_0_PIN 0u 624 #define P20_0_NUM 0u 625 #define P20_0_AMUXSEGMENT AMUXBUS_MAIN 626 #define P20_1_PORT GPIO_PRT20 627 #define P20_1_PIN 1u 628 #define P20_1_NUM 1u 629 #define P20_1_AMUXSEGMENT AMUXBUS_MAIN 630 #define P20_2_PORT GPIO_PRT20 631 #define P20_2_PIN 2u 632 #define P20_2_NUM 2u 633 #define P20_2_AMUXSEGMENT AMUXBUS_MAIN 634 #define P20_3_PORT GPIO_PRT20 635 #define P20_3_PIN 3u 636 #define P20_3_NUM 3u 637 #define P20_3_AMUXSEGMENT AMUXBUS_MAIN 638 #define P20_4_PORT GPIO_PRT20 639 #define P20_4_PIN 4u 640 #define P20_4_NUM 4u 641 #define P20_4_AMUXSEGMENT AMUXBUS_MAIN 642 #define P20_5_PORT GPIO_PRT20 643 #define P20_5_PIN 5u 644 #define P20_5_NUM 5u 645 #define P20_5_AMUXSEGMENT AMUXBUS_MAIN 646 #define P20_6_PORT GPIO_PRT20 647 #define P20_6_PIN 6u 648 #define P20_6_NUM 6u 649 #define P20_6_AMUXSEGMENT AMUXBUS_MAIN 650 #define P20_7_PORT GPIO_PRT20 651 #define P20_7_PIN 7u 652 #define P20_7_NUM 7u 653 #define P20_7_AMUXSEGMENT AMUXBUS_MAIN 654 655 /* PORT 21 (GPIO) */ 656 #define P21_0_PORT GPIO_PRT21 657 #define P21_0_PIN 0u 658 #define P21_0_NUM 0u 659 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 660 #define P21_1_PORT GPIO_PRT21 661 #define P21_1_PIN 1u 662 #define P21_1_NUM 1u 663 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 664 #define P21_2_PORT GPIO_PRT21 665 #define P21_2_PIN 2u 666 #define P21_2_NUM 2u 667 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 668 #define P21_3_PORT GPIO_PRT21 669 #define P21_3_PIN 3u 670 #define P21_3_NUM 3u 671 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 672 #define P21_4_PORT GPIO_PRT21 673 #define P21_4_PIN 4u 674 #define P21_4_NUM 4u 675 #define P21_4_AMUXSEGMENT AMUXBUS_MAIN 676 #define P21_5_PORT GPIO_PRT21 677 #define P21_5_PIN 5u 678 #define P21_5_NUM 5u 679 #define P21_5_AMUXSEGMENT AMUXBUS_MAIN 680 #define P21_6_PORT GPIO_PRT21 681 #define P21_6_PIN 6u 682 #define P21_6_NUM 6u 683 #define P21_6_AMUXSEGMENT AMUXBUS_MAIN 684 #define P21_7_PORT GPIO_PRT21 685 #define P21_7_PIN 7u 686 #define P21_7_NUM 7u 687 #define P21_7_AMUXSEGMENT AMUXBUS_MAIN 688 689 /* PORT 22 (GPIO) */ 690 #define P22_1_PORT GPIO_PRT22 691 #define P22_1_PIN 1u 692 #define P22_1_NUM 1u 693 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 694 #define P22_2_PORT GPIO_PRT22 695 #define P22_2_PIN 2u 696 #define P22_2_NUM 2u 697 #define P22_2_AMUXSEGMENT AMUXBUS_MAIN 698 #define P22_3_PORT GPIO_PRT22 699 #define P22_3_PIN 3u 700 #define P22_3_NUM 3u 701 #define P22_3_AMUXSEGMENT AMUXBUS_MAIN 702 #define P22_4_PORT GPIO_PRT22 703 #define P22_4_PIN 4u 704 #define P22_4_NUM 4u 705 #define P22_4_AMUXSEGMENT AMUXBUS_MAIN 706 #define P22_5_PORT GPIO_PRT22 707 #define P22_5_PIN 5u 708 #define P22_5_NUM 5u 709 #define P22_5_AMUXSEGMENT AMUXBUS_MAIN 710 #define P22_6_PORT GPIO_PRT22 711 #define P22_6_PIN 6u 712 #define P22_6_NUM 6u 713 #define P22_6_AMUXSEGMENT AMUXBUS_MAIN 714 #define P22_7_PORT GPIO_PRT22 715 #define P22_7_PIN 7u 716 #define P22_7_NUM 7u 717 #define P22_7_AMUXSEGMENT AMUXBUS_MAIN 718 719 /* PORT 23 (GPIO) */ 720 #define P23_0_PORT GPIO_PRT23 721 #define P23_0_PIN 0u 722 #define P23_0_NUM 0u 723 #define P23_0_AMUXSEGMENT AMUXBUS_MAIN 724 #define P23_1_PORT GPIO_PRT23 725 #define P23_1_PIN 1u 726 #define P23_1_NUM 1u 727 #define P23_1_AMUXSEGMENT AMUXBUS_MAIN 728 #define P23_2_PORT GPIO_PRT23 729 #define P23_2_PIN 2u 730 #define P23_2_NUM 2u 731 #define P23_2_AMUXSEGMENT AMUXBUS_MAIN 732 #define P23_3_PORT GPIO_PRT23 733 #define P23_3_PIN 3u 734 #define P23_3_NUM 3u 735 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 736 #define P23_4_PORT GPIO_PRT23 737 #define P23_4_PIN 4u 738 #define P23_4_NUM 4u 739 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 740 #define P23_5_PORT GPIO_PRT23 741 #define P23_5_PIN 5u 742 #define P23_5_NUM 5u 743 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 744 #define P23_6_PORT GPIO_PRT23 745 #define P23_6_PIN 6u 746 #define P23_6_NUM 6u 747 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 748 #define P23_7_PORT GPIO_PRT23 749 #define P23_7_PIN 7u 750 #define P23_7_NUM 7u 751 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 752 753 /* PORT 24 (GPIO) */ 754 #define P24_0_PORT GPIO_PRT24 755 #define P24_0_PIN 0u 756 #define P24_0_NUM 0u 757 #define P24_0_AMUXSEGMENT AMUXBUS_MAIN 758 #define P24_1_PORT GPIO_PRT24 759 #define P24_1_PIN 1u 760 #define P24_1_NUM 1u 761 #define P24_1_AMUXSEGMENT AMUXBUS_MAIN 762 #define P24_2_PORT GPIO_PRT24 763 #define P24_2_PIN 2u 764 #define P24_2_NUM 2u 765 #define P24_2_AMUXSEGMENT AMUXBUS_MAIN 766 #define P24_3_PORT GPIO_PRT24 767 #define P24_3_PIN 3u 768 #define P24_3_NUM 3u 769 #define P24_3_AMUXSEGMENT AMUXBUS_MAIN 770 #define P24_4_PORT GPIO_PRT24 771 #define P24_4_PIN 4u 772 #define P24_4_NUM 4u 773 #define P24_4_AMUXSEGMENT AMUXBUS_MAIN 774 775 /* PORT 25 (GPIO) */ 776 #define P25_0_PORT GPIO_PRT25 777 #define P25_0_PIN 0u 778 #define P25_0_NUM 0u 779 #define P25_0_AMUXSEGMENT AMUXBUS_MAIN 780 #define P25_1_PORT GPIO_PRT25 781 #define P25_1_PIN 1u 782 #define P25_1_NUM 1u 783 #define P25_1_AMUXSEGMENT AMUXBUS_MAIN 784 #define P25_2_PORT GPIO_PRT25 785 #define P25_2_PIN 2u 786 #define P25_2_NUM 2u 787 #define P25_2_AMUXSEGMENT AMUXBUS_MAIN 788 #define P25_3_PORT GPIO_PRT25 789 #define P25_3_PIN 3u 790 #define P25_3_NUM 3u 791 #define P25_3_AMUXSEGMENT AMUXBUS_MAIN 792 #define P25_4_PORT GPIO_PRT25 793 #define P25_4_PIN 4u 794 #define P25_4_NUM 4u 795 #define P25_4_AMUXSEGMENT AMUXBUS_MAIN 796 #define P25_5_PORT GPIO_PRT25 797 #define P25_5_PIN 5u 798 #define P25_5_NUM 5u 799 #define P25_5_AMUXSEGMENT AMUXBUS_MAIN 800 #define P25_6_PORT GPIO_PRT25 801 #define P25_6_PIN 6u 802 #define P25_6_NUM 6u 803 #define P25_6_AMUXSEGMENT AMUXBUS_MAIN 804 #define P25_7_PORT GPIO_PRT25 805 #define P25_7_PIN 7u 806 #define P25_7_NUM 7u 807 #define P25_7_AMUXSEGMENT AMUXBUS_MAIN 808 809 /* PORT 26 (GPIO) */ 810 #define P26_0_PORT GPIO_PRT26 811 #define P26_0_PIN 0u 812 #define P26_0_NUM 0u 813 #define P26_0_AMUXSEGMENT AMUXBUS_MAIN 814 #define P26_1_PORT GPIO_PRT26 815 #define P26_1_PIN 1u 816 #define P26_1_NUM 1u 817 #define P26_1_AMUXSEGMENT AMUXBUS_MAIN 818 #define P26_2_PORT GPIO_PRT26 819 #define P26_2_PIN 2u 820 #define P26_2_NUM 2u 821 #define P26_2_AMUXSEGMENT AMUXBUS_MAIN 822 #define P26_3_PORT GPIO_PRT26 823 #define P26_3_PIN 3u 824 #define P26_3_NUM 3u 825 #define P26_3_AMUXSEGMENT AMUXBUS_MAIN 826 #define P26_4_PORT GPIO_PRT26 827 #define P26_4_PIN 4u 828 #define P26_4_NUM 4u 829 #define P26_4_AMUXSEGMENT AMUXBUS_MAIN 830 #define P26_5_PORT GPIO_PRT26 831 #define P26_5_PIN 5u 832 #define P26_5_NUM 5u 833 #define P26_5_AMUXSEGMENT AMUXBUS_MAIN 834 #define P26_6_PORT GPIO_PRT26 835 #define P26_6_PIN 6u 836 #define P26_6_NUM 6u 837 #define P26_6_AMUXSEGMENT AMUXBUS_MAIN 838 #define P26_7_PORT GPIO_PRT26 839 #define P26_7_PIN 7u 840 #define P26_7_NUM 7u 841 #define P26_7_AMUXSEGMENT AMUXBUS_MAIN 842 843 /* PORT 27 (GPIO) */ 844 #define P27_0_PORT GPIO_PRT27 845 #define P27_0_PIN 0u 846 #define P27_0_NUM 0u 847 #define P27_0_AMUXSEGMENT AMUXBUS_MAIN 848 #define P27_1_PORT GPIO_PRT27 849 #define P27_1_PIN 1u 850 #define P27_1_NUM 1u 851 #define P27_1_AMUXSEGMENT AMUXBUS_MAIN 852 #define P27_2_PORT GPIO_PRT27 853 #define P27_2_PIN 2u 854 #define P27_2_NUM 2u 855 #define P27_2_AMUXSEGMENT AMUXBUS_MAIN 856 #define P27_3_PORT GPIO_PRT27 857 #define P27_3_PIN 3u 858 #define P27_3_NUM 3u 859 #define P27_3_AMUXSEGMENT AMUXBUS_MAIN 860 #define P27_4_PORT GPIO_PRT27 861 #define P27_4_PIN 4u 862 #define P27_4_NUM 4u 863 #define P27_4_AMUXSEGMENT AMUXBUS_MAIN 864 #define P27_5_PORT GPIO_PRT27 865 #define P27_5_PIN 5u 866 #define P27_5_NUM 5u 867 #define P27_5_AMUXSEGMENT AMUXBUS_MAIN 868 #define P27_6_PORT GPIO_PRT27 869 #define P27_6_PIN 6u 870 #define P27_6_NUM 6u 871 #define P27_6_AMUXSEGMENT AMUXBUS_MAIN 872 #define P27_7_PORT GPIO_PRT27 873 #define P27_7_PIN 7u 874 #define P27_7_NUM 7u 875 #define P27_7_AMUXSEGMENT AMUXBUS_MAIN 876 877 /* PORT 28 (GPIO) */ 878 #define P28_0_PORT GPIO_PRT28 879 #define P28_0_PIN 0u 880 #define P28_0_NUM 0u 881 #define P28_0_AMUXSEGMENT AMUXBUS_MAIN 882 #define P28_1_PORT GPIO_PRT28 883 #define P28_1_PIN 1u 884 #define P28_1_NUM 1u 885 #define P28_1_AMUXSEGMENT AMUXBUS_MAIN 886 #define P28_2_PORT GPIO_PRT28 887 #define P28_2_PIN 2u 888 #define P28_2_NUM 2u 889 #define P28_2_AMUXSEGMENT AMUXBUS_MAIN 890 #define P28_3_PORT GPIO_PRT28 891 #define P28_3_PIN 3u 892 #define P28_3_NUM 3u 893 #define P28_3_AMUXSEGMENT AMUXBUS_MAIN 894 #define P28_4_PORT GPIO_PRT28 895 #define P28_4_PIN 4u 896 #define P28_4_NUM 4u 897 #define P28_4_AMUXSEGMENT AMUXBUS_MAIN 898 #define P28_5_PORT GPIO_PRT28 899 #define P28_5_PIN 5u 900 #define P28_5_NUM 5u 901 #define P28_5_AMUXSEGMENT AMUXBUS_MAIN 902 #define P28_6_PORT GPIO_PRT28 903 #define P28_6_PIN 6u 904 #define P28_6_NUM 6u 905 #define P28_6_AMUXSEGMENT AMUXBUS_MAIN 906 #define P28_7_PORT GPIO_PRT28 907 #define P28_7_PIN 7u 908 #define P28_7_NUM 7u 909 #define P28_7_AMUXSEGMENT AMUXBUS_MAIN 910 911 /* PORT 29 (GPIO) */ 912 #define P29_0_PORT GPIO_PRT29 913 #define P29_0_PIN 0u 914 #define P29_0_NUM 0u 915 #define P29_0_AMUXSEGMENT AMUXBUS_MAIN 916 #define P29_1_PORT GPIO_PRT29 917 #define P29_1_PIN 1u 918 #define P29_1_NUM 1u 919 #define P29_1_AMUXSEGMENT AMUXBUS_MAIN 920 #define P29_2_PORT GPIO_PRT29 921 #define P29_2_PIN 2u 922 #define P29_2_NUM 2u 923 #define P29_2_AMUXSEGMENT AMUXBUS_MAIN 924 #define P29_3_PORT GPIO_PRT29 925 #define P29_3_PIN 3u 926 #define P29_3_NUM 3u 927 #define P29_3_AMUXSEGMENT AMUXBUS_MAIN 928 #define P29_4_PORT GPIO_PRT29 929 #define P29_4_PIN 4u 930 #define P29_4_NUM 4u 931 #define P29_4_AMUXSEGMENT AMUXBUS_MAIN 932 #define P29_5_PORT GPIO_PRT29 933 #define P29_5_PIN 5u 934 #define P29_5_NUM 5u 935 #define P29_5_AMUXSEGMENT AMUXBUS_MAIN 936 #define P29_6_PORT GPIO_PRT29 937 #define P29_6_PIN 6u 938 #define P29_6_NUM 6u 939 #define P29_6_AMUXSEGMENT AMUXBUS_MAIN 940 #define P29_7_PORT GPIO_PRT29 941 #define P29_7_PIN 7u 942 #define P29_7_NUM 7u 943 #define P29_7_AMUXSEGMENT AMUXBUS_MAIN 944 945 /* PORT 30 (GPIO) */ 946 #define P30_0_PORT GPIO_PRT30 947 #define P30_0_PIN 0u 948 #define P30_0_NUM 0u 949 #define P30_0_AMUXSEGMENT AMUXBUS_MAIN 950 #define P30_1_PORT GPIO_PRT30 951 #define P30_1_PIN 1u 952 #define P30_1_NUM 1u 953 #define P30_1_AMUXSEGMENT AMUXBUS_MAIN 954 #define P30_2_PORT GPIO_PRT30 955 #define P30_2_PIN 2u 956 #define P30_2_NUM 2u 957 #define P30_2_AMUXSEGMENT AMUXBUS_MAIN 958 #define P30_3_PORT GPIO_PRT30 959 #define P30_3_PIN 3u 960 #define P30_3_NUM 3u 961 #define P30_3_AMUXSEGMENT AMUXBUS_MAIN 962 963 /* PORT 31 (GPIO) */ 964 #define P31_0_PORT GPIO_PRT31 965 #define P31_0_PIN 0u 966 #define P31_0_NUM 0u 967 #define P31_0_AMUXSEGMENT AMUXBUS_MAIN 968 #define P31_1_PORT GPIO_PRT31 969 #define P31_1_PIN 1u 970 #define P31_1_NUM 1u 971 #define P31_1_AMUXSEGMENT AMUXBUS_MAIN 972 #define P31_2_PORT GPIO_PRT31 973 #define P31_2_PIN 2u 974 #define P31_2_NUM 2u 975 #define P31_2_AMUXSEGMENT AMUXBUS_MAIN 976 977 /* PORT 32 (GPIO) */ 978 #define P32_0_PORT GPIO_PRT32 979 #define P32_0_PIN 0u 980 #define P32_0_NUM 0u 981 #define P32_0_AMUXSEGMENT AMUXBUS_MAIN 982 #define P32_1_PORT GPIO_PRT32 983 #define P32_1_PIN 1u 984 #define P32_1_NUM 1u 985 #define P32_1_AMUXSEGMENT AMUXBUS_MAIN 986 #define P32_2_PORT GPIO_PRT32 987 #define P32_2_PIN 2u 988 #define P32_2_NUM 2u 989 #define P32_2_AMUXSEGMENT AMUXBUS_MAIN 990 #define P32_3_PORT GPIO_PRT32 991 #define P32_3_PIN 3u 992 #define P32_3_NUM 3u 993 #define P32_3_AMUXSEGMENT AMUXBUS_MAIN 994 #define P32_4_PORT GPIO_PRT32 995 #define P32_4_PIN 4u 996 #define P32_4_NUM 4u 997 #define P32_4_AMUXSEGMENT AMUXBUS_MAIN 998 #define P32_5_PORT GPIO_PRT32 999 #define P32_5_PIN 5u 1000 #define P32_5_NUM 5u 1001 #define P32_5_AMUXSEGMENT AMUXBUS_MAIN 1002 #define P32_6_PORT GPIO_PRT32 1003 #define P32_6_PIN 6u 1004 #define P32_6_NUM 6u 1005 #define P32_6_AMUXSEGMENT AMUXBUS_MAIN 1006 #define P32_7_PORT GPIO_PRT32 1007 #define P32_7_PIN 7u 1008 #define P32_7_NUM 7u 1009 #define P32_7_AMUXSEGMENT AMUXBUS_MAIN 1010 1011 /* Analog Connections */ 1012 #define PASS0_I_TEMP_KELVIN_PORT 21u 1013 #define PASS0_I_TEMP_KELVIN_PIN 2u 1014 #define PASS0_SARMUX_MOTOR0_PORT 11u 1015 #define PASS0_SARMUX_MOTOR0_PIN 0u 1016 #define PASS0_SARMUX_MOTOR1_PORT 11u 1017 #define PASS0_SARMUX_MOTOR1_PIN 1u 1018 #define PASS0_SARMUX_MOTOR2_PORT 11u 1019 #define PASS0_SARMUX_MOTOR2_PIN 2u 1020 #define PASS0_SARMUX_PADS0_PORT 6u 1021 #define PASS0_SARMUX_PADS0_PIN 0u 1022 #define PASS0_SARMUX_PADS1_PORT 6u 1023 #define PASS0_SARMUX_PADS1_PIN 1u 1024 #define PASS0_SARMUX_PADS10_PORT 32u 1025 #define PASS0_SARMUX_PADS10_PIN 2u 1026 #define PASS0_SARMUX_PADS11_PORT 32u 1027 #define PASS0_SARMUX_PADS11_PIN 3u 1028 #define PASS0_SARMUX_PADS12_PORT 32u 1029 #define PASS0_SARMUX_PADS12_PIN 4u 1030 #define PASS0_SARMUX_PADS13_PORT 32u 1031 #define PASS0_SARMUX_PADS13_PIN 5u 1032 #define PASS0_SARMUX_PADS14_PORT 32u 1033 #define PASS0_SARMUX_PADS14_PIN 6u 1034 #define PASS0_SARMUX_PADS15_PORT 32u 1035 #define PASS0_SARMUX_PADS15_PIN 7u 1036 #define PASS0_SARMUX_PADS16_PORT 7u 1037 #define PASS0_SARMUX_PADS16_PIN 0u 1038 #define PASS0_SARMUX_PADS17_PORT 7u 1039 #define PASS0_SARMUX_PADS17_PIN 1u 1040 #define PASS0_SARMUX_PADS18_PORT 7u 1041 #define PASS0_SARMUX_PADS18_PIN 2u 1042 #define PASS0_SARMUX_PADS19_PORT 7u 1043 #define PASS0_SARMUX_PADS19_PIN 3u 1044 #define PASS0_SARMUX_PADS2_PORT 6u 1045 #define PASS0_SARMUX_PADS2_PIN 2u 1046 #define PASS0_SARMUX_PADS20_PORT 7u 1047 #define PASS0_SARMUX_PADS20_PIN 4u 1048 #define PASS0_SARMUX_PADS21_PORT 7u 1049 #define PASS0_SARMUX_PADS21_PIN 5u 1050 #define PASS0_SARMUX_PADS22_PORT 7u 1051 #define PASS0_SARMUX_PADS22_PIN 6u 1052 #define PASS0_SARMUX_PADS23_PORT 7u 1053 #define PASS0_SARMUX_PADS23_PIN 7u 1054 #define PASS0_SARMUX_PADS24_PORT 8u 1055 #define PASS0_SARMUX_PADS24_PIN 1u 1056 #define PASS0_SARMUX_PADS25_PORT 8u 1057 #define PASS0_SARMUX_PADS25_PIN 2u 1058 #define PASS0_SARMUX_PADS26_PORT 8u 1059 #define PASS0_SARMUX_PADS26_PIN 3u 1060 #define PASS0_SARMUX_PADS27_PORT 8u 1061 #define PASS0_SARMUX_PADS27_PIN 4u 1062 #define PASS0_SARMUX_PADS28_PORT 9u 1063 #define PASS0_SARMUX_PADS28_PIN 0u 1064 #define PASS0_SARMUX_PADS29_PORT 9u 1065 #define PASS0_SARMUX_PADS29_PIN 1u 1066 #define PASS0_SARMUX_PADS3_PORT 6u 1067 #define PASS0_SARMUX_PADS3_PIN 3u 1068 #define PASS0_SARMUX_PADS30_PORT 9u 1069 #define PASS0_SARMUX_PADS30_PIN 2u 1070 #define PASS0_SARMUX_PADS31_PORT 9u 1071 #define PASS0_SARMUX_PADS31_PIN 3u 1072 #define PASS0_SARMUX_PADS32_PORT 10u 1073 #define PASS0_SARMUX_PADS32_PIN 4u 1074 #define PASS0_SARMUX_PADS33_PORT 10u 1075 #define PASS0_SARMUX_PADS33_PIN 5u 1076 #define PASS0_SARMUX_PADS34_PORT 10u 1077 #define PASS0_SARMUX_PADS34_PIN 6u 1078 #define PASS0_SARMUX_PADS35_PORT 10u 1079 #define PASS0_SARMUX_PADS35_PIN 7u 1080 #define PASS0_SARMUX_PADS36_PORT 12u 1081 #define PASS0_SARMUX_PADS36_PIN 0u 1082 #define PASS0_SARMUX_PADS37_PORT 12u 1083 #define PASS0_SARMUX_PADS37_PIN 1u 1084 #define PASS0_SARMUX_PADS38_PORT 12u 1085 #define PASS0_SARMUX_PADS38_PIN 2u 1086 #define PASS0_SARMUX_PADS39_PORT 12u 1087 #define PASS0_SARMUX_PADS39_PIN 3u 1088 #define PASS0_SARMUX_PADS4_PORT 6u 1089 #define PASS0_SARMUX_PADS4_PIN 4u 1090 #define PASS0_SARMUX_PADS40_PORT 12u 1091 #define PASS0_SARMUX_PADS40_PIN 4u 1092 #define PASS0_SARMUX_PADS41_PORT 12u 1093 #define PASS0_SARMUX_PADS41_PIN 5u 1094 #define PASS0_SARMUX_PADS42_PORT 12u 1095 #define PASS0_SARMUX_PADS42_PIN 6u 1096 #define PASS0_SARMUX_PADS43_PORT 12u 1097 #define PASS0_SARMUX_PADS43_PIN 7u 1098 #define PASS0_SARMUX_PADS44_PORT 13u 1099 #define PASS0_SARMUX_PADS44_PIN 0u 1100 #define PASS0_SARMUX_PADS45_PORT 13u 1101 #define PASS0_SARMUX_PADS45_PIN 1u 1102 #define PASS0_SARMUX_PADS46_PORT 13u 1103 #define PASS0_SARMUX_PADS46_PIN 2u 1104 #define PASS0_SARMUX_PADS47_PORT 13u 1105 #define PASS0_SARMUX_PADS47_PIN 3u 1106 #define PASS0_SARMUX_PADS48_PORT 13u 1107 #define PASS0_SARMUX_PADS48_PIN 4u 1108 #define PASS0_SARMUX_PADS49_PORT 13u 1109 #define PASS0_SARMUX_PADS49_PIN 5u 1110 #define PASS0_SARMUX_PADS5_PORT 6u 1111 #define PASS0_SARMUX_PADS5_PIN 5u 1112 #define PASS0_SARMUX_PADS50_PORT 13u 1113 #define PASS0_SARMUX_PADS50_PIN 6u 1114 #define PASS0_SARMUX_PADS51_PORT 13u 1115 #define PASS0_SARMUX_PADS51_PIN 7u 1116 #define PASS0_SARMUX_PADS52_PORT 14u 1117 #define PASS0_SARMUX_PADS52_PIN 0u 1118 #define PASS0_SARMUX_PADS53_PORT 14u 1119 #define PASS0_SARMUX_PADS53_PIN 1u 1120 #define PASS0_SARMUX_PADS54_PORT 14u 1121 #define PASS0_SARMUX_PADS54_PIN 2u 1122 #define PASS0_SARMUX_PADS55_PORT 14u 1123 #define PASS0_SARMUX_PADS55_PIN 3u 1124 #define PASS0_SARMUX_PADS56_PORT 14u 1125 #define PASS0_SARMUX_PADS56_PIN 4u 1126 #define PASS0_SARMUX_PADS57_PORT 14u 1127 #define PASS0_SARMUX_PADS57_PIN 5u 1128 #define PASS0_SARMUX_PADS58_PORT 14u 1129 #define PASS0_SARMUX_PADS58_PIN 6u 1130 #define PASS0_SARMUX_PADS59_PORT 14u 1131 #define PASS0_SARMUX_PADS59_PIN 7u 1132 #define PASS0_SARMUX_PADS6_PORT 6u 1133 #define PASS0_SARMUX_PADS6_PIN 6u 1134 #define PASS0_SARMUX_PADS60_PORT 15u 1135 #define PASS0_SARMUX_PADS60_PIN 0u 1136 #define PASS0_SARMUX_PADS61_PORT 15u 1137 #define PASS0_SARMUX_PADS61_PIN 1u 1138 #define PASS0_SARMUX_PADS62_PORT 15u 1139 #define PASS0_SARMUX_PADS62_PIN 2u 1140 #define PASS0_SARMUX_PADS63_PORT 15u 1141 #define PASS0_SARMUX_PADS63_PIN 3u 1142 #define PASS0_SARMUX_PADS64_PORT 18u 1143 #define PASS0_SARMUX_PADS64_PIN 0u 1144 #define PASS0_SARMUX_PADS65_PORT 18u 1145 #define PASS0_SARMUX_PADS65_PIN 1u 1146 #define PASS0_SARMUX_PADS66_PORT 18u 1147 #define PASS0_SARMUX_PADS66_PIN 2u 1148 #define PASS0_SARMUX_PADS67_PORT 18u 1149 #define PASS0_SARMUX_PADS67_PIN 3u 1150 #define PASS0_SARMUX_PADS68_PORT 18u 1151 #define PASS0_SARMUX_PADS68_PIN 4u 1152 #define PASS0_SARMUX_PADS69_PORT 18u 1153 #define PASS0_SARMUX_PADS69_PIN 5u 1154 #define PASS0_SARMUX_PADS7_PORT 6u 1155 #define PASS0_SARMUX_PADS7_PIN 7u 1156 #define PASS0_SARMUX_PADS70_PORT 18u 1157 #define PASS0_SARMUX_PADS70_PIN 6u 1158 #define PASS0_SARMUX_PADS71_PORT 18u 1159 #define PASS0_SARMUX_PADS71_PIN 7u 1160 #define PASS0_SARMUX_PADS8_PORT 32u 1161 #define PASS0_SARMUX_PADS8_PIN 0u 1162 #define PASS0_SARMUX_PADS9_PORT 32u 1163 #define PASS0_SARMUX_PADS9_PIN 1u 1164 #define PASS0_VB_TEMP_KELVIN_PORT 10u 1165 #define PASS0_VB_TEMP_KELVIN_PIN 4u 1166 #define PASS0_VE_TEMP_KELVIN_PORT 23u 1167 #define PASS0_VE_TEMP_KELVIN_PIN 4u 1168 #define SRSS_ADFT_PIN0_PORT 23u 1169 #define SRSS_ADFT_PIN0_PIN 4u 1170 #define SRSS_ADFT_PIN1_PORT 23u 1171 #define SRSS_ADFT_PIN1_PIN 3u 1172 #define SRSS_ADFT_POR_PAD_HV_PORT 21u 1173 #define SRSS_ADFT_POR_PAD_HV_PIN 4u 1174 #define SRSS_ECO_IN_PORT 21u 1175 #define SRSS_ECO_IN_PIN 2u 1176 #define SRSS_ECO_OUT_PORT 21u 1177 #define SRSS_ECO_OUT_PIN 3u 1178 #define SRSS_REGHC_ISENSE_INM_PORT 22u 1179 #define SRSS_REGHC_ISENSE_INM_PIN 2u 1180 #define SRSS_REGHC_ISENSE_INP_PORT 22u 1181 #define SRSS_REGHC_ISENSE_INP_PIN 1u 1182 #define SRSS_REGHC_RST_VOUT_PORT 22u 1183 #define SRSS_REGHC_RST_VOUT_PIN 3u 1184 #define SRSS_VEXT_REF_REG_PORT 21u 1185 #define SRSS_VEXT_REF_REG_PIN 3u 1186 #define SRSS_WCO_IN_PORT 21u 1187 #define SRSS_WCO_IN_PIN 0u 1188 #define SRSS_WCO_OUT_PORT 21u 1189 #define SRSS_WCO_OUT_PIN 1u 1190 1191 /* HSIOM Connections */ 1192 typedef enum 1193 { 1194 /* Generic HSIOM connections */ 1195 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 1196 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1197 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1198 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1199 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 1200 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 1201 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1202 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1203 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 1204 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 1205 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 1206 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 1207 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 1208 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 1209 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 1210 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 1211 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 1212 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 1213 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 1214 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 1215 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 1216 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 1217 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 1218 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 1219 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 1220 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 1221 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 1222 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 1223 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 1224 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 1225 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 1226 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 1227 1228 /* P0.0 */ 1229 P0_0_GPIO = 0, /* GPIO controls 'out' */ 1230 P0_0_AMUXA = 4, /* Analog mux bus A */ 1231 P0_0_AMUXB = 5, /* Analog mux bus B */ 1232 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1233 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1234 P0_0_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:1 */ 1235 P0_0_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ 1236 P0_0_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:1 */ 1237 P0_0_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:1 */ 1238 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 1239 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 1240 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 1241 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 1242 1243 /* P0.1 */ 1244 P0_1_GPIO = 0, /* GPIO controls 'out' */ 1245 P0_1_AMUXA = 4, /* Analog mux bus A */ 1246 P0_1_AMUXB = 5, /* Analog mux bus B */ 1247 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1248 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1249 P0_1_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:1 */ 1250 P0_1_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:1 */ 1251 P0_1_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:1 */ 1252 P0_1_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:1 */ 1253 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 1254 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 1255 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 1256 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 1257 1258 /* P0.2 */ 1259 P0_2_GPIO = 0, /* GPIO controls 'out' */ 1260 P0_2_AMUXA = 4, /* Analog mux bus A */ 1261 P0_2_AMUXB = 5, /* Analog mux bus B */ 1262 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1263 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1264 P0_2_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:1 */ 1265 P0_2_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:1 */ 1266 P0_2_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:1 */ 1267 P0_2_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:1 */ 1268 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 1269 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 1270 P0_2_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:2 */ 1271 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 1272 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 1273 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 1274 1275 /* P0.3 */ 1276 P0_3_GPIO = 0, /* GPIO controls 'out' */ 1277 P0_3_AMUXA = 4, /* Analog mux bus A */ 1278 P0_3_AMUXB = 5, /* Analog mux bus B */ 1279 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1280 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1281 P0_3_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:1 */ 1282 P0_3_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:1 */ 1283 P0_3_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:1 */ 1284 P0_3_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:1 */ 1285 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 1286 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 1287 P0_3_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:2 */ 1288 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 1289 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 1290 1291 /* P1.0 */ 1292 P1_0_GPIO = 0, /* GPIO controls 'out' */ 1293 P1_0_AMUXA = 4, /* Analog mux bus A */ 1294 P1_0_AMUXB = 5, /* Analog mux bus B */ 1295 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1296 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1297 P1_0_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:1 */ 1298 P1_0_TCPWM0_LINE_COMPL13 = 9, /* Digital Active - tcpwm[0].line_compl[13]:1 */ 1299 P1_0_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:1 */ 1300 P1_0_TCPWM0_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[40]:1 */ 1301 P1_0_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 1302 P1_0_TCPWM0_LINE516 = 16, /* Digital Active - tcpwm[0].line[516]:0 */ 1303 P1_0_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:2 */ 1304 P1_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 1305 1306 /* P1.1 */ 1307 P1_1_GPIO = 0, /* GPIO controls 'out' */ 1308 P1_1_AMUXA = 4, /* Analog mux bus A */ 1309 P1_1_AMUXB = 5, /* Analog mux bus B */ 1310 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1311 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1312 P1_1_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:1 */ 1313 P1_1_TCPWM0_LINE_COMPL12 = 9, /* Digital Active - tcpwm[0].line_compl[12]:1 */ 1314 P1_1_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:1 */ 1315 P1_1_TCPWM0_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:1 */ 1316 P1_1_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 1317 P1_1_TCPWM0_LINE517 = 16, /* Digital Active - tcpwm[0].line[517]:0 */ 1318 P1_1_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:2 */ 1319 P1_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 1320 1321 /* P1.2 */ 1322 P1_2_GPIO = 0, /* GPIO controls 'out' */ 1323 P1_2_AMUXA = 4, /* Analog mux bus A */ 1324 P1_2_AMUXB = 5, /* Analog mux bus B */ 1325 P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1326 P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1327 P1_2_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:1 */ 1328 P1_2_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:1 */ 1329 P1_2_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:1 */ 1330 P1_2_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:1 */ 1331 P1_2_TCPWM0_LINE518 = 16, /* Digital Active - tcpwm[0].line[518]:0 */ 1332 P1_2_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:2 */ 1333 P1_2_PERI_TR_IO_INPUT0 = 26, /* Digital Active - peri.tr_io_input[0]:0 */ 1334 P1_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:1 */ 1335 1336 /* P1.3 */ 1337 P1_3_GPIO = 0, /* GPIO controls 'out' */ 1338 P1_3_AMUXA = 4, /* Analog mux bus A */ 1339 P1_3_AMUXB = 5, /* Analog mux bus B */ 1340 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1341 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1342 P1_3_TCPWM0_LINE8 = 8, /* Digital Active - tcpwm[0].line[8]:1 */ 1343 P1_3_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:1 */ 1344 P1_3_TCPWM0_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[24]:1 */ 1345 P1_3_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:1 */ 1346 P1_3_TCPWM0_LINE519 = 16, /* Digital Active - tcpwm[0].line[519]:0 */ 1347 P1_3_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:2 */ 1348 P1_3_PERI_TR_IO_INPUT1 = 26, /* Digital Active - peri.tr_io_input[1]:0 */ 1349 P1_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:1 */ 1350 1351 /* P1.4 */ 1352 P1_4_GPIO = 0, /* GPIO controls 'out' */ 1353 P1_4_AMUXA = 4, /* Analog mux bus A */ 1354 P1_4_AMUXB = 5, /* Analog mux bus B */ 1355 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1356 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1357 P1_4_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:1 */ 1358 P1_4_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:1 */ 1359 P1_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:2 */ 1360 1361 /* P2.0 */ 1362 P2_0_GPIO = 0, /* GPIO controls 'out' */ 1363 P2_0_AMUXA = 4, /* Analog mux bus A */ 1364 P2_0_AMUXB = 5, /* Analog mux bus B */ 1365 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1366 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1367 P2_0_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 1368 P2_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:1 */ 1369 P2_0_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ 1370 P2_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ 1371 P2_0_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:0 */ 1372 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 1373 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 1374 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 1375 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 1376 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 1377 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 1378 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 1379 1380 /* P2.1 */ 1381 P2_1_GPIO = 0, /* GPIO controls 'out' */ 1382 P2_1_AMUXA = 4, /* Analog mux bus A */ 1383 P2_1_AMUXB = 5, /* Analog mux bus B */ 1384 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1385 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1386 P2_1_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 1387 P2_1_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 1388 P2_1_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:1 */ 1389 P2_1_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ 1390 P2_1_TCPWM0_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1551]:0 */ 1391 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 1392 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 1393 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 1394 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 1395 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 1396 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 1397 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 1398 1399 /* P2.2 */ 1400 P2_2_GPIO = 0, /* GPIO controls 'out' */ 1401 P2_2_AMUXA = 4, /* Analog mux bus A */ 1402 P2_2_AMUXB = 5, /* Analog mux bus B */ 1403 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1404 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1405 P2_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 1406 P2_2_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 1407 P2_2_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:1 */ 1408 P2_2_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:1 */ 1409 P2_2_TCPWM0_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1554]:0 */ 1410 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 1411 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 1412 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 1413 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 1414 P2_2_ETH0_RX_ER = 24, /* Digital Active - eth[0].rx_er:0 */ 1415 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 1416 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 1417 1418 /* P2.3 */ 1419 P2_3_GPIO = 0, /* GPIO controls 'out' */ 1420 P2_3_AMUXA = 4, /* Analog mux bus A */ 1421 P2_3_AMUXB = 5, /* Analog mux bus B */ 1422 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1423 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1424 P2_3_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 1425 P2_3_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 1426 P2_3_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:1 */ 1427 P2_3_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:1 */ 1428 P2_3_TCPWM0_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1557]:0 */ 1429 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 1430 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 1431 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 1432 P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL = 24, /* Digital Active - eth[0].eth_tsu_timer_cmp_val:0 */ 1433 P2_3_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:1 */ 1434 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 1435 1436 /* P2.4 */ 1437 P2_4_GPIO = 0, /* GPIO controls 'out' */ 1438 P2_4_AMUXA = 4, /* Analog mux bus A */ 1439 P2_4_AMUXB = 5, /* Analog mux bus B */ 1440 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1441 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1442 P2_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 1443 P2_4_TCPWM0_LINE_COMPL4 = 9, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 1444 P2_4_TCPWM0_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[9]:1 */ 1445 P2_4_TCPWM0_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[13]:1 */ 1446 P2_4_TCPWM0_LINE_COMPL516 = 16, /* Digital Active - tcpwm[0].line_compl[516]:0 */ 1447 P2_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:0 */ 1448 P2_4_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:1 */ 1449 P2_4_PERI_TR_IO_INPUT6 = 26, /* Digital Active - peri.tr_io_input[6]:0 */ 1450 1451 /* P2.5 */ 1452 P2_5_GPIO = 0, /* GPIO controls 'out' */ 1453 P2_5_AMUXA = 4, /* Analog mux bus A */ 1454 P2_5_AMUXB = 5, /* Analog mux bus B */ 1455 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1456 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1457 P2_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 1458 P2_5_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 1459 P2_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:1 */ 1460 P2_5_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:1 */ 1461 P2_5_TCPWM0_LINE_COMPL517 = 16, /* Digital Active - tcpwm[0].line_compl[517]:0 */ 1462 P2_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:0 */ 1463 P2_5_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:1 */ 1464 P2_5_PERI_TR_IO_INPUT7 = 26, /* Digital Active - peri.tr_io_input[7]:0 */ 1465 1466 /* P2.6 */ 1467 P2_6_GPIO = 0, /* GPIO controls 'out' */ 1468 P2_6_AMUXA = 4, /* Analog mux bus A */ 1469 P2_6_AMUXB = 5, /* Analog mux bus B */ 1470 P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1471 P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1472 P2_6_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:1 */ 1473 P2_6_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:1 */ 1474 1475 /* P2.7 */ 1476 P2_7_GPIO = 0, /* GPIO controls 'out' */ 1477 P2_7_AMUXA = 4, /* Analog mux bus A */ 1478 P2_7_AMUXB = 5, /* Analog mux bus B */ 1479 P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1480 P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1481 P2_7_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:1 */ 1482 P2_7_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:1 */ 1483 1484 /* P3.0 */ 1485 P3_0_GPIO = 0, /* GPIO controls 'out' */ 1486 P3_0_AMUXA = 4, /* Analog mux bus A */ 1487 P3_0_AMUXB = 5, /* Analog mux bus B */ 1488 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1489 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1490 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 1491 P3_0_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 1492 P3_0_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ 1493 P3_0_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:1 */ 1494 P3_0_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:0 */ 1495 P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ 1496 P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ 1497 P3_0_CANFD0_TTCAN_TX3 = 21, /* Digital Active - canfd[0].ttcan_tx[3]:0 */ 1498 P3_0_ETH0_MDIO = 24, /* Digital Active - eth[0].mdio:0 */ 1499 P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 1500 1501 /* P3.1 */ 1502 P3_1_GPIO = 0, /* GPIO controls 'out' */ 1503 P3_1_AMUXA = 4, /* Analog mux bus A */ 1504 P3_1_AMUXB = 5, /* Analog mux bus B */ 1505 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1506 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1507 P3_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 1508 P3_1_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 1509 P3_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ 1510 P3_1_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:1 */ 1511 P3_1_TCPWM0_LINE_COMPL519 = 16, /* Digital Active - tcpwm[0].line_compl[519]:0 */ 1512 P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ 1513 P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ 1514 P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ 1515 P3_1_CANFD0_TTCAN_RX3 = 21, /* Digital Active - canfd[0].ttcan_rx[3]:0 */ 1516 P3_1_ETH0_MDC = 24, /* Digital Active - eth[0].mdc:0 */ 1517 P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 1518 1519 /* P3.2 */ 1520 P3_2_GPIO = 0, /* GPIO controls 'out' */ 1521 P3_2_AMUXA = 4, /* Analog mux bus A */ 1522 P3_2_AMUXB = 5, /* Analog mux bus B */ 1523 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1524 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1525 P3_2_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:1 */ 1526 P3_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 1527 P3_2_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:1 */ 1528 P3_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ 1529 P3_2_TCPWM0_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1549]:0 */ 1530 P3_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:0 */ 1531 P3_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:0 */ 1532 P3_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:0 */ 1533 1534 /* P3.3 */ 1535 P3_3_GPIO = 0, /* GPIO controls 'out' */ 1536 P3_3_AMUXA = 4, /* Analog mux bus A */ 1537 P3_3_AMUXB = 5, /* Analog mux bus B */ 1538 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1539 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1540 P3_3_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:1 */ 1541 P3_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ 1542 P3_3_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:1 */ 1543 P3_3_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:1 */ 1544 P3_3_TCPWM0_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1552]:0 */ 1545 P3_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:0 */ 1546 P3_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:0 */ 1547 1548 /* P3.4 */ 1549 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1550 P3_4_AMUXA = 4, /* Analog mux bus A */ 1551 P3_4_AMUXB = 5, /* Analog mux bus B */ 1552 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1553 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1554 P3_4_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:1 */ 1555 P3_4_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ 1556 P3_4_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:1 */ 1557 P3_4_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:1 */ 1558 P3_4_TCPWM0_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1555]:0 */ 1559 P3_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:0 */ 1560 P3_4_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:2 */ 1561 1562 /* P3.5 */ 1563 P3_5_GPIO = 0, /* GPIO controls 'out' */ 1564 P3_5_AMUXA = 4, /* Analog mux bus A */ 1565 P3_5_AMUXB = 5, /* Analog mux bus B */ 1566 P3_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1567 P3_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1568 P3_5_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:1 */ 1569 P3_5_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ 1570 P3_5_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:1 */ 1571 P3_5_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:1 */ 1572 P3_5_TCPWM0_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1558]:0 */ 1573 P3_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:0 */ 1574 P3_5_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:2 */ 1575 1576 /* P3.6 */ 1577 P3_6_GPIO = 0, /* GPIO controls 'out' */ 1578 P3_6_AMUXA = 4, /* Analog mux bus A */ 1579 P3_6_AMUXB = 5, /* Analog mux bus B */ 1580 P3_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1581 P3_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1582 P3_6_SCB8_SPI_SELECT2 = 19, /* Digital Active - scb[8].spi_select2:0 */ 1583 P3_6_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:1 */ 1584 P3_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:2 */ 1585 1586 /* P3.7 */ 1587 P3_7_GPIO = 0, /* GPIO controls 'out' */ 1588 P3_7_AMUXA = 4, /* Analog mux bus A */ 1589 P3_7_AMUXB = 5, /* Analog mux bus B */ 1590 P3_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1591 P3_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1592 P3_7_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:1 */ 1593 P3_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:2 */ 1594 1595 /* P4.0 */ 1596 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1597 P4_0_AMUXA = 4, /* Analog mux bus A */ 1598 P4_0_AMUXB = 5, /* Analog mux bus B */ 1599 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1600 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1601 P4_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 1602 P4_0_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ 1603 P4_0_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:0 */ 1604 P4_0_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:1 */ 1605 P4_0_PASS0_SAR_EXT_MUX_SEL0 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[0] */ 1606 P4_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:0 */ 1607 P4_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:0 */ 1608 P4_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:1 */ 1609 P4_0_PERI_TR_IO_INPUT10 = 26, /* Digital Active - peri.tr_io_input[10]:0 */ 1610 1611 /* P4.1 */ 1612 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1613 P4_1_AMUXA = 4, /* Analog mux bus A */ 1614 P4_1_AMUXB = 5, /* Analog mux bus B */ 1615 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1616 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1617 P4_1_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 1618 P4_1_TCPWM0_LINE_COMPL4 = 9, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 1619 P4_1_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:0 */ 1620 P4_1_TCPWM0_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[13]:0 */ 1621 P4_1_PASS0_SAR_EXT_MUX_SEL1 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[1] */ 1622 P4_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:0 */ 1623 P4_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:0 */ 1624 P4_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:0 */ 1625 P4_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:1 */ 1626 P4_1_PERI_TR_IO_INPUT11 = 26, /* Digital Active - peri.tr_io_input[11]:0 */ 1627 1628 /* P4.2 */ 1629 P4_2_GPIO = 0, /* GPIO controls 'out' */ 1630 P4_2_AMUXA = 4, /* Analog mux bus A */ 1631 P4_2_AMUXB = 5, /* Analog mux bus B */ 1632 P4_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1633 P4_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1634 P4_2_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ 1635 P4_2_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:0 */ 1636 P4_2_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:0 */ 1637 P4_2_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:0 */ 1638 P4_2_PASS0_SAR_EXT_MUX_SEL2 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[2] */ 1639 P4_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:0 */ 1640 P4_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:0 */ 1641 P4_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:0 */ 1642 P4_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:1 */ 1643 P4_2_PERI_TR_IO_INPUT12 = 26, /* Digital Active - peri.tr_io_input[12]:0 */ 1644 1645 /* P4.3 */ 1646 P4_3_GPIO = 0, /* GPIO controls 'out' */ 1647 P4_3_AMUXA = 4, /* Analog mux bus A */ 1648 P4_3_AMUXB = 5, /* Analog mux bus B */ 1649 P4_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1650 P4_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1651 P4_3_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 1652 P4_3_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:0 */ 1653 P4_3_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:0 */ 1654 P4_3_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:0 */ 1655 P4_3_PASS0_SAR_EXT_MUX_EN0 = 16, /* Digital Active - pass[0].sar_ext_mux_en[0] */ 1656 P4_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:0 */ 1657 P4_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:0 */ 1658 P4_3_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:1 */ 1659 P4_3_PERI_TR_IO_INPUT13 = 26, /* Digital Active - peri.tr_io_input[13]:0 */ 1660 1661 /* P4.4 */ 1662 P4_4_GPIO = 0, /* GPIO controls 'out' */ 1663 P4_4_AMUXA = 4, /* Analog mux bus A */ 1664 P4_4_AMUXB = 5, /* Analog mux bus B */ 1665 P4_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1666 P4_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1667 P4_4_TCPWM0_LINE8 = 8, /* Digital Active - tcpwm[0].line[8]:0 */ 1668 P4_4_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:0 */ 1669 P4_4_TCPWM0_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[24]:0 */ 1670 P4_4_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:0 */ 1671 P4_4_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:1 */ 1672 P4_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:0 */ 1673 P4_4_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:1 */ 1674 1675 /* P5.0 */ 1676 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1677 P5_0_AMUXA = 4, /* Analog mux bus A */ 1678 P5_0_AMUXB = 5, /* Analog mux bus B */ 1679 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1680 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1681 P5_0_TCPWM0_LINE9 = 8, /* Digital Active - tcpwm[0].line[9]:0 */ 1682 P5_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:0 */ 1683 P5_0_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ 1684 P5_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ 1685 P5_0_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:1 */ 1686 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 1687 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 1688 1689 /* P5.1 */ 1690 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1691 P5_1_AMUXA = 4, /* Analog mux bus A */ 1692 P5_1_AMUXB = 5, /* Analog mux bus B */ 1693 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1694 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1695 P5_1_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:0 */ 1696 P5_1_TCPWM0_LINE_COMPL9 = 9, /* Digital Active - tcpwm[0].line_compl[9]:0 */ 1697 P5_1_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ 1698 P5_1_TCPWM0_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ 1699 P5_1_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:1 */ 1700 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 1701 1702 /* P5.2 */ 1703 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1704 P5_2_AMUXA = 4, /* Analog mux bus A */ 1705 P5_2_AMUXB = 5, /* Analog mux bus B */ 1706 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1707 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1708 P5_2_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:0 */ 1709 P5_2_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:0 */ 1710 P5_2_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:0 */ 1711 P5_2_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:0 */ 1712 P5_2_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:2 */ 1713 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 1714 1715 /* P5.3 */ 1716 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1717 P5_3_AMUXA = 4, /* Analog mux bus A */ 1718 P5_3_AMUXB = 5, /* Analog mux bus B */ 1719 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1720 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1721 P5_3_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:0 */ 1722 P5_3_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:0 */ 1723 P5_3_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:0 */ 1724 P5_3_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:0 */ 1725 P5_3_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:2 */ 1726 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 1727 1728 /* P5.4 */ 1729 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1730 P5_4_AMUXA = 4, /* Analog mux bus A */ 1731 P5_4_AMUXB = 5, /* Analog mux bus B */ 1732 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1733 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1734 P5_4_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:0 */ 1735 P5_4_TCPWM0_LINE_COMPL12 = 9, /* Digital Active - tcpwm[0].line_compl[12]:0 */ 1736 P5_4_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:0 */ 1737 P5_4_TCPWM0_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:0 */ 1738 P5_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:0 */ 1739 P5_4_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:1 */ 1740 1741 /* P5.5 */ 1742 P5_5_GPIO = 0, /* GPIO controls 'out' */ 1743 P5_5_AMUXA = 4, /* Analog mux bus A */ 1744 P5_5_AMUXB = 5, /* Analog mux bus B */ 1745 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1746 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1747 P5_5_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:0 */ 1748 P5_5_TCPWM0_LINE_COMPL13 = 9, /* Digital Active - tcpwm[0].line_compl[13]:0 */ 1749 P5_5_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:0 */ 1750 P5_5_TCPWM0_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[40]:0 */ 1751 P5_5_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:0 */ 1752 P5_5_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:1 */ 1753 1754 /* P6.0 */ 1755 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1756 P6_0_AMUXA = 4, /* Analog mux bus A */ 1757 P6_0_AMUXB = 5, /* Analog mux bus B */ 1758 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1759 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1760 P6_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ 1761 P6_0_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:0 */ 1762 P6_0_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:0 */ 1763 P6_0_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:0 */ 1764 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 1765 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 1766 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 1767 P6_0_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:1 */ 1768 1769 /* P6.1 */ 1770 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1771 P6_1_AMUXA = 4, /* Analog mux bus A */ 1772 P6_1_AMUXB = 5, /* Analog mux bus B */ 1773 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1774 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1775 P6_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 1776 P6_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 1777 P6_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 1778 P6_1_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:0 */ 1779 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 1780 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 1781 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 1782 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 1783 1784 /* P6.2 */ 1785 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1786 P6_2_AMUXA = 4, /* Analog mux bus A */ 1787 P6_2_AMUXB = 5, /* Analog mux bus B */ 1788 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1789 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1790 P6_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ 1791 P6_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 1792 P6_2_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:0 */ 1793 P6_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 1794 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 1795 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 1796 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 1797 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 1798 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 1799 P6_2_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:0 */ 1800 1801 /* P6.3 */ 1802 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1803 P6_3_AMUXA = 4, /* Analog mux bus A */ 1804 P6_3_AMUXB = 5, /* Analog mux bus B */ 1805 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1806 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1807 P6_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 1808 P6_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 1809 P6_3_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 1810 P6_3_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:0 */ 1811 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 1812 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 1813 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 1814 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 1815 P6_3_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:0 */ 1816 P6_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:0 */ 1817 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 1818 1819 /* P6.4 */ 1820 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1821 P6_4_AMUXA = 4, /* Analog mux bus A */ 1822 P6_4_AMUXB = 5, /* Analog mux bus B */ 1823 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1824 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1825 P6_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ 1826 P6_4_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 1827 P6_4_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:0 */ 1828 P6_4_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:0 */ 1829 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 1830 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 1831 P6_4_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:0 */ 1832 P6_4_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:0 */ 1833 1834 /* P6.5 */ 1835 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1836 P6_5_AMUXA = 4, /* Analog mux bus A */ 1837 P6_5_AMUXB = 5, /* Analog mux bus B */ 1838 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1839 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1840 P6_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 1841 P6_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 1842 P6_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:0 */ 1843 P6_5_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:0 */ 1844 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 1845 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 1846 P6_5_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:0 */ 1847 P6_5_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:0 */ 1848 1849 /* P6.6 */ 1850 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1851 P6_6_AMUXA = 4, /* Analog mux bus A */ 1852 P6_6_AMUXB = 5, /* Analog mux bus B */ 1853 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1854 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1855 P6_6_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:0 */ 1856 P6_6_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 1857 P6_6_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:0 */ 1858 P6_6_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:0 */ 1859 P6_6_SCB4_SPI_SELECT3 = 19, /* Digital Active - scb[4].spi_select3:0 */ 1860 P6_6_PERI_TR_IO_INPUT8 = 26, /* Digital Active - peri.tr_io_input[8]:0 */ 1861 1862 /* P6.7 */ 1863 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1864 P6_7_AMUXA = 4, /* Analog mux bus A */ 1865 P6_7_AMUXB = 5, /* Analog mux bus B */ 1866 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1867 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1868 P6_7_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 1869 P6_7_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ 1870 P6_7_TCPWM0_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[9]:0 */ 1871 P6_7_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:0 */ 1872 P6_7_PERI_TR_IO_INPUT9 = 26, /* Digital Active - peri.tr_io_input[9]:0 */ 1873 1874 /* P7.0 */ 1875 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1876 P7_0_AMUXA = 4, /* Analog mux bus A */ 1877 P7_0_AMUXB = 5, /* Analog mux bus B */ 1878 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1879 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1880 P7_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ 1881 P7_0_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 1882 P7_0_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:0 */ 1883 P7_0_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:0 */ 1884 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 1885 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 1886 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 1887 P7_0_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:0 */ 1888 P7_0_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:0 */ 1889 1890 /* P7.1 */ 1891 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1892 P7_1_AMUXA = 4, /* Analog mux bus A */ 1893 P7_1_AMUXB = 5, /* Analog mux bus B */ 1894 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1895 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1896 P7_1_TCPWM0_LINE15 = 8, /* Digital Active - tcpwm[0].line[15]:0 */ 1897 P7_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 1898 P7_1_TCPWM0_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[45]:0 */ 1899 P7_1_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:0 */ 1900 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 1901 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 1902 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 1903 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 1904 P7_1_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:0 */ 1905 P7_1_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:0 */ 1906 1907 /* P7.2 */ 1908 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1909 P7_2_AMUXA = 4, /* Analog mux bus A */ 1910 P7_2_AMUXB = 5, /* Analog mux bus B */ 1911 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1912 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1913 P7_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ 1914 P7_2_TCPWM0_LINE_COMPL15 = 9, /* Digital Active - tcpwm[0].line_compl[15]:0 */ 1915 P7_2_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:0 */ 1916 P7_2_TCPWM0_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[46]:0 */ 1917 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 1918 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 1919 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 1920 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 1921 P7_2_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:0 */ 1922 P7_2_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:0 */ 1923 1924 /* P7.3 */ 1925 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1926 P7_3_AMUXA = 4, /* Analog mux bus A */ 1927 P7_3_AMUXB = 5, /* Analog mux bus B */ 1928 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1929 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1930 P7_3_TCPWM0_LINE16 = 8, /* Digital Active - tcpwm[0].line[16]:0 */ 1931 P7_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 1932 P7_3_TCPWM0_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[48]:0 */ 1933 P7_3_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:0 */ 1934 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 1935 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 1936 P7_3_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:0 */ 1937 P7_3_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:0 */ 1938 1939 /* P7.4 */ 1940 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1941 P7_4_AMUXA = 4, /* Analog mux bus A */ 1942 P7_4_AMUXB = 5, /* Analog mux bus B */ 1943 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1944 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1945 P7_4_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:0 */ 1946 P7_4_TCPWM0_LINE_COMPL16 = 9, /* Digital Active - tcpwm[0].line_compl[16]:0 */ 1947 P7_4_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:0 */ 1948 P7_4_TCPWM0_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[49]:0 */ 1949 P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ 1950 P7_4_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:0 */ 1951 P7_4_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:0 */ 1952 1953 /* P7.5 */ 1954 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1955 P7_5_AMUXA = 4, /* Analog mux bus A */ 1956 P7_5_AMUXB = 5, /* Analog mux bus B */ 1957 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1958 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1959 P7_5_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:0 */ 1960 P7_5_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 1961 P7_5_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:0 */ 1962 P7_5_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:0 */ 1963 P7_5_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:0 */ 1964 P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ 1965 P7_5_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:0 */ 1966 P7_5_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:0 */ 1967 1968 /* P7.6 */ 1969 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1970 P7_6_AMUXA = 4, /* Analog mux bus A */ 1971 P7_6_AMUXB = 5, /* Analog mux bus B */ 1972 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1973 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1974 P7_6_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:0 */ 1975 P7_6_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:0 */ 1976 P7_6_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:0 */ 1977 P7_6_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:0 */ 1978 P7_6_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:0 */ 1979 P7_6_PERI_TR_IO_INPUT16 = 26, /* Digital Active - peri.tr_io_input[16]:0 */ 1980 1981 /* P7.7 */ 1982 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1983 P7_7_AMUXA = 4, /* Analog mux bus A */ 1984 P7_7_AMUXB = 5, /* Analog mux bus B */ 1985 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1986 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1987 P7_7_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:0 */ 1988 P7_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ 1989 P7_7_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:0 */ 1990 P7_7_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:0 */ 1991 P7_7_LIN0_LIN_EN10 = 18, /* Digital Active - lin[0].lin_en[10]:0 */ 1992 P7_7_PERI_TR_IO_INPUT17 = 26, /* Digital Active - peri.tr_io_input[17]:0 */ 1993 1994 /* P8.0 */ 1995 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1996 P8_0_AMUXA = 4, /* Analog mux bus A */ 1997 P8_0_AMUXB = 5, /* Analog mux bus B */ 1998 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1999 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2000 P8_0_TCPWM0_LINE19 = 8, /* Digital Active - tcpwm[0].line[19]:0 */ 2001 P8_0_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:0 */ 2002 P8_0_TCPWM0_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[57]:0 */ 2003 P8_0_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:0 */ 2004 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 2005 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 2006 P8_0_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:0 */ 2007 P8_0_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:0 */ 2008 2009 /* P8.1 */ 2010 P8_1_GPIO = 0, /* GPIO controls 'out' */ 2011 P8_1_AMUXA = 4, /* Analog mux bus A */ 2012 P8_1_AMUXB = 5, /* Analog mux bus B */ 2013 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2014 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2015 P8_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ 2016 P8_1_TCPWM0_LINE_COMPL19 = 9, /* Digital Active - tcpwm[0].line_compl[19]:0 */ 2017 P8_1_TCPWM0_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[60]:0 */ 2018 P8_1_TCPWM0_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[58]:0 */ 2019 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 2020 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 2021 P8_1_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:0 */ 2022 P8_1_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:0 */ 2023 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 2024 2025 /* P8.2 */ 2026 P8_2_GPIO = 0, /* GPIO controls 'out' */ 2027 P8_2_AMUXA = 4, /* Analog mux bus A */ 2028 P8_2_AMUXB = 5, /* Analog mux bus B */ 2029 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2030 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2031 P8_2_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:0 */ 2032 P8_2_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:0 */ 2033 P8_2_TCPWM0_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[63]:0 */ 2034 P8_2_TCPWM0_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[61]:0 */ 2035 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 2036 P8_2_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:0 */ 2037 P8_2_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:0 */ 2038 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 2039 2040 /* P8.3 */ 2041 P8_3_GPIO = 0, /* GPIO controls 'out' */ 2042 P8_3_AMUXA = 4, /* Analog mux bus A */ 2043 P8_3_AMUXB = 5, /* Analog mux bus B */ 2044 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2045 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2046 P8_3_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:0 */ 2047 P8_3_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:0 */ 2048 P8_3_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:0 */ 2049 P8_3_TCPWM0_TR_ONE_CNT_IN64 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[64]:0 */ 2050 P8_3_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:1 */ 2051 2052 /* P8.4 */ 2053 P8_4_GPIO = 0, /* GPIO controls 'out' */ 2054 P8_4_AMUXA = 4, /* Analog mux bus A */ 2055 P8_4_AMUXB = 5, /* Analog mux bus B */ 2056 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2057 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2058 P8_4_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:0 */ 2059 P8_4_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:0 */ 2060 P8_4_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:0 */ 2061 P8_4_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:0 */ 2062 P8_4_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:1 */ 2063 2064 /* P9.0 */ 2065 P9_0_GPIO = 0, /* GPIO controls 'out' */ 2066 P9_0_AMUXA = 4, /* Analog mux bus A */ 2067 P9_0_AMUXB = 5, /* Analog mux bus B */ 2068 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2069 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2070 P9_0_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:0 */ 2071 P9_0_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:0 */ 2072 P9_0_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:0 */ 2073 P9_0_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:0 */ 2074 2075 /* P9.1 */ 2076 P9_1_GPIO = 0, /* GPIO controls 'out' */ 2077 P9_1_AMUXA = 4, /* Analog mux bus A */ 2078 P9_1_AMUXB = 5, /* Analog mux bus B */ 2079 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2080 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2081 P9_1_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:0 */ 2082 P9_1_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:0 */ 2083 P9_1_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:0 */ 2084 P9_1_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:0 */ 2085 P9_1_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:0 */ 2086 2087 /* P9.2 */ 2088 P9_2_GPIO = 0, /* GPIO controls 'out' */ 2089 P9_2_AMUXA = 4, /* Analog mux bus A */ 2090 P9_2_AMUXB = 5, /* Analog mux bus B */ 2091 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2092 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2093 P9_2_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:0 */ 2094 P9_2_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:0 */ 2095 P9_2_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:0 */ 2096 P9_2_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:0 */ 2097 P9_2_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:0 */ 2098 2099 /* P9.3 */ 2100 P9_3_GPIO = 0, /* GPIO controls 'out' */ 2101 P9_3_AMUXA = 4, /* Analog mux bus A */ 2102 P9_3_AMUXB = 5, /* Analog mux bus B */ 2103 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2104 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2105 P9_3_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:0 */ 2106 P9_3_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:0 */ 2107 P9_3_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:0 */ 2108 P9_3_TCPWM0_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[79]:0 */ 2109 P9_3_LIN0_LIN_EN12 = 21, /* Digital Active - lin[0].lin_en[12]:0 */ 2110 2111 /* P10.0 */ 2112 P10_0_GPIO = 0, /* GPIO controls 'out' */ 2113 P10_0_AMUXA = 4, /* Analog mux bus A */ 2114 P10_0_AMUXB = 5, /* Analog mux bus B */ 2115 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2116 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2117 P10_0_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:0 */ 2118 P10_0_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:0 */ 2119 P10_0_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:0 */ 2120 P10_0_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:0 */ 2121 P10_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:1 */ 2122 P10_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:1 */ 2123 P10_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:2 */ 2124 P10_0_PERI_TR_IO_INPUT18 = 26, /* Digital Active - peri.tr_io_input[18]:0 */ 2125 2126 /* P10.1 */ 2127 P10_1_GPIO = 0, /* GPIO controls 'out' */ 2128 P10_1_AMUXA = 4, /* Analog mux bus A */ 2129 P10_1_AMUXB = 5, /* Analog mux bus B */ 2130 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2131 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2132 P10_1_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:0 */ 2133 P10_1_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:0 */ 2134 P10_1_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:0 */ 2135 P10_1_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:0 */ 2136 P10_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:1 */ 2137 P10_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:1 */ 2138 P10_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:1 */ 2139 P10_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:2 */ 2140 P10_1_PERI_TR_IO_INPUT19 = 26, /* Digital Active - peri.tr_io_input[19]:0 */ 2141 2142 /* P10.2 */ 2143 P10_2_GPIO = 0, /* GPIO controls 'out' */ 2144 P10_2_AMUXA = 4, /* Analog mux bus A */ 2145 P10_2_AMUXB = 5, /* Analog mux bus B */ 2146 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2147 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2148 P10_2_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:0 */ 2149 P10_2_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:0 */ 2150 P10_2_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:0 */ 2151 P10_2_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:0 */ 2152 P10_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:1 */ 2153 P10_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:1 */ 2154 P10_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:1 */ 2155 P10_2_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:1 */ 2156 2157 /* P10.3 */ 2158 P10_3_GPIO = 0, /* GPIO controls 'out' */ 2159 P10_3_AMUXA = 4, /* Analog mux bus A */ 2160 P10_3_AMUXB = 5, /* Analog mux bus B */ 2161 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2162 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2163 P10_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:0 */ 2164 P10_3_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:0 */ 2165 P10_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:0 */ 2166 P10_3_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:0 */ 2167 P10_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:1 */ 2168 P10_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:1 */ 2169 P10_3_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:1 */ 2170 2171 /* P10.4 */ 2172 P10_4_GPIO = 0, /* GPIO controls 'out' */ 2173 P10_4_AMUXA = 4, /* Analog mux bus A */ 2174 P10_4_AMUXB = 5, /* Analog mux bus B */ 2175 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2176 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2177 P10_4_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:0 */ 2178 P10_4_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:0 */ 2179 P10_4_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:0 */ 2180 P10_4_TCPWM0_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[94]:0 */ 2181 P10_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:1 */ 2182 P10_4_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:1 */ 2183 2184 /* P10.5 */ 2185 P10_5_GPIO = 0, /* GPIO controls 'out' */ 2186 P10_5_AMUXA = 4, /* Analog mux bus A */ 2187 P10_5_AMUXB = 5, /* Analog mux bus B */ 2188 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2189 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2190 P10_5_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:0 */ 2191 P10_5_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:0 */ 2192 P10_5_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:0 */ 2193 P10_5_TCPWM0_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[97]:0 */ 2194 P10_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:1 */ 2195 P10_5_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:0 */ 2196 2197 /* P10.6 */ 2198 P10_6_GPIO = 0, /* GPIO controls 'out' */ 2199 P10_6_AMUXA = 4, /* Analog mux bus A */ 2200 P10_6_AMUXB = 5, /* Analog mux bus B */ 2201 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2202 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2203 P10_6_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:0 */ 2204 P10_6_TCPWM0_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[100]:0 */ 2205 P10_6_TCPWM0_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:0 */ 2206 P10_6_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:0 */ 2207 P10_6_TCPWM0_LINE34 = 22, /* Digital Active - tcpwm[0].line[34]:0 */ 2208 2209 /* P10.7 */ 2210 P10_7_GPIO = 0, /* GPIO controls 'out' */ 2211 P10_7_AMUXA = 4, /* Analog mux bus A */ 2212 P10_7_AMUXB = 5, /* Analog mux bus B */ 2213 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2214 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2215 P10_7_TCPWM0_LINE35 = 8, /* Digital Active - tcpwm[0].line[35]:0 */ 2216 P10_7_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:0 */ 2217 P10_7_TCPWM0_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[105]:0 */ 2218 P10_7_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:0 */ 2219 P10_7_LIN0_LIN_EN13 = 21, /* Digital Active - lin[0].lin_en[13]:0 */ 2220 2221 /* P11.0 */ 2222 P11_0_GPIO = 0, /* GPIO controls 'out' */ 2223 P11_0_AMUXA = 4, /* Analog mux bus A */ 2224 P11_0_AMUXB = 5, /* Analog mux bus B */ 2225 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2226 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2227 P11_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:2 */ 2228 P11_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:2 */ 2229 P11_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:2 */ 2230 P11_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:2 */ 2231 P11_0_AUDIOSS0_MCLK = 25, /* Digital Active - audioss[0].mclk:0 */ 2232 2233 /* P11.1 */ 2234 P11_1_GPIO = 0, /* GPIO controls 'out' */ 2235 P11_1_AMUXA = 4, /* Analog mux bus A */ 2236 P11_1_AMUXB = 5, /* Analog mux bus B */ 2237 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2238 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2239 P11_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:2 */ 2240 P11_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:2 */ 2241 P11_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:2 */ 2242 P11_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:2 */ 2243 P11_1_AUDIOSS0_TX_SCK = 25, /* Digital Active - audioss[0].tx_sck:0 */ 2244 2245 /* P11.2 */ 2246 P11_2_GPIO = 0, /* GPIO controls 'out' */ 2247 P11_2_AMUXA = 4, /* Analog mux bus A */ 2248 P11_2_AMUXB = 5, /* Analog mux bus B */ 2249 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2250 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2251 P11_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:2 */ 2252 P11_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:2 */ 2253 P11_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:2 */ 2254 P11_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:2 */ 2255 P11_2_AUDIOSS0_TX_WS = 25, /* Digital Active - audioss[0].tx_ws:0 */ 2256 2257 /* P12.0 */ 2258 P12_0_GPIO = 0, /* GPIO controls 'out' */ 2259 P12_0_AMUXA = 4, /* Analog mux bus A */ 2260 P12_0_AMUXB = 5, /* Analog mux bus B */ 2261 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2262 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2263 P12_0_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ 2264 P12_0_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:0 */ 2265 P12_0_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:0 */ 2266 P12_0_TCPWM0_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:0 */ 2267 P12_0_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:0 */ 2268 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 2269 P12_0_TCPWM0_LINE_COMPL35 = 23, /* Digital Active - tcpwm[0].line_compl[35]:0 */ 2270 P12_0_AUDIOSS0_TX_SDO = 25, /* Digital Active - audioss[0].tx_sdo:0 */ 2271 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 2272 2273 /* P12.1 */ 2274 P12_1_GPIO = 0, /* GPIO controls 'out' */ 2275 P12_1_AMUXA = 4, /* Analog mux bus A */ 2276 P12_1_AMUXB = 5, /* Analog mux bus B */ 2277 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2278 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2279 P12_1_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ 2280 P12_1_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ 2281 P12_1_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:0 */ 2282 P12_1_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:0 */ 2283 P12_1_SCB8_UART_TX = 17, /* Digital Active - scb[8].uart_tx:0 */ 2284 P12_1_SCB8_I2C_SDA = 18, /* Digital Active - scb[8].i2c_sda:0 */ 2285 P12_1_SCB8_SPI_MOSI = 19, /* Digital Active - scb[8].spi_mosi:0 */ 2286 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 2287 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 2288 P12_1_AUDIOSS0_CLK_I2S_IF = 25, /* Digital Active - audioss[0].clk_i2s_if:0 */ 2289 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 2290 2291 /* P12.2 */ 2292 P12_2_GPIO = 0, /* GPIO controls 'out' */ 2293 P12_2_AMUXA = 4, /* Analog mux bus A */ 2294 P12_2_AMUXB = 5, /* Analog mux bus B */ 2295 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2296 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2297 P12_2_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:0 */ 2298 P12_2_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:0 */ 2299 P12_2_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:0 */ 2300 P12_2_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:0 */ 2301 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 2302 P12_2_SCB8_UART_RTS = 17, /* Digital Active - scb[8].uart_rts:0 */ 2303 P12_2_SCB8_I2C_SCL = 18, /* Digital Active - scb[8].i2c_scl:0 */ 2304 P12_2_SCB8_SPI_CLK = 19, /* Digital Active - scb[8].spi_clk:0 */ 2305 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 2306 P12_2_AUDIOSS0_RX_SCK = 25, /* Digital Active - audioss[0].rx_sck:0 */ 2307 2308 /* P12.3 */ 2309 P12_3_GPIO = 0, /* GPIO controls 'out' */ 2310 P12_3_AMUXA = 4, /* Analog mux bus A */ 2311 P12_3_AMUXB = 5, /* Analog mux bus B */ 2312 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2313 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2314 P12_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:0 */ 2315 P12_3_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:0 */ 2316 P12_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:0 */ 2317 P12_3_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:0 */ 2318 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 2319 P12_3_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:0 */ 2320 P12_3_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:0 */ 2321 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 2322 P12_3_AUDIOSS0_RX_WS = 25, /* Digital Active - audioss[0].rx_ws:0 */ 2323 2324 /* P12.4 */ 2325 P12_4_GPIO = 0, /* GPIO controls 'out' */ 2326 P12_4_AMUXA = 4, /* Analog mux bus A */ 2327 P12_4_AMUXB = 5, /* Analog mux bus B */ 2328 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2329 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2330 P12_4_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:0 */ 2331 P12_4_TCPWM0_LINE_COMPL39 = 9, /* Digital Active - tcpwm[0].line_compl[39]:0 */ 2332 P12_4_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:0 */ 2333 P12_4_TCPWM0_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[118]:0 */ 2334 P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 2335 P12_4_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:0 */ 2336 P12_4_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:2 */ 2337 P12_4_AUDIOSS0_RX_SDI = 25, /* Digital Active - audioss[0].rx_sdi:0 */ 2338 2339 /* P12.5 */ 2340 P12_5_GPIO = 0, /* GPIO controls 'out' */ 2341 P12_5_AMUXA = 4, /* Analog mux bus A */ 2342 P12_5_AMUXB = 5, /* Analog mux bus B */ 2343 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2344 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2345 P12_5_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:0 */ 2346 P12_5_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:0 */ 2347 P12_5_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:0 */ 2348 P12_5_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:0 */ 2349 P12_5_PASS0_SAR_EXT_MUX_SEL5 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[5] */ 2350 P12_5_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:2 */ 2351 2352 /* P12.6 */ 2353 P12_6_GPIO = 0, /* GPIO controls 'out' */ 2354 P12_6_AMUXA = 4, /* Analog mux bus A */ 2355 P12_6_AMUXB = 5, /* Analog mux bus B */ 2356 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2357 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2358 P12_6_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:0 */ 2359 P12_6_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:0 */ 2360 P12_6_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:0 */ 2361 P12_6_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:0 */ 2362 2363 /* P12.7 */ 2364 P12_7_GPIO = 0, /* GPIO controls 'out' */ 2365 P12_7_AMUXA = 4, /* Analog mux bus A */ 2366 P12_7_AMUXB = 5, /* Analog mux bus B */ 2367 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2368 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2369 P12_7_TCPWM0_LINE43 = 8, /* Digital Active - tcpwm[0].line[43]:0 */ 2370 P12_7_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:0 */ 2371 P12_7_TCPWM0_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[129]:0 */ 2372 P12_7_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:0 */ 2373 2374 /* P13.0 */ 2375 P13_0_GPIO = 0, /* GPIO controls 'out' */ 2376 P13_0_AMUXA = 4, /* Analog mux bus A */ 2377 P13_0_AMUXB = 5, /* Analog mux bus B */ 2378 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2379 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2380 P13_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ 2381 P13_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:0 */ 2382 P13_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:0 */ 2383 P13_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:0 */ 2384 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 2385 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 2386 P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ 2387 P13_0_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:0 */ 2388 P13_0_AUDIOSS1_MCLK = 25, /* Digital Active - audioss[1].mclk:0 */ 2389 2390 /* P13.1 */ 2391 P13_1_GPIO = 0, /* GPIO controls 'out' */ 2392 P13_1_AMUXA = 4, /* Analog mux bus A */ 2393 P13_1_AMUXB = 5, /* Analog mux bus B */ 2394 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2395 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2396 P13_1_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:0 */ 2397 P13_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ 2398 P13_1_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:0 */ 2399 P13_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:0 */ 2400 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 2401 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 2402 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 2403 P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ 2404 P13_1_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:0 */ 2405 P13_1_AUDIOSS1_TX_SCK = 25, /* Digital Active - audioss[1].tx_sck:0 */ 2406 2407 /* P13.2 */ 2408 P13_2_GPIO = 0, /* GPIO controls 'out' */ 2409 P13_2_AMUXA = 4, /* Analog mux bus A */ 2410 P13_2_AMUXB = 5, /* Analog mux bus B */ 2411 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2412 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2413 P13_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ 2414 P13_2_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:0 */ 2415 P13_2_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:0 */ 2416 P13_2_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:0 */ 2417 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 2418 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 2419 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 2420 P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ 2421 P13_2_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:0 */ 2422 P13_2_AUDIOSS1_TX_WS = 25, /* Digital Active - audioss[1].tx_ws:0 */ 2423 2424 /* P13.3 */ 2425 P13_3_GPIO = 0, /* GPIO controls 'out' */ 2426 P13_3_AMUXA = 4, /* Analog mux bus A */ 2427 P13_3_AMUXB = 5, /* Analog mux bus B */ 2428 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2429 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2430 P13_3_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:0 */ 2431 P13_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ 2432 P13_3_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:0 */ 2433 P13_3_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:0 */ 2434 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 2435 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 2436 P13_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:2 */ 2437 P13_3_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:0 */ 2438 P13_3_AUDIOSS1_TX_SDO = 25, /* Digital Active - audioss[1].tx_sdo:0 */ 2439 2440 /* P13.4 */ 2441 P13_4_GPIO = 0, /* GPIO controls 'out' */ 2442 P13_4_AMUXA = 4, /* Analog mux bus A */ 2443 P13_4_AMUXB = 5, /* Analog mux bus B */ 2444 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2445 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2446 P13_4_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:0 */ 2447 P13_4_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:0 */ 2448 P13_4_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:0 */ 2449 P13_4_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:0 */ 2450 P13_4_TCPWM0_LINE516 = 16, /* Digital Active - tcpwm[0].line[516]:1 */ 2451 P13_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:2 */ 2452 P13_4_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:0 */ 2453 P13_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:0 */ 2454 P13_4_AUDIOSS1_CLK_I2S_IF = 25, /* Digital Active - audioss[1].clk_i2s_if:0 */ 2455 2456 /* P13.5 */ 2457 P13_5_GPIO = 0, /* GPIO controls 'out' */ 2458 P13_5_AMUXA = 4, /* Analog mux bus A */ 2459 P13_5_AMUXB = 5, /* Analog mux bus B */ 2460 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2461 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2462 P13_5_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:0 */ 2463 P13_5_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:0 */ 2464 P13_5_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:0 */ 2465 P13_5_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:0 */ 2466 P13_5_TCPWM0_LINE_COMPL516 = 16, /* Digital Active - tcpwm[0].line_compl[516]:1 */ 2467 P13_5_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:0 */ 2468 P13_5_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:0 */ 2469 P13_5_AUDIOSS1_RX_SCK = 25, /* Digital Active - audioss[1].rx_sck:0 */ 2470 2471 /* P13.6 */ 2472 P13_6_GPIO = 0, /* GPIO controls 'out' */ 2473 P13_6_AMUXA = 4, /* Analog mux bus A */ 2474 P13_6_AMUXB = 5, /* Analog mux bus B */ 2475 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2476 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2477 P13_6_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:0 */ 2478 P13_6_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:0 */ 2479 P13_6_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:0 */ 2480 P13_6_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:0 */ 2481 P13_6_TCPWM0_LINE517 = 16, /* Digital Active - tcpwm[0].line[517]:1 */ 2482 P13_6_SCB3_SPI_SELECT3 = 21, /* Digital Active - scb[3].spi_select3:0 */ 2483 P13_6_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:0 */ 2484 P13_6_AUDIOSS1_RX_WS = 25, /* Digital Active - audioss[1].rx_ws:0 */ 2485 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 2486 2487 /* P13.7 */ 2488 P13_7_GPIO = 0, /* GPIO controls 'out' */ 2489 P13_7_AMUXA = 4, /* Analog mux bus A */ 2490 P13_7_AMUXB = 5, /* Analog mux bus B */ 2491 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2492 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2493 P13_7_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:0 */ 2494 P13_7_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:0 */ 2495 P13_7_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:0 */ 2496 P13_7_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:0 */ 2497 P13_7_TCPWM0_LINE_COMPL517 = 16, /* Digital Active - tcpwm[0].line_compl[517]:1 */ 2498 P13_7_AUDIOSS1_RX_SDI = 25, /* Digital Active - audioss[1].rx_sdi:0 */ 2499 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 2500 2501 /* P14.0 */ 2502 P14_0_GPIO = 0, /* GPIO controls 'out' */ 2503 P14_0_AMUXA = 4, /* Analog mux bus A */ 2504 P14_0_AMUXB = 5, /* Analog mux bus B */ 2505 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2506 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2507 P14_0_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:0 */ 2508 P14_0_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:0 */ 2509 P14_0_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:0 */ 2510 P14_0_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:0 */ 2511 P14_0_TCPWM0_LINE518 = 16, /* Digital Active - tcpwm[0].line[518]:1 */ 2512 P14_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:0 */ 2513 P14_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:0 */ 2514 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 2515 P14_0_AUDIOSS2_MCLK = 25, /* Digital Active - audioss[2].mclk:0 */ 2516 2517 /* P14.1 */ 2518 P14_1_GPIO = 0, /* GPIO controls 'out' */ 2519 P14_1_AMUXA = 4, /* Analog mux bus A */ 2520 P14_1_AMUXB = 5, /* Analog mux bus B */ 2521 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2522 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2523 P14_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:0 */ 2524 P14_1_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:0 */ 2525 P14_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:0 */ 2526 P14_1_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:0 */ 2527 P14_1_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:1 */ 2528 P14_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:0 */ 2529 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 2530 P14_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:0 */ 2531 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 2532 P14_1_AUDIOSS2_TX_SCK = 25, /* Digital Active - audioss[2].tx_sck:0 */ 2533 2534 /* P14.2 */ 2535 P14_2_GPIO = 0, /* GPIO controls 'out' */ 2536 P14_2_AMUXA = 4, /* Analog mux bus A */ 2537 P14_2_AMUXB = 5, /* Analog mux bus B */ 2538 P14_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2539 P14_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2540 P14_2_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:0 */ 2541 P14_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:0 */ 2542 P14_2_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:0 */ 2543 P14_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:0 */ 2544 P14_2_TCPWM0_LINE519 = 16, /* Digital Active - tcpwm[0].line[519]:1 */ 2545 P14_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:0 */ 2546 P14_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:0 */ 2547 P14_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:0 */ 2548 P14_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:1 */ 2549 2550 /* P14.3 */ 2551 P14_3_GPIO = 0, /* GPIO controls 'out' */ 2552 P14_3_AMUXA = 4, /* Analog mux bus A */ 2553 P14_3_AMUXB = 5, /* Analog mux bus B */ 2554 P14_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2555 P14_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2556 P14_3_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:0 */ 2557 P14_3_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:0 */ 2558 P14_3_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:0 */ 2559 P14_3_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:0 */ 2560 P14_3_TCPWM0_LINE_COMPL519 = 16, /* Digital Active - tcpwm[0].line_compl[519]:1 */ 2561 P14_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:0 */ 2562 P14_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:0 */ 2563 P14_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:1 */ 2564 2565 /* P14.4 */ 2566 P14_4_GPIO = 0, /* GPIO controls 'out' */ 2567 P14_4_AMUXA = 4, /* Analog mux bus A */ 2568 P14_4_AMUXB = 5, /* Analog mux bus B */ 2569 P14_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2570 P14_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2571 P14_4_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:0 */ 2572 P14_4_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:0 */ 2573 P14_4_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:0 */ 2574 P14_4_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:0 */ 2575 P14_4_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:1 */ 2576 P14_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:0 */ 2577 P14_4_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:1 */ 2578 P14_4_AUDIOSS2_TX_WS = 25, /* Digital Active - audioss[2].tx_ws:0 */ 2579 2580 /* P14.5 */ 2581 P14_5_GPIO = 0, /* GPIO controls 'out' */ 2582 P14_5_AMUXA = 4, /* Analog mux bus A */ 2583 P14_5_AMUXB = 5, /* Analog mux bus B */ 2584 P14_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2585 P14_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2586 P14_5_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:0 */ 2587 P14_5_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:0 */ 2588 P14_5_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:0 */ 2589 P14_5_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:0 */ 2590 P14_5_TCPWM0_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1549]:1 */ 2591 P14_5_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:0 */ 2592 P14_5_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:0 */ 2593 P14_5_AUDIOSS2_TX_SDO = 25, /* Digital Active - audioss[2].tx_sdo:0 */ 2594 2595 /* P14.6 */ 2596 P14_6_GPIO = 0, /* GPIO controls 'out' */ 2597 P14_6_AMUXA = 4, /* Analog mux bus A */ 2598 P14_6_AMUXB = 5, /* Analog mux bus B */ 2599 P14_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2600 P14_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2601 P14_6_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:0 */ 2602 P14_6_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:0 */ 2603 P14_6_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:0 */ 2604 P14_6_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:0 */ 2605 P14_6_TCPWM0_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1551]:1 */ 2606 P14_6_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:0 */ 2607 P14_6_PERI_TR_IO_INPUT24 = 26, /* Digital Active - peri.tr_io_input[24]:0 */ 2608 2609 /* P14.7 */ 2610 P14_7_GPIO = 0, /* GPIO controls 'out' */ 2611 P14_7_AMUXA = 4, /* Analog mux bus A */ 2612 P14_7_AMUXB = 5, /* Analog mux bus B */ 2613 P14_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2614 P14_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2615 P14_7_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:0 */ 2616 P14_7_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:0 */ 2617 P14_7_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:0 */ 2618 P14_7_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:0 */ 2619 P14_7_TCPWM0_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1552]:1 */ 2620 P14_7_LIN0_LIN_EN14 = 18, /* Digital Active - lin[0].lin_en[14]:0 */ 2621 P14_7_PERI_TR_IO_INPUT25 = 26, /* Digital Active - peri.tr_io_input[25]:0 */ 2622 2623 /* P15.0 */ 2624 P15_0_GPIO = 0, /* GPIO controls 'out' */ 2625 P15_0_AMUXA = 4, /* Analog mux bus A */ 2626 P15_0_AMUXB = 5, /* Analog mux bus B */ 2627 P15_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2628 P15_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2629 P15_0_TCPWM0_LINE56 = 8, /* Digital Active - tcpwm[0].line[56]:0 */ 2630 P15_0_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:0 */ 2631 P15_0_TCPWM0_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[168]:0 */ 2632 P15_0_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:0 */ 2633 P15_0_TCPWM0_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1554]:1 */ 2634 P15_0_SCB9_UART_RX = 17, /* Digital Active - scb[9].uart_rx:0 */ 2635 P15_0_SCB9_SPI_MISO = 19, /* Digital Active - scb[9].spi_miso:0 */ 2636 P15_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:1 */ 2637 P15_0_AUDIOSS2_CLK_I2S_IF = 25, /* Digital Active - audioss[2].clk_i2s_if:0 */ 2638 2639 /* P15.1 */ 2640 P15_1_GPIO = 0, /* GPIO controls 'out' */ 2641 P15_1_AMUXA = 4, /* Analog mux bus A */ 2642 P15_1_AMUXB = 5, /* Analog mux bus B */ 2643 P15_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2644 P15_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2645 P15_1_TCPWM0_LINE57 = 8, /* Digital Active - tcpwm[0].line[57]:0 */ 2646 P15_1_TCPWM0_LINE_COMPL56 = 9, /* Digital Active - tcpwm[0].line_compl[56]:0 */ 2647 P15_1_TCPWM0_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[171]:0 */ 2648 P15_1_TCPWM0_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[169]:0 */ 2649 P15_1_TCPWM0_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1555]:1 */ 2650 P15_1_SCB9_UART_TX = 17, /* Digital Active - scb[9].uart_tx:0 */ 2651 P15_1_SCB9_I2C_SDA = 18, /* Digital Active - scb[9].i2c_sda:0 */ 2652 P15_1_SCB9_SPI_MOSI = 19, /* Digital Active - scb[9].spi_mosi:0 */ 2653 P15_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:1 */ 2654 P15_1_AUDIOSS2_RX_SCK = 25, /* Digital Active - audioss[2].rx_sck:0 */ 2655 2656 /* P15.2 */ 2657 P15_2_GPIO = 0, /* GPIO controls 'out' */ 2658 P15_2_AMUXA = 4, /* Analog mux bus A */ 2659 P15_2_AMUXB = 5, /* Analog mux bus B */ 2660 P15_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2661 P15_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2662 P15_2_TCPWM0_LINE58 = 8, /* Digital Active - tcpwm[0].line[58]:0 */ 2663 P15_2_TCPWM0_LINE_COMPL57 = 9, /* Digital Active - tcpwm[0].line_compl[57]:0 */ 2664 P15_2_TCPWM0_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[174]:0 */ 2665 P15_2_TCPWM0_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[172]:0 */ 2666 P15_2_TCPWM0_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1557]:1 */ 2667 P15_2_SCB9_UART_RTS = 17, /* Digital Active - scb[9].uart_rts:0 */ 2668 P15_2_SCB9_I2C_SCL = 18, /* Digital Active - scb[9].i2c_scl:0 */ 2669 P15_2_SCB9_SPI_CLK = 19, /* Digital Active - scb[9].spi_clk:0 */ 2670 P15_2_AUDIOSS2_RX_WS = 25, /* Digital Active - audioss[2].rx_ws:0 */ 2671 2672 /* P15.3 */ 2673 P15_3_GPIO = 0, /* GPIO controls 'out' */ 2674 P15_3_AMUXA = 4, /* Analog mux bus A */ 2675 P15_3_AMUXB = 5, /* Analog mux bus B */ 2676 P15_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2677 P15_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2678 P15_3_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:0 */ 2679 P15_3_TCPWM0_LINE_COMPL58 = 9, /* Digital Active - tcpwm[0].line_compl[58]:0 */ 2680 P15_3_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:0 */ 2681 P15_3_TCPWM0_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[175]:0 */ 2682 P15_3_TCPWM0_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1558]:1 */ 2683 P15_3_SCB9_UART_CTS = 17, /* Digital Active - scb[9].uart_cts:0 */ 2684 P15_3_SCB9_SPI_SELECT0 = 19, /* Digital Active - scb[9].spi_select0:0 */ 2685 P15_3_AUDIOSS2_RX_SDI = 25, /* Digital Active - audioss[2].rx_sdi:0 */ 2686 2687 /* P16.0 */ 2688 P16_0_GPIO = 0, /* GPIO controls 'out' */ 2689 P16_0_AMUXA = 4, /* Analog mux bus A */ 2690 P16_0_AMUXB = 5, /* Analog mux bus B */ 2691 P16_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2692 P16_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2693 P16_0_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:0 */ 2694 P16_0_TCPWM0_LINE_COMPL59 = 9, /* Digital Active - tcpwm[0].line_compl[59]:0 */ 2695 P16_0_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:0 */ 2696 P16_0_TCPWM0_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[178]:0 */ 2697 P16_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:1 */ 2698 P16_0_SCB9_SPI_SELECT1 = 19, /* Digital Active - scb[9].spi_select1:0 */ 2699 P16_0_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:0 */ 2700 2701 /* P16.1 */ 2702 P16_1_GPIO = 0, /* GPIO controls 'out' */ 2703 P16_1_AMUXA = 4, /* Analog mux bus A */ 2704 P16_1_AMUXB = 5, /* Analog mux bus B */ 2705 P16_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2706 P16_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2707 P16_1_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:0 */ 2708 P16_1_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:0 */ 2709 P16_1_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:0 */ 2710 P16_1_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:0 */ 2711 P16_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:1 */ 2712 P16_1_SCB9_SPI_SELECT2 = 19, /* Digital Active - scb[9].spi_select2:0 */ 2713 P16_1_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:0 */ 2714 2715 /* P16.2 */ 2716 P16_2_GPIO = 0, /* GPIO controls 'out' */ 2717 P16_2_AMUXA = 4, /* Analog mux bus A */ 2718 P16_2_AMUXB = 5, /* Analog mux bus B */ 2719 P16_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2720 P16_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2721 P16_2_TCPWM0_LINE62 = 8, /* Digital Active - tcpwm[0].line[62]:0 */ 2722 P16_2_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:0 */ 2723 P16_2_TCPWM0_TR_ONE_CNT_IN186 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[186]:0 */ 2724 P16_2_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:0 */ 2725 P16_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:1 */ 2726 P16_2_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:0 */ 2727 P16_2_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:0 */ 2728 2729 /* P16.3 */ 2730 P16_3_GPIO = 0, /* GPIO controls 'out' */ 2731 P16_3_AMUXA = 4, /* Analog mux bus A */ 2732 P16_3_AMUXB = 5, /* Analog mux bus B */ 2733 P16_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2734 P16_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2735 P16_3_TCPWM0_LINE62 = 8, /* Digital Active - tcpwm[0].line[62]:1 */ 2736 P16_3_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:0 */ 2737 P16_3_TCPWM0_TR_ONE_CNT_IN186 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[186]:1 */ 2738 P16_3_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:0 */ 2739 P16_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:1 */ 2740 2741 /* P16.4 */ 2742 P16_4_GPIO = 0, /* GPIO controls 'out' */ 2743 P16_4_AMUXA = 4, /* Analog mux bus A */ 2744 P16_4_AMUXB = 5, /* Analog mux bus B */ 2745 P16_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2746 P16_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2747 2748 /* P16.5 */ 2749 P16_5_GPIO = 0, /* GPIO controls 'out' */ 2750 P16_5_AMUXA = 4, /* Analog mux bus A */ 2751 P16_5_AMUXB = 5, /* Analog mux bus B */ 2752 P16_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2753 P16_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2754 2755 /* P16.6 */ 2756 P16_6_GPIO = 0, /* GPIO controls 'out' */ 2757 P16_6_AMUXA = 4, /* Analog mux bus A */ 2758 P16_6_AMUXB = 5, /* Analog mux bus B */ 2759 P16_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2760 P16_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2761 2762 /* P16.7 */ 2763 P16_7_GPIO = 0, /* GPIO controls 'out' */ 2764 P16_7_AMUXA = 4, /* Analog mux bus A */ 2765 P16_7_AMUXB = 5, /* Analog mux bus B */ 2766 P16_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2767 P16_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2768 2769 /* P17.0 */ 2770 P17_0_GPIO = 0, /* GPIO controls 'out' */ 2771 P17_0_AMUXA = 4, /* Analog mux bus A */ 2772 P17_0_AMUXB = 5, /* Analog mux bus B */ 2773 P17_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2774 P17_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2775 P17_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:1 */ 2776 P17_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:1 */ 2777 P17_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:1 */ 2778 P17_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:1 */ 2779 P17_0_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:2 */ 2780 P17_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:0 */ 2781 2782 /* P17.1 */ 2783 P17_1_GPIO = 0, /* GPIO controls 'out' */ 2784 P17_1_AMUXA = 4, /* Analog mux bus A */ 2785 P17_1_AMUXB = 5, /* Analog mux bus B */ 2786 P17_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2787 P17_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2788 P17_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:1 */ 2789 P17_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:1 */ 2790 P17_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:1 */ 2791 P17_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:1 */ 2792 P17_1_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:1 */ 2793 P17_1_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:2 */ 2794 P17_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:0 */ 2795 2796 /* P17.2 */ 2797 P17_2_GPIO = 0, /* GPIO controls 'out' */ 2798 P17_2_AMUXA = 4, /* Analog mux bus A */ 2799 P17_2_AMUXB = 5, /* Analog mux bus B */ 2800 P17_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2801 P17_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2802 P17_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:1 */ 2803 P17_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:1 */ 2804 P17_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:1 */ 2805 P17_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:1 */ 2806 P17_2_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:1 */ 2807 P17_2_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:1 */ 2808 P17_2_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:2 */ 2809 2810 /* P17.3 */ 2811 P17_3_GPIO = 0, /* GPIO controls 'out' */ 2812 P17_3_AMUXA = 4, /* Analog mux bus A */ 2813 P17_3_AMUXB = 5, /* Analog mux bus B */ 2814 P17_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2815 P17_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2816 P17_3_TCPWM0_LINE58 = 8, /* Digital Active - tcpwm[0].line[58]:1 */ 2817 P17_3_TCPWM0_LINE_COMPL59 = 9, /* Digital Active - tcpwm[0].line_compl[59]:1 */ 2818 P17_3_TCPWM0_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[174]:1 */ 2819 P17_3_TCPWM0_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[178]:1 */ 2820 P17_3_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:1 */ 2821 P17_3_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:1 */ 2822 P17_3_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:1 */ 2823 P17_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:1 */ 2824 P17_3_PERI_TR_IO_INPUT26 = 26, /* Digital Active - peri.tr_io_input[26]:0 */ 2825 2826 /* P17.4 */ 2827 P17_4_GPIO = 0, /* GPIO controls 'out' */ 2828 P17_4_AMUXA = 4, /* Analog mux bus A */ 2829 P17_4_AMUXB = 5, /* Analog mux bus B */ 2830 P17_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2831 P17_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2832 P17_4_TCPWM0_LINE57 = 8, /* Digital Active - tcpwm[0].line[57]:1 */ 2833 P17_4_TCPWM0_LINE_COMPL58 = 9, /* Digital Active - tcpwm[0].line_compl[58]:1 */ 2834 P17_4_TCPWM0_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[171]:1 */ 2835 P17_4_TCPWM0_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[175]:1 */ 2836 P17_4_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:1 */ 2837 P17_4_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:1 */ 2838 P17_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:1 */ 2839 P17_4_PERI_TR_IO_INPUT27 = 26, /* Digital Active - peri.tr_io_input[27]:0 */ 2840 2841 /* P17.5 */ 2842 P17_5_GPIO = 0, /* GPIO controls 'out' */ 2843 P17_5_AMUXA = 4, /* Analog mux bus A */ 2844 P17_5_AMUXB = 5, /* Analog mux bus B */ 2845 P17_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2846 P17_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2847 P17_5_TCPWM0_LINE56 = 8, /* Digital Active - tcpwm[0].line[56]:1 */ 2848 P17_5_TCPWM0_LINE_COMPL57 = 9, /* Digital Active - tcpwm[0].line_compl[57]:1 */ 2849 P17_5_TCPWM0_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[168]:1 */ 2850 P17_5_TCPWM0_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[172]:1 */ 2851 P17_5_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:1 */ 2852 P17_5_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:0 */ 2853 P17_5_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:1 */ 2854 2855 /* P17.6 */ 2856 P17_6_GPIO = 0, /* GPIO controls 'out' */ 2857 P17_6_AMUXA = 4, /* Analog mux bus A */ 2858 P17_6_AMUXB = 5, /* Analog mux bus B */ 2859 P17_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2860 P17_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2861 P17_6_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:1 */ 2862 P17_6_TCPWM0_LINE_COMPL56 = 9, /* Digital Active - tcpwm[0].line_compl[56]:1 */ 2863 P17_6_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:1 */ 2864 P17_6_TCPWM0_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[169]:1 */ 2865 P17_6_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:1 */ 2866 P17_6_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:0 */ 2867 P17_6_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:1 */ 2868 2869 /* P17.7 */ 2870 P17_7_GPIO = 0, /* GPIO controls 'out' */ 2871 P17_7_AMUXA = 4, /* Analog mux bus A */ 2872 P17_7_AMUXB = 5, /* Analog mux bus B */ 2873 P17_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2874 P17_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2875 P17_7_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:1 */ 2876 P17_7_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ 2877 P17_7_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:1 */ 2878 P17_7_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:1 */ 2879 P17_7_LIN0_LIN_EN15 = 18, /* Digital Active - lin[0].lin_en[15]:0 */ 2880 P17_7_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:1 */ 2881 2882 /* P18.0 */ 2883 P18_0_GPIO = 0, /* GPIO controls 'out' */ 2884 P18_0_AMUXA = 4, /* Analog mux bus A */ 2885 P18_0_AMUXB = 5, /* Analog mux bus B */ 2886 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2887 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2888 P18_0_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:1 */ 2889 P18_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 2890 P18_0_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:1 */ 2891 P18_0_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:1 */ 2892 P18_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:0 */ 2893 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 2894 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 2895 P18_0_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:1 */ 2896 P18_0_ETH0_REF_CLK = 24, /* Digital Active - eth[0].ref_clk:0 */ 2897 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 2898 2899 /* P18.1 */ 2900 P18_1_GPIO = 0, /* GPIO controls 'out' */ 2901 P18_1_AMUXA = 4, /* Analog mux bus A */ 2902 P18_1_AMUXB = 5, /* Analog mux bus B */ 2903 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2904 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2905 P18_1_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:1 */ 2906 P18_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 2907 P18_1_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:1 */ 2908 P18_1_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:1 */ 2909 P18_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:0 */ 2910 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 2911 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 2912 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 2913 P18_1_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:1 */ 2914 P18_1_ETH0_TX_CTL = 24, /* Digital Active - eth[0].tx_ctl:0 */ 2915 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 2916 2917 /* P18.2 */ 2918 P18_2_GPIO = 0, /* GPIO controls 'out' */ 2919 P18_2_AMUXA = 4, /* Analog mux bus A */ 2920 P18_2_AMUXB = 5, /* Analog mux bus B */ 2921 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2922 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2923 P18_2_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:1 */ 2924 P18_2_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ 2925 P18_2_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:1 */ 2926 P18_2_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:1 */ 2927 P18_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:0 */ 2928 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 2929 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 2930 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 2931 P18_2_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:1 */ 2932 P18_2_ETH0_TX_ER = 24, /* Digital Active - eth[0].tx_er:0 */ 2933 2934 /* P18.3 */ 2935 P18_3_GPIO = 0, /* GPIO controls 'out' */ 2936 P18_3_AMUXA = 4, /* Analog mux bus A */ 2937 P18_3_AMUXB = 5, /* Analog mux bus B */ 2938 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2939 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2940 P18_3_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:1 */ 2941 P18_3_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:1 */ 2942 P18_3_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:1 */ 2943 P18_3_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:1 */ 2944 P18_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:0 */ 2945 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 2946 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 2947 P18_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:2 */ 2948 P18_3_ETH0_TX_CLK = 24, /* Digital Active - eth[0].tx_clk:0 */ 2949 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 2950 2951 /* P18.4 */ 2952 P18_4_GPIO = 0, /* GPIO controls 'out' */ 2953 P18_4_AMUXA = 4, /* Analog mux bus A */ 2954 P18_4_AMUXB = 5, /* Analog mux bus B */ 2955 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2956 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2957 P18_4_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:1 */ 2958 P18_4_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:1 */ 2959 P18_4_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:1 */ 2960 P18_4_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:1 */ 2961 P18_4_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:0 */ 2962 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 2963 P18_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:2 */ 2964 P18_4_ETH0_TXD0 = 24, /* Digital Active - eth[0].txd[0]:0 */ 2965 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 2966 2967 /* P18.5 */ 2968 P18_5_GPIO = 0, /* GPIO controls 'out' */ 2969 P18_5_AMUXA = 4, /* Analog mux bus A */ 2970 P18_5_AMUXB = 5, /* Analog mux bus B */ 2971 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2972 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2973 P18_5_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:1 */ 2974 P18_5_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:1 */ 2975 P18_5_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:1 */ 2976 P18_5_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:1 */ 2977 P18_5_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:0 */ 2978 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 2979 P18_5_ETH0_TXD1 = 24, /* Digital Active - eth[0].txd[1]:0 */ 2980 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 2981 2982 /* P18.6 */ 2983 P18_6_GPIO = 0, /* GPIO controls 'out' */ 2984 P18_6_AMUXA = 4, /* Analog mux bus A */ 2985 P18_6_AMUXB = 5, /* Analog mux bus B */ 2986 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2987 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2988 P18_6_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:1 */ 2989 P18_6_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:1 */ 2990 P18_6_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:1 */ 2991 P18_6_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:1 */ 2992 P18_6_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:0 */ 2993 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 2994 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 2995 P18_6_ETH0_TXD2 = 24, /* Digital Active - eth[0].txd[2]:0 */ 2996 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 2997 2998 /* P18.7 */ 2999 P18_7_GPIO = 0, /* GPIO controls 'out' */ 3000 P18_7_AMUXA = 4, /* Analog mux bus A */ 3001 P18_7_AMUXB = 5, /* Analog mux bus B */ 3002 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3003 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3004 P18_7_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:1 */ 3005 P18_7_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:1 */ 3006 P18_7_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:1 */ 3007 P18_7_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:1 */ 3008 P18_7_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:0 */ 3009 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 3010 P18_7_ETH0_TXD3 = 24, /* Digital Active - eth[0].txd[3]:0 */ 3011 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 3012 3013 /* P19.0 */ 3014 P19_0_GPIO = 0, /* GPIO controls 'out' */ 3015 P19_0_AMUXA = 4, /* Analog mux bus A */ 3016 P19_0_AMUXB = 5, /* Analog mux bus B */ 3017 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3018 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3019 P19_0_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:2 */ 3020 P19_0_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:1 */ 3021 P19_0_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:2 */ 3022 P19_0_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:1 */ 3023 P19_0_TCPWM0_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536]:0 */ 3024 P19_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:1 */ 3025 P19_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:1 */ 3026 P19_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:0 */ 3027 P19_0_ETH0_RXD0 = 24, /* Digital Active - eth[0].rxd[0]:0 */ 3028 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 3029 3030 /* P19.1 */ 3031 P19_1_GPIO = 0, /* GPIO controls 'out' */ 3032 P19_1_AMUXA = 4, /* Analog mux bus A */ 3033 P19_1_AMUXB = 5, /* Analog mux bus B */ 3034 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3035 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3036 P19_1_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:1 */ 3037 P19_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ 3038 P19_1_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:1 */ 3039 P19_1_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:2 */ 3040 P19_1_TCPWM0_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537]:0 */ 3041 P19_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:1 */ 3042 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 3043 P19_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:1 */ 3044 P19_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:0 */ 3045 P19_1_ETH0_RXD1 = 24, /* Digital Active - eth[0].rxd[1]:0 */ 3046 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 3047 3048 /* P19.2 */ 3049 P19_2_GPIO = 0, /* GPIO controls 'out' */ 3050 P19_2_AMUXA = 4, /* Analog mux bus A */ 3051 P19_2_AMUXB = 5, /* Analog mux bus B */ 3052 P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3053 P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3054 P19_2_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:2 */ 3055 P19_2_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:1 */ 3056 P19_2_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:2 */ 3057 P19_2_TCPWM0_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[79]:1 */ 3058 P19_2_TCPWM0_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539]:0 */ 3059 P19_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:1 */ 3060 P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ 3061 P19_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:1 */ 3062 P19_2_ETH0_RXD2 = 24, /* Digital Active - eth[0].rxd[2]:0 */ 3063 P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ 3064 3065 /* P19.3 */ 3066 P19_3_GPIO = 0, /* GPIO controls 'out' */ 3067 P19_3_AMUXA = 4, /* Analog mux bus A */ 3068 P19_3_AMUXB = 5, /* Analog mux bus B */ 3069 P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3070 P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3071 P19_3_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:2 */ 3072 P19_3_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:2 */ 3073 P19_3_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:2 */ 3074 P19_3_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:2 */ 3075 P19_3_TCPWM0_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540]:0 */ 3076 P19_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:1 */ 3077 P19_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:1 */ 3078 P19_3_ETH0_RXD3 = 24, /* Digital Active - eth[0].rxd[3]:0 */ 3079 P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ 3080 3081 /* P19.4 */ 3082 P19_4_GPIO = 0, /* GPIO controls 'out' */ 3083 P19_4_AMUXA = 4, /* Analog mux bus A */ 3084 P19_4_AMUXB = 5, /* Analog mux bus B */ 3085 P19_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3086 P19_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3087 P19_4_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:2 */ 3088 P19_4_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:2 */ 3089 P19_4_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:2 */ 3090 P19_4_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:2 */ 3091 P19_4_TCPWM0_TR_ONE_CNT_IN1542 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1542]:0 */ 3092 P19_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:1 */ 3093 3094 /* P20.0 */ 3095 P20_0_GPIO = 0, /* GPIO controls 'out' */ 3096 P20_0_AMUXA = 4, /* Analog mux bus A */ 3097 P20_0_AMUXB = 5, /* Analog mux bus B */ 3098 P20_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3099 P20_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3100 P20_0_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:2 */ 3101 P20_0_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:2 */ 3102 P20_0_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:2 */ 3103 P20_0_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:2 */ 3104 P20_0_TCPWM0_TR_ONE_CNT_IN1543 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1543]:0 */ 3105 P20_0_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:1 */ 3106 P20_0_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:0 */ 3107 3108 /* P20.1 */ 3109 P20_1_GPIO = 0, /* GPIO controls 'out' */ 3110 P20_1_AMUXA = 4, /* Analog mux bus A */ 3111 P20_1_AMUXB = 5, /* Analog mux bus B */ 3112 P20_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3113 P20_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3114 P20_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:1 */ 3115 P20_1_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:2 */ 3116 P20_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:1 */ 3117 P20_1_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:2 */ 3118 P20_1_TCPWM0_TR_ONE_CNT_IN1545 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1545]:0 */ 3119 P20_1_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:0 */ 3120 3121 /* P20.2 */ 3122 P20_2_GPIO = 0, /* GPIO controls 'out' */ 3123 P20_2_AMUXA = 4, /* Analog mux bus A */ 3124 P20_2_AMUXB = 5, /* Analog mux bus B */ 3125 P20_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3126 P20_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3127 P20_2_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:1 */ 3128 P20_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:1 */ 3129 P20_2_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:1 */ 3130 P20_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:1 */ 3131 P20_2_TCPWM0_TR_ONE_CNT_IN1546 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1546]:0 */ 3132 P20_2_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:0 */ 3133 3134 /* P20.3 */ 3135 P20_3_GPIO = 0, /* GPIO controls 'out' */ 3136 P20_3_AMUXA = 4, /* Analog mux bus A */ 3137 P20_3_AMUXB = 5, /* Analog mux bus B */ 3138 P20_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3139 P20_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3140 P20_3_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:1 */ 3141 P20_3_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:1 */ 3142 P20_3_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:1 */ 3143 P20_3_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:1 */ 3144 P20_3_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:1 */ 3145 P20_3_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:1 */ 3146 P20_3_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:1 */ 3147 3148 /* P20.4 */ 3149 P20_4_GPIO = 0, /* GPIO controls 'out' */ 3150 P20_4_AMUXA = 4, /* Analog mux bus A */ 3151 P20_4_AMUXB = 5, /* Analog mux bus B */ 3152 P20_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3153 P20_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3154 P20_4_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:1 */ 3155 P20_4_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:1 */ 3156 P20_4_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:1 */ 3157 P20_4_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:1 */ 3158 P20_4_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:1 */ 3159 P20_4_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:1 */ 3160 P20_4_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:1 */ 3161 P20_4_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:1 */ 3162 3163 /* P20.5 */ 3164 P20_5_GPIO = 0, /* GPIO controls 'out' */ 3165 P20_5_AMUXA = 4, /* Analog mux bus A */ 3166 P20_5_AMUXB = 5, /* Analog mux bus B */ 3167 P20_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3168 P20_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3169 P20_5_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:1 */ 3170 P20_5_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:1 */ 3171 P20_5_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:1 */ 3172 P20_5_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:1 */ 3173 P20_5_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:1 */ 3174 P20_5_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:1 */ 3175 P20_5_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:1 */ 3176 3177 /* P20.6 */ 3178 P20_6_GPIO = 0, /* GPIO controls 'out' */ 3179 P20_6_AMUXA = 4, /* Analog mux bus A */ 3180 P20_6_AMUXB = 5, /* Analog mux bus B */ 3181 P20_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3182 P20_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3183 P20_6_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:1 */ 3184 P20_6_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:1 */ 3185 P20_6_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:1 */ 3186 P20_6_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:1 */ 3187 P20_6_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:1 */ 3188 P20_6_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:1 */ 3189 3190 /* P20.7 */ 3191 P20_7_GPIO = 0, /* GPIO controls 'out' */ 3192 P20_7_AMUXA = 4, /* Analog mux bus A */ 3193 P20_7_AMUXB = 5, /* Analog mux bus B */ 3194 P20_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3195 P20_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3196 P20_7_TCPWM0_LINE43 = 8, /* Digital Active - tcpwm[0].line[43]:1 */ 3197 P20_7_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:1 */ 3198 P20_7_TCPWM0_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[129]:1 */ 3199 P20_7_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:1 */ 3200 P20_7_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:1 */ 3201 3202 /* P21.0 */ 3203 P21_0_GPIO = 0, /* GPIO controls 'out' */ 3204 P21_0_AMUXA = 4, /* Analog mux bus A */ 3205 P21_0_AMUXB = 5, /* Analog mux bus B */ 3206 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3207 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3208 P21_0_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:1 */ 3209 P21_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:1 */ 3210 P21_0_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:1 */ 3211 P21_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:1 */ 3212 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 3213 3214 /* P21.1 */ 3215 P21_1_GPIO = 0, /* GPIO controls 'out' */ 3216 P21_1_AMUXA = 4, /* Analog mux bus A */ 3217 P21_1_AMUXB = 5, /* Analog mux bus B */ 3218 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3219 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3220 P21_1_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:1 */ 3221 P21_1_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:1 */ 3222 P21_1_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:1 */ 3223 P21_1_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:1 */ 3224 3225 /* P21.2 */ 3226 P21_2_GPIO = 0, /* GPIO controls 'out' */ 3227 P21_2_AMUXA = 4, /* Analog mux bus A */ 3228 P21_2_AMUXB = 5, /* Analog mux bus B */ 3229 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3230 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3231 P21_2_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:1 */ 3232 P21_2_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:1 */ 3233 P21_2_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:1 */ 3234 P21_2_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:1 */ 3235 P21_2_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:0 */ 3236 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 3237 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 3238 3239 /* P21.3 */ 3240 P21_3_GPIO = 0, /* GPIO controls 'out' */ 3241 P21_3_AMUXA = 4, /* Analog mux bus A */ 3242 P21_3_AMUXB = 5, /* Analog mux bus B */ 3243 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3244 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3245 P21_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:1 */ 3246 P21_3_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:1 */ 3247 P21_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:1 */ 3248 P21_3_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:1 */ 3249 3250 /* P21.4 */ 3251 P21_4_GPIO = 0, /* GPIO controls 'out' */ 3252 P21_4_AMUXA = 4, /* Analog mux bus A */ 3253 P21_4_AMUXB = 5, /* Analog mux bus B */ 3254 P21_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3255 P21_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3256 P21_4_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:1 */ 3257 P21_4_TCPWM0_LINE_COMPL39 = 9, /* Digital Active - tcpwm[0].line_compl[39]:1 */ 3258 P21_4_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:1 */ 3259 P21_4_TCPWM0_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[118]:1 */ 3260 3261 /* P21.5 */ 3262 P21_5_GPIO = 0, /* GPIO controls 'out' */ 3263 P21_5_AMUXA = 4, /* Analog mux bus A */ 3264 P21_5_AMUXB = 5, /* Analog mux bus B */ 3265 P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3266 P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3267 P21_5_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:1 */ 3268 P21_5_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:1 */ 3269 P21_5_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:1 */ 3270 P21_5_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:1 */ 3271 P21_5_TCPWM0_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:1 */ 3272 P21_5_TCPWM0_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:1 */ 3273 P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ 3274 P21_5_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 3275 P21_5_TCPWM0_LINE34 = 22, /* Digital Active - tcpwm[0].line[34]:1 */ 3276 P21_5_TCPWM0_LINE_COMPL35 = 23, /* Digital Active - tcpwm[0].line_compl[35]:1 */ 3277 P21_5_ETH0_RX_CTL = 24, /* Digital Active - eth[0].rx_ctl:0 */ 3278 P21_5_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 3279 3280 /* P21.6 */ 3281 P21_6_GPIO = 0, /* GPIO controls 'out' */ 3282 P21_6_AMUXA = 4, /* Analog mux bus A */ 3283 P21_6_AMUXB = 5, /* Analog mux bus B */ 3284 P21_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3285 P21_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3286 P21_6_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:1 */ 3287 P21_6_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:1 */ 3288 P21_6_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:1 */ 3289 P21_6_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:1 */ 3290 P21_6_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:1 */ 3291 P21_6_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:1 */ 3292 P21_6_CPUSS_CLK_FM_PUMP = 26, /* Digital Active - cpuss.clk_fm_pump */ 3293 3294 /* P21.7 */ 3295 P21_7_GPIO = 0, /* GPIO controls 'out' */ 3296 P21_7_AMUXA = 4, /* Analog mux bus A */ 3297 P21_7_AMUXB = 5, /* Analog mux bus B */ 3298 P21_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3299 P21_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3300 P21_7_TCPWM0_LINE35 = 8, /* Digital Active - tcpwm[0].line[35]:1 */ 3301 P21_7_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:1 */ 3302 P21_7_TCPWM0_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[105]:1 */ 3303 P21_7_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:1 */ 3304 P21_7_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ 3305 P21_7_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ 3306 P21_7_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:1 */ 3307 P21_7_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:1 */ 3308 P21_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:1 */ 3309 P21_7_SRSS_CAL_WAVE = 29, /* Digital Deep Sleep - srss.cal_wave:0 */ 3310 3311 /* P22.1 */ 3312 P22_1_GPIO = 0, /* GPIO controls 'out' */ 3313 P22_1_AMUXA = 4, /* Analog mux bus A */ 3314 P22_1_AMUXB = 5, /* Analog mux bus B */ 3315 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3316 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3317 P22_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:1 */ 3318 P22_1_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:1 */ 3319 P22_1_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:1 */ 3320 P22_1_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:1 */ 3321 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 3322 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 3323 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 3324 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 3325 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 3326 3327 /* P22.2 */ 3328 P22_2_GPIO = 0, /* GPIO controls 'out' */ 3329 P22_2_AMUXA = 4, /* Analog mux bus A */ 3330 P22_2_AMUXB = 5, /* Analog mux bus B */ 3331 P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3332 P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3333 P22_2_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:1 */ 3334 P22_2_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:1 */ 3335 P22_2_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:1 */ 3336 P22_2_TCPWM0_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[100]:1 */ 3337 P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ 3338 P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ 3339 P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ 3340 P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 3341 3342 /* P22.3 */ 3343 P22_3_GPIO = 0, /* GPIO controls 'out' */ 3344 P22_3_AMUXA = 4, /* Analog mux bus A */ 3345 P22_3_AMUXB = 5, /* Analog mux bus B */ 3346 P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3347 P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3348 P22_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:1 */ 3349 P22_3_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:1 */ 3350 P22_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:1 */ 3351 P22_3_TCPWM0_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[97]:1 */ 3352 P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ 3353 P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ 3354 P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 3355 3356 /* P22.4 */ 3357 P22_4_GPIO = 0, /* GPIO controls 'out' */ 3358 P22_4_AMUXA = 4, /* Analog mux bus A */ 3359 P22_4_AMUXB = 5, /* Analog mux bus B */ 3360 P22_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3361 P22_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3362 P22_4_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:1 */ 3363 P22_4_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:1 */ 3364 P22_4_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:1 */ 3365 P22_4_TCPWM0_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[94]:1 */ 3366 P22_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:1 */ 3367 P22_4_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:1 */ 3368 3369 /* P22.5 */ 3370 P22_5_GPIO = 0, /* GPIO controls 'out' */ 3371 P22_5_AMUXA = 4, /* Analog mux bus A */ 3372 P22_5_AMUXB = 5, /* Analog mux bus B */ 3373 P22_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3374 P22_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3375 P22_5_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:1 */ 3376 P22_5_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:1 */ 3377 P22_5_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:1 */ 3378 P22_5_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:1 */ 3379 P22_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:1 */ 3380 P22_5_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:1 */ 3381 3382 /* P22.6 */ 3383 P22_6_GPIO = 0, /* GPIO controls 'out' */ 3384 P22_6_AMUXA = 4, /* Analog mux bus A */ 3385 P22_6_AMUXB = 5, /* Analog mux bus B */ 3386 P22_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3387 P22_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3388 P22_6_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:1 */ 3389 P22_6_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:1 */ 3390 P22_6_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:1 */ 3391 P22_6_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:1 */ 3392 P22_6_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:1 */ 3393 3394 /* P22.7 */ 3395 P22_7_GPIO = 0, /* GPIO controls 'out' */ 3396 P22_7_AMUXA = 4, /* Analog mux bus A */ 3397 P22_7_AMUXB = 5, /* Analog mux bus B */ 3398 P22_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3399 P22_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3400 P22_7_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:1 */ 3401 P22_7_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:1 */ 3402 P22_7_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:1 */ 3403 P22_7_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:1 */ 3404 P22_7_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:1 */ 3405 P22_7_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:1 */ 3406 3407 /* P23.0 */ 3408 P23_0_GPIO = 0, /* GPIO controls 'out' */ 3409 P23_0_AMUXA = 4, /* Analog mux bus A */ 3410 P23_0_AMUXB = 5, /* Analog mux bus B */ 3411 P23_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3412 P23_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3413 P23_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:1 */ 3414 P23_0_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:1 */ 3415 P23_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:1 */ 3416 P23_0_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:1 */ 3417 P23_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:1 */ 3418 P23_0_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:1 */ 3419 P23_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:1 */ 3420 P23_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:1 */ 3421 P23_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:1 */ 3422 3423 /* P23.1 */ 3424 P23_1_GPIO = 0, /* GPIO controls 'out' */ 3425 P23_1_AMUXA = 4, /* Analog mux bus A */ 3426 P23_1_AMUXB = 5, /* Analog mux bus B */ 3427 P23_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3428 P23_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3429 P23_1_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:1 */ 3430 P23_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:1 */ 3431 P23_1_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:1 */ 3432 P23_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:1 */ 3433 P23_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:1 */ 3434 P23_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:1 */ 3435 P23_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:1 */ 3436 P23_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:1 */ 3437 P23_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:1 */ 3438 3439 /* P23.2 */ 3440 P23_2_GPIO = 0, /* GPIO controls 'out' */ 3441 P23_2_AMUXA = 4, /* Analog mux bus A */ 3442 P23_2_AMUXB = 5, /* Analog mux bus B */ 3443 P23_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3444 P23_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3445 P23_2_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:1 */ 3446 P23_2_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:1 */ 3447 P23_2_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:1 */ 3448 P23_2_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:1 */ 3449 P23_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:1 */ 3450 P23_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:1 */ 3451 P23_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:1 */ 3452 P23_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:2 */ 3453 P23_2_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:1 */ 3454 3455 /* P23.3 */ 3456 P23_3_GPIO = 0, /* GPIO controls 'out' */ 3457 P23_3_AMUXA = 4, /* Analog mux bus A */ 3458 P23_3_AMUXB = 5, /* Analog mux bus B */ 3459 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3460 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3461 P23_3_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:1 */ 3462 P23_3_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:1 */ 3463 P23_3_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:1 */ 3464 P23_3_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:1 */ 3465 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 3466 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 3467 P23_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:2 */ 3468 P23_3_ETH0_RX_CLK = 24, /* Digital Active - eth[0].rx_clk:0 */ 3469 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 3470 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 3471 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 3472 3473 /* P23.4 */ 3474 P23_4_GPIO = 0, /* GPIO controls 'out' */ 3475 P23_4_AMUXA = 4, /* Analog mux bus A */ 3476 P23_4_AMUXB = 5, /* Analog mux bus B */ 3477 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3478 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3479 P23_4_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ 3480 P23_4_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:1 */ 3481 P23_4_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:1 */ 3482 P23_4_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:1 */ 3483 P23_4_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:2 */ 3484 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 3485 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 3486 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 3487 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 3488 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 3489 3490 /* P23.5 */ 3491 P23_5_GPIO = 0, /* GPIO controls 'out' */ 3492 P23_5_AMUXA = 4, /* Analog mux bus A */ 3493 P23_5_AMUXB = 5, /* Analog mux bus B */ 3494 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3495 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3496 P23_5_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ 3497 P23_5_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ 3498 P23_5_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:1 */ 3499 P23_5_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:1 */ 3500 P23_5_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:2 */ 3501 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 3502 P23_5_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:0 */ 3503 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 3504 3505 /* P23.6 */ 3506 P23_6_GPIO = 0, /* GPIO controls 'out' */ 3507 P23_6_AMUXA = 4, /* Analog mux bus A */ 3508 P23_6_AMUXB = 5, /* Analog mux bus B */ 3509 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3510 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3511 P23_6_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ 3512 P23_6_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ 3513 P23_6_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:1 */ 3514 P23_6_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:1 */ 3515 P23_6_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:2 */ 3516 P23_6_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:0 */ 3517 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 3518 3519 /* P23.7 */ 3520 P23_7_GPIO = 0, /* GPIO controls 'out' */ 3521 P23_7_AMUXA = 4, /* Analog mux bus A */ 3522 P23_7_AMUXB = 5, /* Analog mux bus B */ 3523 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3524 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3525 P23_7_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ 3526 P23_7_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ 3527 P23_7_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:1 */ 3528 P23_7_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:1 */ 3529 P23_7_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:2 */ 3530 P23_7_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:1 */ 3531 P23_7_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:0 */ 3532 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 3533 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 3534 P23_7_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 3535 3536 /* P24.0 */ 3537 P24_0_GPIO = 0, /* GPIO controls 'out' */ 3538 P24_0_AMUXA = 4, /* Analog mux bus A */ 3539 P24_0_AMUXB = 5, /* Analog mux bus B */ 3540 P24_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3541 P24_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3542 P24_0_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:2 */ 3543 P24_0_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:1 */ 3544 3545 /* P24.1 */ 3546 P24_1_GPIO = 0, /* GPIO controls 'out' */ 3547 P24_1_AMUXA = 4, /* Analog mux bus A */ 3548 P24_1_AMUXB = 5, /* Analog mux bus B */ 3549 P24_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3550 P24_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3551 P24_1_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:1 */ 3552 P24_1_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:1 */ 3553 3554 /* P24.2 */ 3555 P24_2_GPIO = 0, /* GPIO controls 'out' */ 3556 P24_2_AMUXA = 4, /* Analog mux bus A */ 3557 P24_2_AMUXB = 5, /* Analog mux bus B */ 3558 P24_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3559 P24_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3560 P24_2_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:1 */ 3561 P24_2_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:1 */ 3562 3563 /* P24.3 */ 3564 P24_3_GPIO = 0, /* GPIO controls 'out' */ 3565 P24_3_AMUXA = 4, /* Analog mux bus A */ 3566 P24_3_AMUXB = 5, /* Analog mux bus B */ 3567 P24_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3568 P24_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3569 P24_3_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:1 */ 3570 P24_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:1 */ 3571 3572 /* P24.4 */ 3573 P24_4_GPIO = 0, /* GPIO controls 'out' */ 3574 P24_4_AMUXA = 4, /* Analog mux bus A */ 3575 P24_4_AMUXB = 5, /* Analog mux bus B */ 3576 P24_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3577 P24_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3578 P24_4_SRSS_DDFT_CLK_DIRECT = 22, /* Digital Active - srss.ddft_clk_direct */ 3579 P24_4_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:1 */ 3580 P24_4_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:1 */ 3581 3582 /* P25.0 */ 3583 P25_0_GPIO = 0, /* GPIO controls 'out' */ 3584 P25_0_AMUXA = 4, /* Analog mux bus A */ 3585 P25_0_AMUXB = 5, /* Analog mux bus B */ 3586 P25_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3587 P25_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3588 P25_0_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:1 */ 3589 P25_0_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:1 */ 3590 3591 /* P25.1 */ 3592 P25_1_GPIO = 0, /* GPIO controls 'out' */ 3593 P25_1_AMUXA = 4, /* Analog mux bus A */ 3594 P25_1_AMUXB = 5, /* Analog mux bus B */ 3595 P25_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3596 P25_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3597 P25_1_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:1 */ 3598 P25_1_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:1 */ 3599 3600 /* P25.2 */ 3601 P25_2_GPIO = 0, /* GPIO controls 'out' */ 3602 P25_2_AMUXA = 4, /* Analog mux bus A */ 3603 P25_2_AMUXB = 5, /* Analog mux bus B */ 3604 P25_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3605 P25_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3606 P25_2_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:1 */ 3607 P25_2_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:1 */ 3608 3609 /* P25.3 */ 3610 P25_3_GPIO = 0, /* GPIO controls 'out' */ 3611 P25_3_AMUXA = 4, /* Analog mux bus A */ 3612 P25_3_AMUXB = 5, /* Analog mux bus B */ 3613 P25_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3614 P25_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3615 P25_3_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:1 */ 3616 P25_3_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:1 */ 3617 3618 /* P25.4 */ 3619 P25_4_GPIO = 0, /* GPIO controls 'out' */ 3620 P25_4_AMUXA = 4, /* Analog mux bus A */ 3621 P25_4_AMUXB = 5, /* Analog mux bus B */ 3622 P25_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3623 P25_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3624 P25_4_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:1 */ 3625 P25_4_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:1 */ 3626 3627 /* P25.5 */ 3628 P25_5_GPIO = 0, /* GPIO controls 'out' */ 3629 P25_5_AMUXA = 4, /* Analog mux bus A */ 3630 P25_5_AMUXB = 5, /* Analog mux bus B */ 3631 P25_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3632 P25_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3633 P25_5_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:1 */ 3634 P25_5_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:1 */ 3635 3636 /* P25.6 */ 3637 P25_6_GPIO = 0, /* GPIO controls 'out' */ 3638 P25_6_AMUXA = 4, /* Analog mux bus A */ 3639 P25_6_AMUXB = 5, /* Analog mux bus B */ 3640 P25_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3641 P25_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3642 P25_6_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:1 */ 3643 P25_6_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:1 */ 3644 3645 /* P25.7 */ 3646 P25_7_GPIO = 0, /* GPIO controls 'out' */ 3647 P25_7_AMUXA = 4, /* Analog mux bus A */ 3648 P25_7_AMUXB = 5, /* Analog mux bus B */ 3649 P25_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3650 P25_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3651 P25_7_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:1 */ 3652 P25_7_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:1 */ 3653 3654 /* P26.0 */ 3655 P26_0_GPIO = 0, /* GPIO controls 'out' */ 3656 P26_0_AMUXA = 4, /* Analog mux bus A */ 3657 P26_0_AMUXB = 5, /* Analog mux bus B */ 3658 P26_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3659 P26_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3660 3661 /* P26.1 */ 3662 P26_1_GPIO = 0, /* GPIO controls 'out' */ 3663 P26_1_AMUXA = 4, /* Analog mux bus A */ 3664 P26_1_AMUXB = 5, /* Analog mux bus B */ 3665 P26_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3666 P26_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3667 3668 /* P26.2 */ 3669 P26_2_GPIO = 0, /* GPIO controls 'out' */ 3670 P26_2_AMUXA = 4, /* Analog mux bus A */ 3671 P26_2_AMUXB = 5, /* Analog mux bus B */ 3672 P26_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3673 P26_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3674 3675 /* P26.3 */ 3676 P26_3_GPIO = 0, /* GPIO controls 'out' */ 3677 P26_3_AMUXA = 4, /* Analog mux bus A */ 3678 P26_3_AMUXB = 5, /* Analog mux bus B */ 3679 P26_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3680 P26_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3681 3682 /* P26.4 */ 3683 P26_4_GPIO = 0, /* GPIO controls 'out' */ 3684 P26_4_AMUXA = 4, /* Analog mux bus A */ 3685 P26_4_AMUXB = 5, /* Analog mux bus B */ 3686 P26_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3687 P26_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3688 3689 /* P26.5 */ 3690 P26_5_GPIO = 0, /* GPIO controls 'out' */ 3691 P26_5_AMUXA = 4, /* Analog mux bus A */ 3692 P26_5_AMUXB = 5, /* Analog mux bus B */ 3693 P26_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3694 P26_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3695 3696 /* P26.6 */ 3697 P26_6_GPIO = 0, /* GPIO controls 'out' */ 3698 P26_6_AMUXA = 4, /* Analog mux bus A */ 3699 P26_6_AMUXB = 5, /* Analog mux bus B */ 3700 P26_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3701 P26_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3702 3703 /* P26.7 */ 3704 P26_7_GPIO = 0, /* GPIO controls 'out' */ 3705 P26_7_AMUXA = 4, /* Analog mux bus A */ 3706 P26_7_AMUXB = 5, /* Analog mux bus B */ 3707 P26_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3708 P26_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3709 3710 /* P27.0 */ 3711 P27_0_GPIO = 0, /* GPIO controls 'out' */ 3712 P27_0_AMUXA = 4, /* Analog mux bus A */ 3713 P27_0_AMUXB = 5, /* Analog mux bus B */ 3714 P27_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3715 P27_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3716 3717 /* P27.1 */ 3718 P27_1_GPIO = 0, /* GPIO controls 'out' */ 3719 P27_1_AMUXA = 4, /* Analog mux bus A */ 3720 P27_1_AMUXB = 5, /* Analog mux bus B */ 3721 P27_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3722 P27_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3723 3724 /* P27.2 */ 3725 P27_2_GPIO = 0, /* GPIO controls 'out' */ 3726 P27_2_AMUXA = 4, /* Analog mux bus A */ 3727 P27_2_AMUXB = 5, /* Analog mux bus B */ 3728 P27_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3729 P27_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3730 3731 /* P27.3 */ 3732 P27_3_GPIO = 0, /* GPIO controls 'out' */ 3733 P27_3_AMUXA = 4, /* Analog mux bus A */ 3734 P27_3_AMUXB = 5, /* Analog mux bus B */ 3735 P27_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3736 P27_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3737 3738 /* P27.4 */ 3739 P27_4_GPIO = 0, /* GPIO controls 'out' */ 3740 P27_4_AMUXA = 4, /* Analog mux bus A */ 3741 P27_4_AMUXB = 5, /* Analog mux bus B */ 3742 P27_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3743 P27_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3744 3745 /* P27.5 */ 3746 P27_5_GPIO = 0, /* GPIO controls 'out' */ 3747 P27_5_AMUXA = 4, /* Analog mux bus A */ 3748 P27_5_AMUXB = 5, /* Analog mux bus B */ 3749 P27_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3750 P27_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3751 3752 /* P27.6 */ 3753 P27_6_GPIO = 0, /* GPIO controls 'out' */ 3754 P27_6_AMUXA = 4, /* Analog mux bus A */ 3755 P27_6_AMUXB = 5, /* Analog mux bus B */ 3756 P27_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3757 P27_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3758 3759 /* P27.7 */ 3760 P27_7_GPIO = 0, /* GPIO controls 'out' */ 3761 P27_7_AMUXA = 4, /* Analog mux bus A */ 3762 P27_7_AMUXB = 5, /* Analog mux bus B */ 3763 P27_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3764 P27_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3765 P27_7_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:0 */ 3766 3767 /* P28.0 */ 3768 P28_0_GPIO = 0, /* GPIO controls 'out' */ 3769 P28_0_AMUXA = 4, /* Analog mux bus A */ 3770 P28_0_AMUXB = 5, /* Analog mux bus B */ 3771 P28_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3772 P28_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3773 P28_0_SCB10_UART_RX = 17, /* Digital Active - scb[10].uart_rx:0 */ 3774 P28_0_SCB10_SPI_MISO = 19, /* Digital Active - scb[10].spi_miso:0 */ 3775 3776 /* P28.1 */ 3777 P28_1_GPIO = 0, /* GPIO controls 'out' */ 3778 P28_1_AMUXA = 4, /* Analog mux bus A */ 3779 P28_1_AMUXB = 5, /* Analog mux bus B */ 3780 P28_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3781 P28_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3782 P28_1_SCB10_UART_TX = 17, /* Digital Active - scb[10].uart_tx:0 */ 3783 P28_1_SCB10_I2C_SDA = 18, /* Digital Active - scb[10].i2c_sda:0 */ 3784 P28_1_SCB10_SPI_MOSI = 19, /* Digital Active - scb[10].spi_mosi:0 */ 3785 3786 /* P28.2 */ 3787 P28_2_GPIO = 0, /* GPIO controls 'out' */ 3788 P28_2_AMUXA = 4, /* Analog mux bus A */ 3789 P28_2_AMUXB = 5, /* Analog mux bus B */ 3790 P28_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3791 P28_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3792 P28_2_SCB10_UART_RTS = 17, /* Digital Active - scb[10].uart_rts:0 */ 3793 P28_2_SCB10_I2C_SCL = 18, /* Digital Active - scb[10].i2c_scl:0 */ 3794 P28_2_SCB10_SPI_CLK = 19, /* Digital Active - scb[10].spi_clk:0 */ 3795 3796 /* P28.3 */ 3797 P28_3_GPIO = 0, /* GPIO controls 'out' */ 3798 P28_3_AMUXA = 4, /* Analog mux bus A */ 3799 P28_3_AMUXB = 5, /* Analog mux bus B */ 3800 P28_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3801 P28_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3802 P28_3_SCB10_UART_CTS = 17, /* Digital Active - scb[10].uart_cts:0 */ 3803 P28_3_SCB10_SPI_SELECT0 = 19, /* Digital Active - scb[10].spi_select0:0 */ 3804 3805 /* P28.4 */ 3806 P28_4_GPIO = 0, /* GPIO controls 'out' */ 3807 P28_4_AMUXA = 4, /* Analog mux bus A */ 3808 P28_4_AMUXB = 5, /* Analog mux bus B */ 3809 P28_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3810 P28_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3811 P28_4_SCB10_SPI_SELECT1 = 19, /* Digital Active - scb[10].spi_select1:0 */ 3812 3813 /* P28.5 */ 3814 P28_5_GPIO = 0, /* GPIO controls 'out' */ 3815 P28_5_AMUXA = 4, /* Analog mux bus A */ 3816 P28_5_AMUXB = 5, /* Analog mux bus B */ 3817 P28_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3818 P28_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3819 P28_5_SCB10_SPI_SELECT2 = 19, /* Digital Active - scb[10].spi_select2:0 */ 3820 3821 /* P28.6 */ 3822 P28_6_GPIO = 0, /* GPIO controls 'out' */ 3823 P28_6_AMUXA = 4, /* Analog mux bus A */ 3824 P28_6_AMUXB = 5, /* Analog mux bus B */ 3825 P28_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3826 P28_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3827 P28_6_SCB10_SPI_SELECT3 = 19, /* Digital Active - scb[10].spi_select3:0 */ 3828 3829 /* P28.7 */ 3830 P28_7_GPIO = 0, /* GPIO controls 'out' */ 3831 P28_7_AMUXA = 4, /* Analog mux bus A */ 3832 P28_7_AMUXB = 5, /* Analog mux bus B */ 3833 P28_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3834 P28_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3835 3836 /* P29.0 */ 3837 P29_0_GPIO = 0, /* GPIO controls 'out' */ 3838 P29_0_AMUXA = 4, /* Analog mux bus A */ 3839 P29_0_AMUXB = 5, /* Analog mux bus B */ 3840 P29_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3841 P29_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3842 3843 /* P29.1 */ 3844 P29_1_GPIO = 0, /* GPIO controls 'out' */ 3845 P29_1_AMUXA = 4, /* Analog mux bus A */ 3846 P29_1_AMUXB = 5, /* Analog mux bus B */ 3847 P29_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3848 P29_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3849 3850 /* P29.2 */ 3851 P29_2_GPIO = 0, /* GPIO controls 'out' */ 3852 P29_2_AMUXA = 4, /* Analog mux bus A */ 3853 P29_2_AMUXB = 5, /* Analog mux bus B */ 3854 P29_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3855 P29_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3856 3857 /* P29.3 */ 3858 P29_3_GPIO = 0, /* GPIO controls 'out' */ 3859 P29_3_AMUXA = 4, /* Analog mux bus A */ 3860 P29_3_AMUXB = 5, /* Analog mux bus B */ 3861 P29_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3862 P29_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3863 3864 /* P29.4 */ 3865 P29_4_GPIO = 0, /* GPIO controls 'out' */ 3866 P29_4_AMUXA = 4, /* Analog mux bus A */ 3867 P29_4_AMUXB = 5, /* Analog mux bus B */ 3868 P29_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3869 P29_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3870 3871 /* P29.5 */ 3872 P29_5_GPIO = 0, /* GPIO controls 'out' */ 3873 P29_5_AMUXA = 4, /* Analog mux bus A */ 3874 P29_5_AMUXB = 5, /* Analog mux bus B */ 3875 P29_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3876 P29_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3877 3878 /* P29.6 */ 3879 P29_6_GPIO = 0, /* GPIO controls 'out' */ 3880 P29_6_AMUXA = 4, /* Analog mux bus A */ 3881 P29_6_AMUXB = 5, /* Analog mux bus B */ 3882 P29_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3883 P29_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3884 3885 /* P29.7 */ 3886 P29_7_GPIO = 0, /* GPIO controls 'out' */ 3887 P29_7_AMUXA = 4, /* Analog mux bus A */ 3888 P29_7_AMUXB = 5, /* Analog mux bus B */ 3889 P29_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3890 P29_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3891 3892 /* P30.0 */ 3893 P30_0_GPIO = 0, /* GPIO controls 'out' */ 3894 P30_0_AMUXA = 4, /* Analog mux bus A */ 3895 P30_0_AMUXB = 5, /* Analog mux bus B */ 3896 P30_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3897 P30_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3898 P30_0_SCB9_UART_RTS = 17, /* Digital Active - scb[9].uart_rts:1 */ 3899 P30_0_SCB9_SPI_CLK = 19, /* Digital Active - scb[9].spi_clk:1 */ 3900 3901 /* P30.1 */ 3902 P30_1_GPIO = 0, /* GPIO controls 'out' */ 3903 P30_1_AMUXA = 4, /* Analog mux bus A */ 3904 P30_1_AMUXB = 5, /* Analog mux bus B */ 3905 P30_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3906 P30_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3907 P30_1_SCB9_UART_CTS = 17, /* Digital Active - scb[9].uart_cts:1 */ 3908 P30_1_SCB9_SPI_SELECT0 = 19, /* Digital Active - scb[9].spi_select0:1 */ 3909 3910 /* P30.2 */ 3911 P30_2_GPIO = 0, /* GPIO controls 'out' */ 3912 P30_2_AMUXA = 4, /* Analog mux bus A */ 3913 P30_2_AMUXB = 5, /* Analog mux bus B */ 3914 P30_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3915 P30_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3916 P30_2_SCB9_SPI_SELECT1 = 19, /* Digital Active - scb[9].spi_select1:1 */ 3917 P30_2_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:2 */ 3918 3919 /* P30.3 */ 3920 P30_3_GPIO = 0, /* GPIO controls 'out' */ 3921 P30_3_AMUXA = 4, /* Analog mux bus A */ 3922 P30_3_AMUXB = 5, /* Analog mux bus B */ 3923 P30_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3924 P30_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3925 P30_3_SCB9_SPI_SELECT2 = 19, /* Digital Active - scb[9].spi_select2:1 */ 3926 P30_3_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:2 */ 3927 3928 /* P31.0 */ 3929 P31_0_GPIO = 0, /* GPIO controls 'out' */ 3930 P31_0_AMUXA = 4, /* Analog mux bus A */ 3931 P31_0_AMUXB = 5, /* Analog mux bus B */ 3932 P31_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3933 P31_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3934 3935 /* P31.1 */ 3936 P31_1_GPIO = 0, /* GPIO controls 'out' */ 3937 P31_1_AMUXA = 4, /* Analog mux bus A */ 3938 P31_1_AMUXB = 5, /* Analog mux bus B */ 3939 P31_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3940 P31_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3941 3942 /* P31.2 */ 3943 P31_2_GPIO = 0, /* GPIO controls 'out' */ 3944 P31_2_AMUXA = 4, /* Analog mux bus A */ 3945 P31_2_AMUXB = 5, /* Analog mux bus B */ 3946 P31_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3947 P31_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3948 3949 /* P32.0 */ 3950 P32_0_GPIO = 0, /* GPIO controls 'out' */ 3951 P32_0_AMUXA = 4, /* Analog mux bus A */ 3952 P32_0_AMUXB = 5, /* Analog mux bus B */ 3953 P32_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3954 P32_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3955 P32_0_SCB10_UART_RX = 17, /* Digital Active - scb[10].uart_rx:1 */ 3956 P32_0_SCB10_SPI_MISO = 19, /* Digital Active - scb[10].spi_miso:1 */ 3957 3958 /* P32.1 */ 3959 P32_1_GPIO = 0, /* GPIO controls 'out' */ 3960 P32_1_AMUXA = 4, /* Analog mux bus A */ 3961 P32_1_AMUXB = 5, /* Analog mux bus B */ 3962 P32_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3963 P32_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3964 P32_1_SCB10_UART_TX = 17, /* Digital Active - scb[10].uart_tx:1 */ 3965 P32_1_SCB10_I2C_SDA = 18, /* Digital Active - scb[10].i2c_sda:1 */ 3966 P32_1_SCB10_SPI_MOSI = 19, /* Digital Active - scb[10].spi_mosi:1 */ 3967 3968 /* P32.2 */ 3969 P32_2_GPIO = 0, /* GPIO controls 'out' */ 3970 P32_2_AMUXA = 4, /* Analog mux bus A */ 3971 P32_2_AMUXB = 5, /* Analog mux bus B */ 3972 P32_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3973 P32_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3974 P32_2_SCB10_UART_RTS = 17, /* Digital Active - scb[10].uart_rts:1 */ 3975 P32_2_SCB10_I2C_SCL = 18, /* Digital Active - scb[10].i2c_scl:1 */ 3976 P32_2_SCB10_SPI_CLK = 19, /* Digital Active - scb[10].spi_clk:1 */ 3977 3978 /* P32.3 */ 3979 P32_3_GPIO = 0, /* GPIO controls 'out' */ 3980 P32_3_AMUXA = 4, /* Analog mux bus A */ 3981 P32_3_AMUXB = 5, /* Analog mux bus B */ 3982 P32_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3983 P32_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3984 P32_3_SCB10_UART_CTS = 17, /* Digital Active - scb[10].uart_cts:1 */ 3985 P32_3_SCB10_SPI_SELECT0 = 19, /* Digital Active - scb[10].spi_select0:1 */ 3986 3987 /* P32.4 */ 3988 P32_4_GPIO = 0, /* GPIO controls 'out' */ 3989 P32_4_AMUXA = 4, /* Analog mux bus A */ 3990 P32_4_AMUXB = 5, /* Analog mux bus B */ 3991 P32_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3992 P32_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3993 P32_4_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:1 */ 3994 P32_4_SCB10_SPI_SELECT1 = 19, /* Digital Active - scb[10].spi_select1:1 */ 3995 3996 /* P32.5 */ 3997 P32_5_GPIO = 0, /* GPIO controls 'out' */ 3998 P32_5_AMUXA = 4, /* Analog mux bus A */ 3999 P32_5_AMUXB = 5, /* Analog mux bus B */ 4000 P32_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4001 P32_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4002 P32_5_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:1 */ 4003 P32_5_SCB10_SPI_SELECT2 = 19, /* Digital Active - scb[10].spi_select2:1 */ 4004 4005 /* P32.6 */ 4006 P32_6_GPIO = 0, /* GPIO controls 'out' */ 4007 P32_6_AMUXA = 4, /* Analog mux bus A */ 4008 P32_6_AMUXB = 5, /* Analog mux bus B */ 4009 P32_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4010 P32_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4011 P32_6_LIN0_LIN_EN10 = 18, /* Digital Active - lin[0].lin_en[10]:1 */ 4012 P32_6_SCB10_SPI_SELECT3 = 19, /* Digital Active - scb[10].spi_select3:1 */ 4013 4014 /* P32.7 */ 4015 P32_7_GPIO = 0, /* GPIO controls 'out' */ 4016 P32_7_AMUXA = 4, /* Analog mux bus A */ 4017 P32_7_AMUXB = 5, /* Analog mux bus B */ 4018 P32_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4019 P32_7_AMUXB_DSI = 7 /* Analog mux bus B, DSI control */ 4020 } en_hsiom_sel_t; 4021 4022 #endif /* _GPIO_XMC7100_272_BGA_H_ */ 4023 4024 4025 /* [] END OF FILE */ 4026
