1 /***************************************************************************//** 2 * \file gpio_xmc7100_176_teqfp.h 3 * 4 * \brief 5 * XMC7100 device GPIO header for 176-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_XMC7100_176_TEQFP_H_ 28 #define _GPIO_XMC7100_176_TEQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_TEQFP 44 #define CY_GPIO_PIN_COUNT 176u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_MAIN, 50 AMUXBUS_REGHC_ISENSE, 51 AMUXBUS_TEST, 52 AMUXBUS_TESTECT, 53 AMUXBUS_TESTSRSS, 54 }; 55 56 /* AMUX Splitter Controls */ 57 typedef enum 58 { 59 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_REGHC_ISENSE */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 0 (GPIO) */ 66 #define P0_0_PORT GPIO_PRT0 67 #define P0_0_PIN 0u 68 #define P0_0_NUM 0u 69 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 70 #define P0_1_PORT GPIO_PRT0 71 #define P0_1_PIN 1u 72 #define P0_1_NUM 1u 73 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 78 #define P0_3_PORT GPIO_PRT0 79 #define P0_3_PIN 3u 80 #define P0_3_NUM 3u 81 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 82 83 /* PORT 1 (GPIO) */ 84 #define P1_0_PORT GPIO_PRT1 85 #define P1_0_PIN 0u 86 #define P1_0_NUM 0u 87 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 88 #define P1_1_PORT GPIO_PRT1 89 #define P1_1_PIN 1u 90 #define P1_1_NUM 1u 91 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 92 #define P1_2_PORT GPIO_PRT1 93 #define P1_2_PIN 2u 94 #define P1_2_NUM 2u 95 #define P1_2_AMUXSEGMENT AMUXBUS_MAIN 96 #define P1_3_PORT GPIO_PRT1 97 #define P1_3_PIN 3u 98 #define P1_3_NUM 3u 99 #define P1_3_AMUXSEGMENT AMUXBUS_MAIN 100 101 /* PORT 2 (GPIO) */ 102 #define P2_0_PORT GPIO_PRT2 103 #define P2_0_PIN 0u 104 #define P2_0_NUM 0u 105 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 106 #define P2_1_PORT GPIO_PRT2 107 #define P2_1_PIN 1u 108 #define P2_1_NUM 1u 109 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 110 #define P2_2_PORT GPIO_PRT2 111 #define P2_2_PIN 2u 112 #define P2_2_NUM 2u 113 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 114 #define P2_3_PORT GPIO_PRT2 115 #define P2_3_PIN 3u 116 #define P2_3_NUM 3u 117 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 118 #define P2_4_PORT GPIO_PRT2 119 #define P2_4_PIN 4u 120 #define P2_4_NUM 4u 121 #define P2_4_AMUXSEGMENT AMUXBUS_MAIN 122 #define P2_5_PORT GPIO_PRT2 123 #define P2_5_PIN 5u 124 #define P2_5_NUM 5u 125 #define P2_5_AMUXSEGMENT AMUXBUS_MAIN 126 127 /* PORT 3 (GPIO) */ 128 #define P3_0_PORT GPIO_PRT3 129 #define P3_0_PIN 0u 130 #define P3_0_NUM 0u 131 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 132 #define P3_1_PORT GPIO_PRT3 133 #define P3_1_PIN 1u 134 #define P3_1_NUM 1u 135 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 136 #define P3_2_PORT GPIO_PRT3 137 #define P3_2_PIN 2u 138 #define P3_2_NUM 2u 139 #define P3_2_AMUXSEGMENT AMUXBUS_MAIN 140 #define P3_3_PORT GPIO_PRT3 141 #define P3_3_PIN 3u 142 #define P3_3_NUM 3u 143 #define P3_3_AMUXSEGMENT AMUXBUS_MAIN 144 #define P3_4_PORT GPIO_PRT3 145 #define P3_4_PIN 4u 146 #define P3_4_NUM 4u 147 #define P3_4_AMUXSEGMENT AMUXBUS_MAIN 148 #define P3_5_PORT GPIO_PRT3 149 #define P3_5_PIN 5u 150 #define P3_5_NUM 5u 151 #define P3_5_AMUXSEGMENT AMUXBUS_MAIN 152 153 /* PORT 4 (GPIO) */ 154 #define P4_0_PORT GPIO_PRT4 155 #define P4_0_PIN 0u 156 #define P4_0_NUM 0u 157 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 158 #define P4_1_PORT GPIO_PRT4 159 #define P4_1_PIN 1u 160 #define P4_1_NUM 1u 161 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 162 #define P4_2_PORT GPIO_PRT4 163 #define P4_2_PIN 2u 164 #define P4_2_NUM 2u 165 #define P4_2_AMUXSEGMENT AMUXBUS_MAIN 166 #define P4_3_PORT GPIO_PRT4 167 #define P4_3_PIN 3u 168 #define P4_3_NUM 3u 169 #define P4_3_AMUXSEGMENT AMUXBUS_MAIN 170 #define P4_4_PORT GPIO_PRT4 171 #define P4_4_PIN 4u 172 #define P4_4_NUM 4u 173 #define P4_4_AMUXSEGMENT AMUXBUS_MAIN 174 175 /* PORT 5 (GPIO) */ 176 #define P5_0_PORT GPIO_PRT5 177 #define P5_0_PIN 0u 178 #define P5_0_NUM 0u 179 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 180 #define P5_1_PORT GPIO_PRT5 181 #define P5_1_PIN 1u 182 #define P5_1_NUM 1u 183 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 184 #define P5_2_PORT GPIO_PRT5 185 #define P5_2_PIN 2u 186 #define P5_2_NUM 2u 187 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 188 #define P5_3_PORT GPIO_PRT5 189 #define P5_3_PIN 3u 190 #define P5_3_NUM 3u 191 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 192 #define P5_4_PORT GPIO_PRT5 193 #define P5_4_PIN 4u 194 #define P5_4_NUM 4u 195 #define P5_4_AMUXSEGMENT AMUXBUS_MAIN 196 #define P5_5_PORT GPIO_PRT5 197 #define P5_5_PIN 5u 198 #define P5_5_NUM 5u 199 #define P5_5_AMUXSEGMENT AMUXBUS_MAIN 200 201 /* PORT 6 (GPIO) */ 202 #define P6_0_PORT GPIO_PRT6 203 #define P6_0_PIN 0u 204 #define P6_0_NUM 0u 205 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 206 #define P6_1_PORT GPIO_PRT6 207 #define P6_1_PIN 1u 208 #define P6_1_NUM 1u 209 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 210 #define P6_2_PORT GPIO_PRT6 211 #define P6_2_PIN 2u 212 #define P6_2_NUM 2u 213 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 214 #define P6_3_PORT GPIO_PRT6 215 #define P6_3_PIN 3u 216 #define P6_3_NUM 3u 217 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 218 #define P6_4_PORT GPIO_PRT6 219 #define P6_4_PIN 4u 220 #define P6_4_NUM 4u 221 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 222 #define P6_5_PORT GPIO_PRT6 223 #define P6_5_PIN 5u 224 #define P6_5_NUM 5u 225 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 226 #define P6_6_PORT GPIO_PRT6 227 #define P6_6_PIN 6u 228 #define P6_6_NUM 6u 229 #define P6_6_AMUXSEGMENT AMUXBUS_MAIN 230 #define P6_7_PORT GPIO_PRT6 231 #define P6_7_PIN 7u 232 #define P6_7_NUM 7u 233 #define P6_7_AMUXSEGMENT AMUXBUS_MAIN 234 235 /* PORT 7 (GPIO) */ 236 #define P7_0_PORT GPIO_PRT7 237 #define P7_0_PIN 0u 238 #define P7_0_NUM 0u 239 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 240 #define P7_1_PORT GPIO_PRT7 241 #define P7_1_PIN 1u 242 #define P7_1_NUM 1u 243 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 244 #define P7_2_PORT GPIO_PRT7 245 #define P7_2_PIN 2u 246 #define P7_2_NUM 2u 247 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 248 #define P7_3_PORT GPIO_PRT7 249 #define P7_3_PIN 3u 250 #define P7_3_NUM 3u 251 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 252 #define P7_4_PORT GPIO_PRT7 253 #define P7_4_PIN 4u 254 #define P7_4_NUM 4u 255 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 256 #define P7_5_PORT GPIO_PRT7 257 #define P7_5_PIN 5u 258 #define P7_5_NUM 5u 259 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 260 #define P7_6_PORT GPIO_PRT7 261 #define P7_6_PIN 6u 262 #define P7_6_NUM 6u 263 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 264 #define P7_7_PORT GPIO_PRT7 265 #define P7_7_PIN 7u 266 #define P7_7_NUM 7u 267 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 268 269 /* PORT 8 (GPIO) */ 270 #define P8_0_PORT GPIO_PRT8 271 #define P8_0_PIN 0u 272 #define P8_0_NUM 0u 273 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 274 #define P8_1_PORT GPIO_PRT8 275 #define P8_1_PIN 1u 276 #define P8_1_NUM 1u 277 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 278 #define P8_2_PORT GPIO_PRT8 279 #define P8_2_PIN 2u 280 #define P8_2_NUM 2u 281 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 282 #define P8_3_PORT GPIO_PRT8 283 #define P8_3_PIN 3u 284 #define P8_3_NUM 3u 285 #define P8_3_AMUXSEGMENT AMUXBUS_MAIN 286 #define P8_4_PORT GPIO_PRT8 287 #define P8_4_PIN 4u 288 #define P8_4_NUM 4u 289 #define P8_4_AMUXSEGMENT AMUXBUS_MAIN 290 291 /* PORT 9 (GPIO) */ 292 #define P9_0_PORT GPIO_PRT9 293 #define P9_0_PIN 0u 294 #define P9_0_NUM 0u 295 #define P9_0_AMUXSEGMENT AMUXBUS_MAIN 296 #define P9_1_PORT GPIO_PRT9 297 #define P9_1_PIN 1u 298 #define P9_1_NUM 1u 299 #define P9_1_AMUXSEGMENT AMUXBUS_MAIN 300 #define P9_2_PORT GPIO_PRT9 301 #define P9_2_PIN 2u 302 #define P9_2_NUM 2u 303 #define P9_2_AMUXSEGMENT AMUXBUS_MAIN 304 #define P9_3_PORT GPIO_PRT9 305 #define P9_3_PIN 3u 306 #define P9_3_NUM 3u 307 #define P9_3_AMUXSEGMENT AMUXBUS_MAIN 308 309 /* PORT 10 (GPIO) */ 310 #define P10_0_PORT GPIO_PRT10 311 #define P10_0_PIN 0u 312 #define P10_0_NUM 0u 313 #define P10_0_AMUXSEGMENT AMUXBUS_MAIN 314 #define P10_1_PORT GPIO_PRT10 315 #define P10_1_PIN 1u 316 #define P10_1_NUM 1u 317 #define P10_1_AMUXSEGMENT AMUXBUS_MAIN 318 #define P10_2_PORT GPIO_PRT10 319 #define P10_2_PIN 2u 320 #define P10_2_NUM 2u 321 #define P10_2_AMUXSEGMENT AMUXBUS_MAIN 322 #define P10_3_PORT GPIO_PRT10 323 #define P10_3_PIN 3u 324 #define P10_3_NUM 3u 325 #define P10_3_AMUXSEGMENT AMUXBUS_MAIN 326 #define P10_4_PORT GPIO_PRT10 327 #define P10_4_PIN 4u 328 #define P10_4_NUM 4u 329 #define P10_4_AMUXSEGMENT AMUXBUS_MAIN 330 #define P10_5_PORT GPIO_PRT10 331 #define P10_5_PIN 5u 332 #define P10_5_NUM 5u 333 #define P10_5_AMUXSEGMENT AMUXBUS_MAIN 334 #define P10_6_PORT GPIO_PRT10 335 #define P10_6_PIN 6u 336 #define P10_6_NUM 6u 337 #define P10_6_AMUXSEGMENT AMUXBUS_MAIN 338 #define P10_7_PORT GPIO_PRT10 339 #define P10_7_PIN 7u 340 #define P10_7_NUM 7u 341 #define P10_7_AMUXSEGMENT AMUXBUS_MAIN 342 343 /* PORT 11 (GPIO) */ 344 #define P11_0_PORT GPIO_PRT11 345 #define P11_0_PIN 0u 346 #define P11_0_NUM 0u 347 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 348 #define P11_1_PORT GPIO_PRT11 349 #define P11_1_PIN 1u 350 #define P11_1_NUM 1u 351 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 352 #define P11_2_PORT GPIO_PRT11 353 #define P11_2_PIN 2u 354 #define P11_2_NUM 2u 355 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 356 357 /* PORT 12 (GPIO) */ 358 #define P12_0_PORT GPIO_PRT12 359 #define P12_0_PIN 0u 360 #define P12_0_NUM 0u 361 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 362 #define P12_1_PORT GPIO_PRT12 363 #define P12_1_PIN 1u 364 #define P12_1_NUM 1u 365 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 366 #define P12_2_PORT GPIO_PRT12 367 #define P12_2_PIN 2u 368 #define P12_2_NUM 2u 369 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 370 #define P12_3_PORT GPIO_PRT12 371 #define P12_3_PIN 3u 372 #define P12_3_NUM 3u 373 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 374 #define P12_4_PORT GPIO_PRT12 375 #define P12_4_PIN 4u 376 #define P12_4_NUM 4u 377 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 378 #define P12_5_PORT GPIO_PRT12 379 #define P12_5_PIN 5u 380 #define P12_5_NUM 5u 381 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 382 #define P12_6_PORT GPIO_PRT12 383 #define P12_6_PIN 6u 384 #define P12_6_NUM 6u 385 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 386 #define P12_7_PORT GPIO_PRT12 387 #define P12_7_PIN 7u 388 #define P12_7_NUM 7u 389 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 390 391 /* PORT 13 (GPIO) */ 392 #define P13_0_PORT GPIO_PRT13 393 #define P13_0_PIN 0u 394 #define P13_0_NUM 0u 395 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 396 #define P13_1_PORT GPIO_PRT13 397 #define P13_1_PIN 1u 398 #define P13_1_NUM 1u 399 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 400 #define P13_2_PORT GPIO_PRT13 401 #define P13_2_PIN 2u 402 #define P13_2_NUM 2u 403 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 404 #define P13_3_PORT GPIO_PRT13 405 #define P13_3_PIN 3u 406 #define P13_3_NUM 3u 407 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 408 #define P13_4_PORT GPIO_PRT13 409 #define P13_4_PIN 4u 410 #define P13_4_NUM 4u 411 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 412 #define P13_5_PORT GPIO_PRT13 413 #define P13_5_PIN 5u 414 #define P13_5_NUM 5u 415 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 416 #define P13_6_PORT GPIO_PRT13 417 #define P13_6_PIN 6u 418 #define P13_6_NUM 6u 419 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 420 #define P13_7_PORT GPIO_PRT13 421 #define P13_7_PIN 7u 422 #define P13_7_NUM 7u 423 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 424 425 /* PORT 14 (GPIO) */ 426 #define P14_0_PORT GPIO_PRT14 427 #define P14_0_PIN 0u 428 #define P14_0_NUM 0u 429 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 430 #define P14_1_PORT GPIO_PRT14 431 #define P14_1_PIN 1u 432 #define P14_1_NUM 1u 433 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 434 #define P14_2_PORT GPIO_PRT14 435 #define P14_2_PIN 2u 436 #define P14_2_NUM 2u 437 #define P14_2_AMUXSEGMENT AMUXBUS_MAIN 438 #define P14_3_PORT GPIO_PRT14 439 #define P14_3_PIN 3u 440 #define P14_3_NUM 3u 441 #define P14_3_AMUXSEGMENT AMUXBUS_MAIN 442 #define P14_4_PORT GPIO_PRT14 443 #define P14_4_PIN 4u 444 #define P14_4_NUM 4u 445 #define P14_4_AMUXSEGMENT AMUXBUS_MAIN 446 #define P14_5_PORT GPIO_PRT14 447 #define P14_5_PIN 5u 448 #define P14_5_NUM 5u 449 #define P14_5_AMUXSEGMENT AMUXBUS_MAIN 450 #define P14_6_PORT GPIO_PRT14 451 #define P14_6_PIN 6u 452 #define P14_6_NUM 6u 453 #define P14_6_AMUXSEGMENT AMUXBUS_MAIN 454 #define P14_7_PORT GPIO_PRT14 455 #define P14_7_PIN 7u 456 #define P14_7_NUM 7u 457 #define P14_7_AMUXSEGMENT AMUXBUS_MAIN 458 459 /* PORT 15 (GPIO) */ 460 #define P15_0_PORT GPIO_PRT15 461 #define P15_0_PIN 0u 462 #define P15_0_NUM 0u 463 #define P15_0_AMUXSEGMENT AMUXBUS_MAIN 464 #define P15_1_PORT GPIO_PRT15 465 #define P15_1_PIN 1u 466 #define P15_1_NUM 1u 467 #define P15_1_AMUXSEGMENT AMUXBUS_MAIN 468 #define P15_2_PORT GPIO_PRT15 469 #define P15_2_PIN 2u 470 #define P15_2_NUM 2u 471 #define P15_2_AMUXSEGMENT AMUXBUS_MAIN 472 #define P15_3_PORT GPIO_PRT15 473 #define P15_3_PIN 3u 474 #define P15_3_NUM 3u 475 #define P15_3_AMUXSEGMENT AMUXBUS_MAIN 476 477 /* PORT 16 (GPIO) */ 478 #define P16_3_PORT GPIO_PRT16 479 #define P16_3_PIN 3u 480 #define P16_3_NUM 3u 481 #define P16_3_AMUXSEGMENT AMUXBUS_MAIN 482 483 /* PORT 17 (GPIO) */ 484 #define P17_0_PORT GPIO_PRT17 485 #define P17_0_PIN 0u 486 #define P17_0_NUM 0u 487 #define P17_0_AMUXSEGMENT AMUXBUS_MAIN 488 #define P17_1_PORT GPIO_PRT17 489 #define P17_1_PIN 1u 490 #define P17_1_NUM 1u 491 #define P17_1_AMUXSEGMENT AMUXBUS_MAIN 492 #define P17_2_PORT GPIO_PRT17 493 #define P17_2_PIN 2u 494 #define P17_2_NUM 2u 495 #define P17_2_AMUXSEGMENT AMUXBUS_MAIN 496 #define P17_3_PORT GPIO_PRT17 497 #define P17_3_PIN 3u 498 #define P17_3_NUM 3u 499 #define P17_3_AMUXSEGMENT AMUXBUS_MAIN 500 #define P17_4_PORT GPIO_PRT17 501 #define P17_4_PIN 4u 502 #define P17_4_NUM 4u 503 #define P17_4_AMUXSEGMENT AMUXBUS_MAIN 504 #define P17_5_PORT GPIO_PRT17 505 #define P17_5_PIN 5u 506 #define P17_5_NUM 5u 507 #define P17_5_AMUXSEGMENT AMUXBUS_MAIN 508 #define P17_6_PORT GPIO_PRT17 509 #define P17_6_PIN 6u 510 #define P17_6_NUM 6u 511 #define P17_6_AMUXSEGMENT AMUXBUS_MAIN 512 #define P17_7_PORT GPIO_PRT17 513 #define P17_7_PIN 7u 514 #define P17_7_NUM 7u 515 #define P17_7_AMUXSEGMENT AMUXBUS_MAIN 516 517 /* PORT 18 (GPIO) */ 518 #define P18_0_PORT GPIO_PRT18 519 #define P18_0_PIN 0u 520 #define P18_0_NUM 0u 521 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 522 #define P18_1_PORT GPIO_PRT18 523 #define P18_1_PIN 1u 524 #define P18_1_NUM 1u 525 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 526 #define P18_2_PORT GPIO_PRT18 527 #define P18_2_PIN 2u 528 #define P18_2_NUM 2u 529 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 530 #define P18_3_PORT GPIO_PRT18 531 #define P18_3_PIN 3u 532 #define P18_3_NUM 3u 533 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 534 #define P18_4_PORT GPIO_PRT18 535 #define P18_4_PIN 4u 536 #define P18_4_NUM 4u 537 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 538 #define P18_5_PORT GPIO_PRT18 539 #define P18_5_PIN 5u 540 #define P18_5_NUM 5u 541 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 542 #define P18_6_PORT GPIO_PRT18 543 #define P18_6_PIN 6u 544 #define P18_6_NUM 6u 545 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 546 #define P18_7_PORT GPIO_PRT18 547 #define P18_7_PIN 7u 548 #define P18_7_NUM 7u 549 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 550 551 /* PORT 19 (GPIO) */ 552 #define P19_0_PORT GPIO_PRT19 553 #define P19_0_PIN 0u 554 #define P19_0_NUM 0u 555 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 556 #define P19_1_PORT GPIO_PRT19 557 #define P19_1_PIN 1u 558 #define P19_1_NUM 1u 559 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 560 #define P19_2_PORT GPIO_PRT19 561 #define P19_2_PIN 2u 562 #define P19_2_NUM 2u 563 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 564 #define P19_3_PORT GPIO_PRT19 565 #define P19_3_PIN 3u 566 #define P19_3_NUM 3u 567 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 568 #define P19_4_PORT GPIO_PRT19 569 #define P19_4_PIN 4u 570 #define P19_4_NUM 4u 571 #define P19_4_AMUXSEGMENT AMUXBUS_MAIN 572 573 /* PORT 20 (GPIO) */ 574 #define P20_0_PORT GPIO_PRT20 575 #define P20_0_PIN 0u 576 #define P20_0_NUM 0u 577 #define P20_0_AMUXSEGMENT AMUXBUS_MAIN 578 #define P20_1_PORT GPIO_PRT20 579 #define P20_1_PIN 1u 580 #define P20_1_NUM 1u 581 #define P20_1_AMUXSEGMENT AMUXBUS_MAIN 582 #define P20_2_PORT GPIO_PRT20 583 #define P20_2_PIN 2u 584 #define P20_2_NUM 2u 585 #define P20_2_AMUXSEGMENT AMUXBUS_MAIN 586 #define P20_3_PORT GPIO_PRT20 587 #define P20_3_PIN 3u 588 #define P20_3_NUM 3u 589 #define P20_3_AMUXSEGMENT AMUXBUS_MAIN 590 #define P20_4_PORT GPIO_PRT20 591 #define P20_4_PIN 4u 592 #define P20_4_NUM 4u 593 #define P20_4_AMUXSEGMENT AMUXBUS_MAIN 594 #define P20_5_PORT GPIO_PRT20 595 #define P20_5_PIN 5u 596 #define P20_5_NUM 5u 597 #define P20_5_AMUXSEGMENT AMUXBUS_MAIN 598 #define P20_6_PORT GPIO_PRT20 599 #define P20_6_PIN 6u 600 #define P20_6_NUM 6u 601 #define P20_6_AMUXSEGMENT AMUXBUS_MAIN 602 #define P20_7_PORT GPIO_PRT20 603 #define P20_7_PIN 7u 604 #define P20_7_NUM 7u 605 #define P20_7_AMUXSEGMENT AMUXBUS_MAIN 606 607 /* PORT 21 (GPIO) */ 608 #define P21_0_PORT GPIO_PRT21 609 #define P21_0_PIN 0u 610 #define P21_0_NUM 0u 611 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 612 #define P21_1_PORT GPIO_PRT21 613 #define P21_1_PIN 1u 614 #define P21_1_NUM 1u 615 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 616 #define P21_2_PORT GPIO_PRT21 617 #define P21_2_PIN 2u 618 #define P21_2_NUM 2u 619 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 620 #define P21_3_PORT GPIO_PRT21 621 #define P21_3_PIN 3u 622 #define P21_3_NUM 3u 623 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 624 #define P21_4_PORT GPIO_PRT21 625 #define P21_4_PIN 4u 626 #define P21_4_NUM 4u 627 #define P21_4_AMUXSEGMENT AMUXBUS_MAIN 628 #define P21_5_PORT GPIO_PRT21 629 #define P21_5_PIN 5u 630 #define P21_5_NUM 5u 631 #define P21_5_AMUXSEGMENT AMUXBUS_MAIN 632 #define P21_6_PORT GPIO_PRT21 633 #define P21_6_PIN 6u 634 #define P21_6_NUM 6u 635 #define P21_6_AMUXSEGMENT AMUXBUS_MAIN 636 #define P21_7_PORT GPIO_PRT21 637 #define P21_7_PIN 7u 638 #define P21_7_NUM 7u 639 #define P21_7_AMUXSEGMENT AMUXBUS_MAIN 640 641 /* PORT 22 (GPIO) */ 642 #define P22_1_PORT GPIO_PRT22 643 #define P22_1_PIN 1u 644 #define P22_1_NUM 1u 645 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 646 #define P22_2_PORT GPIO_PRT22 647 #define P22_2_PIN 2u 648 #define P22_2_NUM 2u 649 #define P22_2_AMUXSEGMENT AMUXBUS_MAIN 650 #define P22_3_PORT GPIO_PRT22 651 #define P22_3_PIN 3u 652 #define P22_3_NUM 3u 653 #define P22_3_AMUXSEGMENT AMUXBUS_MAIN 654 #define P22_4_PORT GPIO_PRT22 655 #define P22_4_PIN 4u 656 #define P22_4_NUM 4u 657 #define P22_4_AMUXSEGMENT AMUXBUS_MAIN 658 #define P22_5_PORT GPIO_PRT22 659 #define P22_5_PIN 5u 660 #define P22_5_NUM 5u 661 #define P22_5_AMUXSEGMENT AMUXBUS_MAIN 662 #define P22_6_PORT GPIO_PRT22 663 #define P22_6_PIN 6u 664 #define P22_6_NUM 6u 665 #define P22_6_AMUXSEGMENT AMUXBUS_MAIN 666 #define P22_7_PORT GPIO_PRT22 667 #define P22_7_PIN 7u 668 #define P22_7_NUM 7u 669 #define P22_7_AMUXSEGMENT AMUXBUS_MAIN 670 671 /* PORT 23 (GPIO) */ 672 #define P23_0_PORT GPIO_PRT23 673 #define P23_0_PIN 0u 674 #define P23_0_NUM 0u 675 #define P23_0_AMUXSEGMENT AMUXBUS_MAIN 676 #define P23_1_PORT GPIO_PRT23 677 #define P23_1_PIN 1u 678 #define P23_1_NUM 1u 679 #define P23_1_AMUXSEGMENT AMUXBUS_MAIN 680 #define P23_2_PORT GPIO_PRT23 681 #define P23_2_PIN 2u 682 #define P23_2_NUM 2u 683 #define P23_2_AMUXSEGMENT AMUXBUS_MAIN 684 #define P23_3_PORT GPIO_PRT23 685 #define P23_3_PIN 3u 686 #define P23_3_NUM 3u 687 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 688 #define P23_4_PORT GPIO_PRT23 689 #define P23_4_PIN 4u 690 #define P23_4_NUM 4u 691 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 692 #define P23_5_PORT GPIO_PRT23 693 #define P23_5_PIN 5u 694 #define P23_5_NUM 5u 695 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 696 #define P23_6_PORT GPIO_PRT23 697 #define P23_6_PIN 6u 698 #define P23_6_NUM 6u 699 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 700 #define P23_7_PORT GPIO_PRT23 701 #define P23_7_PIN 7u 702 #define P23_7_NUM 7u 703 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 704 705 /* Analog Connections */ 706 #define PASS0_I_TEMP_KELVIN_PORT 21u 707 #define PASS0_I_TEMP_KELVIN_PIN 2u 708 #define PASS0_SARMUX_MOTOR0_PORT 11u 709 #define PASS0_SARMUX_MOTOR0_PIN 0u 710 #define PASS0_SARMUX_MOTOR1_PORT 11u 711 #define PASS0_SARMUX_MOTOR1_PIN 1u 712 #define PASS0_SARMUX_MOTOR2_PORT 11u 713 #define PASS0_SARMUX_MOTOR2_PIN 2u 714 #define PASS0_SARMUX_PADS0_PORT 6u 715 #define PASS0_SARMUX_PADS0_PIN 0u 716 #define PASS0_SARMUX_PADS1_PORT 6u 717 #define PASS0_SARMUX_PADS1_PIN 1u 718 #define PASS0_SARMUX_PADS16_PORT 7u 719 #define PASS0_SARMUX_PADS16_PIN 0u 720 #define PASS0_SARMUX_PADS17_PORT 7u 721 #define PASS0_SARMUX_PADS17_PIN 1u 722 #define PASS0_SARMUX_PADS18_PORT 7u 723 #define PASS0_SARMUX_PADS18_PIN 2u 724 #define PASS0_SARMUX_PADS19_PORT 7u 725 #define PASS0_SARMUX_PADS19_PIN 3u 726 #define PASS0_SARMUX_PADS2_PORT 6u 727 #define PASS0_SARMUX_PADS2_PIN 2u 728 #define PASS0_SARMUX_PADS20_PORT 7u 729 #define PASS0_SARMUX_PADS20_PIN 4u 730 #define PASS0_SARMUX_PADS21_PORT 7u 731 #define PASS0_SARMUX_PADS21_PIN 5u 732 #define PASS0_SARMUX_PADS22_PORT 7u 733 #define PASS0_SARMUX_PADS22_PIN 6u 734 #define PASS0_SARMUX_PADS23_PORT 7u 735 #define PASS0_SARMUX_PADS23_PIN 7u 736 #define PASS0_SARMUX_PADS24_PORT 8u 737 #define PASS0_SARMUX_PADS24_PIN 1u 738 #define PASS0_SARMUX_PADS25_PORT 8u 739 #define PASS0_SARMUX_PADS25_PIN 2u 740 #define PASS0_SARMUX_PADS26_PORT 8u 741 #define PASS0_SARMUX_PADS26_PIN 3u 742 #define PASS0_SARMUX_PADS27_PORT 8u 743 #define PASS0_SARMUX_PADS27_PIN 4u 744 #define PASS0_SARMUX_PADS28_PORT 9u 745 #define PASS0_SARMUX_PADS28_PIN 0u 746 #define PASS0_SARMUX_PADS29_PORT 9u 747 #define PASS0_SARMUX_PADS29_PIN 1u 748 #define PASS0_SARMUX_PADS3_PORT 6u 749 #define PASS0_SARMUX_PADS3_PIN 3u 750 #define PASS0_SARMUX_PADS30_PORT 9u 751 #define PASS0_SARMUX_PADS30_PIN 2u 752 #define PASS0_SARMUX_PADS31_PORT 9u 753 #define PASS0_SARMUX_PADS31_PIN 3u 754 #define PASS0_SARMUX_PADS32_PORT 10u 755 #define PASS0_SARMUX_PADS32_PIN 4u 756 #define PASS0_SARMUX_PADS33_PORT 10u 757 #define PASS0_SARMUX_PADS33_PIN 5u 758 #define PASS0_SARMUX_PADS34_PORT 10u 759 #define PASS0_SARMUX_PADS34_PIN 6u 760 #define PASS0_SARMUX_PADS35_PORT 10u 761 #define PASS0_SARMUX_PADS35_PIN 7u 762 #define PASS0_SARMUX_PADS36_PORT 12u 763 #define PASS0_SARMUX_PADS36_PIN 0u 764 #define PASS0_SARMUX_PADS37_PORT 12u 765 #define PASS0_SARMUX_PADS37_PIN 1u 766 #define PASS0_SARMUX_PADS38_PORT 12u 767 #define PASS0_SARMUX_PADS38_PIN 2u 768 #define PASS0_SARMUX_PADS39_PORT 12u 769 #define PASS0_SARMUX_PADS39_PIN 3u 770 #define PASS0_SARMUX_PADS4_PORT 6u 771 #define PASS0_SARMUX_PADS4_PIN 4u 772 #define PASS0_SARMUX_PADS40_PORT 12u 773 #define PASS0_SARMUX_PADS40_PIN 4u 774 #define PASS0_SARMUX_PADS41_PORT 12u 775 #define PASS0_SARMUX_PADS41_PIN 5u 776 #define PASS0_SARMUX_PADS42_PORT 12u 777 #define PASS0_SARMUX_PADS42_PIN 6u 778 #define PASS0_SARMUX_PADS43_PORT 12u 779 #define PASS0_SARMUX_PADS43_PIN 7u 780 #define PASS0_SARMUX_PADS44_PORT 13u 781 #define PASS0_SARMUX_PADS44_PIN 0u 782 #define PASS0_SARMUX_PADS45_PORT 13u 783 #define PASS0_SARMUX_PADS45_PIN 1u 784 #define PASS0_SARMUX_PADS46_PORT 13u 785 #define PASS0_SARMUX_PADS46_PIN 2u 786 #define PASS0_SARMUX_PADS47_PORT 13u 787 #define PASS0_SARMUX_PADS47_PIN 3u 788 #define PASS0_SARMUX_PADS48_PORT 13u 789 #define PASS0_SARMUX_PADS48_PIN 4u 790 #define PASS0_SARMUX_PADS49_PORT 13u 791 #define PASS0_SARMUX_PADS49_PIN 5u 792 #define PASS0_SARMUX_PADS5_PORT 6u 793 #define PASS0_SARMUX_PADS5_PIN 5u 794 #define PASS0_SARMUX_PADS50_PORT 13u 795 #define PASS0_SARMUX_PADS50_PIN 6u 796 #define PASS0_SARMUX_PADS51_PORT 13u 797 #define PASS0_SARMUX_PADS51_PIN 7u 798 #define PASS0_SARMUX_PADS52_PORT 14u 799 #define PASS0_SARMUX_PADS52_PIN 0u 800 #define PASS0_SARMUX_PADS53_PORT 14u 801 #define PASS0_SARMUX_PADS53_PIN 1u 802 #define PASS0_SARMUX_PADS54_PORT 14u 803 #define PASS0_SARMUX_PADS54_PIN 2u 804 #define PASS0_SARMUX_PADS55_PORT 14u 805 #define PASS0_SARMUX_PADS55_PIN 3u 806 #define PASS0_SARMUX_PADS56_PORT 14u 807 #define PASS0_SARMUX_PADS56_PIN 4u 808 #define PASS0_SARMUX_PADS57_PORT 14u 809 #define PASS0_SARMUX_PADS57_PIN 5u 810 #define PASS0_SARMUX_PADS58_PORT 14u 811 #define PASS0_SARMUX_PADS58_PIN 6u 812 #define PASS0_SARMUX_PADS59_PORT 14u 813 #define PASS0_SARMUX_PADS59_PIN 7u 814 #define PASS0_SARMUX_PADS6_PORT 6u 815 #define PASS0_SARMUX_PADS6_PIN 6u 816 #define PASS0_SARMUX_PADS60_PORT 15u 817 #define PASS0_SARMUX_PADS60_PIN 0u 818 #define PASS0_SARMUX_PADS61_PORT 15u 819 #define PASS0_SARMUX_PADS61_PIN 1u 820 #define PASS0_SARMUX_PADS62_PORT 15u 821 #define PASS0_SARMUX_PADS62_PIN 2u 822 #define PASS0_SARMUX_PADS63_PORT 15u 823 #define PASS0_SARMUX_PADS63_PIN 3u 824 #define PASS0_SARMUX_PADS64_PORT 18u 825 #define PASS0_SARMUX_PADS64_PIN 0u 826 #define PASS0_SARMUX_PADS65_PORT 18u 827 #define PASS0_SARMUX_PADS65_PIN 1u 828 #define PASS0_SARMUX_PADS66_PORT 18u 829 #define PASS0_SARMUX_PADS66_PIN 2u 830 #define PASS0_SARMUX_PADS67_PORT 18u 831 #define PASS0_SARMUX_PADS67_PIN 3u 832 #define PASS0_SARMUX_PADS68_PORT 18u 833 #define PASS0_SARMUX_PADS68_PIN 4u 834 #define PASS0_SARMUX_PADS69_PORT 18u 835 #define PASS0_SARMUX_PADS69_PIN 5u 836 #define PASS0_SARMUX_PADS7_PORT 6u 837 #define PASS0_SARMUX_PADS7_PIN 7u 838 #define PASS0_SARMUX_PADS70_PORT 18u 839 #define PASS0_SARMUX_PADS70_PIN 6u 840 #define PASS0_SARMUX_PADS71_PORT 18u 841 #define PASS0_SARMUX_PADS71_PIN 7u 842 #define PASS0_VB_TEMP_KELVIN_PORT 10u 843 #define PASS0_VB_TEMP_KELVIN_PIN 4u 844 #define PASS0_VE_TEMP_KELVIN_PORT 23u 845 #define PASS0_VE_TEMP_KELVIN_PIN 4u 846 #define SRSS_ADFT_PIN0_PORT 23u 847 #define SRSS_ADFT_PIN0_PIN 4u 848 #define SRSS_ADFT_PIN1_PORT 23u 849 #define SRSS_ADFT_PIN1_PIN 3u 850 #define SRSS_ADFT_POR_PAD_HV_PORT 21u 851 #define SRSS_ADFT_POR_PAD_HV_PIN 4u 852 #define SRSS_ECO_IN_PORT 21u 853 #define SRSS_ECO_IN_PIN 2u 854 #define SRSS_ECO_OUT_PORT 21u 855 #define SRSS_ECO_OUT_PIN 3u 856 #define SRSS_REGHC_ISENSE_INM_PORT 22u 857 #define SRSS_REGHC_ISENSE_INM_PIN 2u 858 #define SRSS_REGHC_ISENSE_INP_PORT 22u 859 #define SRSS_REGHC_ISENSE_INP_PIN 1u 860 #define SRSS_REGHC_RST_VOUT_PORT 22u 861 #define SRSS_REGHC_RST_VOUT_PIN 3u 862 #define SRSS_VEXT_REF_REG_PORT 21u 863 #define SRSS_VEXT_REF_REG_PIN 3u 864 #define SRSS_WCO_IN_PORT 21u 865 #define SRSS_WCO_IN_PIN 0u 866 #define SRSS_WCO_OUT_PORT 21u 867 #define SRSS_WCO_OUT_PIN 1u 868 869 /* HSIOM Connections */ 870 typedef enum 871 { 872 /* Generic HSIOM connections */ 873 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 874 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 875 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 876 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 877 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 878 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 879 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 880 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 881 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 882 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 883 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 884 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 885 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 886 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 887 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 888 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 889 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 890 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 891 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 892 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 893 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 894 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 895 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 896 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 897 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 898 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 899 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 900 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 901 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 902 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 903 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 904 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 905 906 /* P0.0 */ 907 P0_0_GPIO = 0, /* GPIO controls 'out' */ 908 P0_0_AMUXA = 4, /* Analog mux bus A */ 909 P0_0_AMUXB = 5, /* Analog mux bus B */ 910 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 911 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 912 P0_0_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:1 */ 913 P0_0_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ 914 P0_0_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:1 */ 915 P0_0_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:1 */ 916 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 917 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 918 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 919 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 920 921 /* P0.1 */ 922 P0_1_GPIO = 0, /* GPIO controls 'out' */ 923 P0_1_AMUXA = 4, /* Analog mux bus A */ 924 P0_1_AMUXB = 5, /* Analog mux bus B */ 925 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 926 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 927 P0_1_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:1 */ 928 P0_1_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:1 */ 929 P0_1_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:1 */ 930 P0_1_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:1 */ 931 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 932 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 933 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 934 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 935 936 /* P0.2 */ 937 P0_2_GPIO = 0, /* GPIO controls 'out' */ 938 P0_2_AMUXA = 4, /* Analog mux bus A */ 939 P0_2_AMUXB = 5, /* Analog mux bus B */ 940 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 941 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 942 P0_2_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:1 */ 943 P0_2_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:1 */ 944 P0_2_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:1 */ 945 P0_2_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:1 */ 946 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 947 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 948 P0_2_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:2 */ 949 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 950 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 951 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 952 953 /* P0.3 */ 954 P0_3_GPIO = 0, /* GPIO controls 'out' */ 955 P0_3_AMUXA = 4, /* Analog mux bus A */ 956 P0_3_AMUXB = 5, /* Analog mux bus B */ 957 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 958 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 959 P0_3_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:1 */ 960 P0_3_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:1 */ 961 P0_3_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:1 */ 962 P0_3_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:1 */ 963 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 964 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 965 P0_3_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:2 */ 966 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 967 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 968 969 /* P1.0 */ 970 P1_0_GPIO = 0, /* GPIO controls 'out' */ 971 P1_0_AMUXA = 4, /* Analog mux bus A */ 972 P1_0_AMUXB = 5, /* Analog mux bus B */ 973 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 974 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 975 P1_0_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:1 */ 976 P1_0_TCPWM0_LINE_COMPL13 = 9, /* Digital Active - tcpwm[0].line_compl[13]:1 */ 977 P1_0_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:1 */ 978 P1_0_TCPWM0_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[40]:1 */ 979 P1_0_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 980 P1_0_TCPWM0_LINE516 = 16, /* Digital Active - tcpwm[0].line[516]:0 */ 981 P1_0_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:2 */ 982 P1_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 983 984 /* P1.1 */ 985 P1_1_GPIO = 0, /* GPIO controls 'out' */ 986 P1_1_AMUXA = 4, /* Analog mux bus A */ 987 P1_1_AMUXB = 5, /* Analog mux bus B */ 988 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 989 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 990 P1_1_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:1 */ 991 P1_1_TCPWM0_LINE_COMPL12 = 9, /* Digital Active - tcpwm[0].line_compl[12]:1 */ 992 P1_1_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:1 */ 993 P1_1_TCPWM0_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:1 */ 994 P1_1_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 995 P1_1_TCPWM0_LINE517 = 16, /* Digital Active - tcpwm[0].line[517]:0 */ 996 P1_1_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:2 */ 997 P1_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 998 999 /* P1.2 */ 1000 P1_2_GPIO = 0, /* GPIO controls 'out' */ 1001 P1_2_AMUXA = 4, /* Analog mux bus A */ 1002 P1_2_AMUXB = 5, /* Analog mux bus B */ 1003 P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1004 P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1005 P1_2_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:1 */ 1006 P1_2_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:1 */ 1007 P1_2_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:1 */ 1008 P1_2_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:1 */ 1009 P1_2_TCPWM0_LINE518 = 16, /* Digital Active - tcpwm[0].line[518]:0 */ 1010 P1_2_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:2 */ 1011 P1_2_PERI_TR_IO_INPUT0 = 26, /* Digital Active - peri.tr_io_input[0]:0 */ 1012 P1_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:1 */ 1013 1014 /* P1.3 */ 1015 P1_3_GPIO = 0, /* GPIO controls 'out' */ 1016 P1_3_AMUXA = 4, /* Analog mux bus A */ 1017 P1_3_AMUXB = 5, /* Analog mux bus B */ 1018 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1019 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1020 P1_3_TCPWM0_LINE8 = 8, /* Digital Active - tcpwm[0].line[8]:1 */ 1021 P1_3_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:1 */ 1022 P1_3_TCPWM0_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[24]:1 */ 1023 P1_3_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:1 */ 1024 P1_3_TCPWM0_LINE519 = 16, /* Digital Active - tcpwm[0].line[519]:0 */ 1025 P1_3_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:2 */ 1026 P1_3_PERI_TR_IO_INPUT1 = 26, /* Digital Active - peri.tr_io_input[1]:0 */ 1027 P1_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:1 */ 1028 1029 /* P2.0 */ 1030 P2_0_GPIO = 0, /* GPIO controls 'out' */ 1031 P2_0_AMUXA = 4, /* Analog mux bus A */ 1032 P2_0_AMUXB = 5, /* Analog mux bus B */ 1033 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1034 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1035 P2_0_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 1036 P2_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:1 */ 1037 P2_0_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ 1038 P2_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ 1039 P2_0_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:0 */ 1040 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 1041 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 1042 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 1043 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 1044 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 1045 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 1046 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 1047 1048 /* P2.1 */ 1049 P2_1_GPIO = 0, /* GPIO controls 'out' */ 1050 P2_1_AMUXA = 4, /* Analog mux bus A */ 1051 P2_1_AMUXB = 5, /* Analog mux bus B */ 1052 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1053 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1054 P2_1_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 1055 P2_1_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 1056 P2_1_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:1 */ 1057 P2_1_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ 1058 P2_1_TCPWM0_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1551]:0 */ 1059 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 1060 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 1061 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 1062 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 1063 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 1064 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 1065 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 1066 1067 /* P2.2 */ 1068 P2_2_GPIO = 0, /* GPIO controls 'out' */ 1069 P2_2_AMUXA = 4, /* Analog mux bus A */ 1070 P2_2_AMUXB = 5, /* Analog mux bus B */ 1071 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1072 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1073 P2_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 1074 P2_2_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 1075 P2_2_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:1 */ 1076 P2_2_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:1 */ 1077 P2_2_TCPWM0_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1554]:0 */ 1078 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 1079 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 1080 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 1081 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 1082 P2_2_ETH0_RX_ER = 24, /* Digital Active - eth[0].rx_er:0 */ 1083 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 1084 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 1085 1086 /* P2.3 */ 1087 P2_3_GPIO = 0, /* GPIO controls 'out' */ 1088 P2_3_AMUXA = 4, /* Analog mux bus A */ 1089 P2_3_AMUXB = 5, /* Analog mux bus B */ 1090 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1091 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1092 P2_3_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 1093 P2_3_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 1094 P2_3_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:1 */ 1095 P2_3_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:1 */ 1096 P2_3_TCPWM0_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1557]:0 */ 1097 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 1098 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 1099 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 1100 P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL = 24, /* Digital Active - eth[0].eth_tsu_timer_cmp_val:0 */ 1101 P2_3_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:1 */ 1102 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 1103 1104 /* P2.4 */ 1105 P2_4_GPIO = 0, /* GPIO controls 'out' */ 1106 P2_4_AMUXA = 4, /* Analog mux bus A */ 1107 P2_4_AMUXB = 5, /* Analog mux bus B */ 1108 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1109 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1110 P2_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 1111 P2_4_TCPWM0_LINE_COMPL4 = 9, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 1112 P2_4_TCPWM0_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[9]:1 */ 1113 P2_4_TCPWM0_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[13]:1 */ 1114 P2_4_TCPWM0_LINE_COMPL516 = 16, /* Digital Active - tcpwm[0].line_compl[516]:0 */ 1115 P2_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:0 */ 1116 P2_4_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:1 */ 1117 P2_4_PERI_TR_IO_INPUT6 = 26, /* Digital Active - peri.tr_io_input[6]:0 */ 1118 1119 /* P2.5 */ 1120 P2_5_GPIO = 0, /* GPIO controls 'out' */ 1121 P2_5_AMUXA = 4, /* Analog mux bus A */ 1122 P2_5_AMUXB = 5, /* Analog mux bus B */ 1123 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1124 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1125 P2_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 1126 P2_5_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 1127 P2_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:1 */ 1128 P2_5_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:1 */ 1129 P2_5_TCPWM0_LINE_COMPL517 = 16, /* Digital Active - tcpwm[0].line_compl[517]:0 */ 1130 P2_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:0 */ 1131 P2_5_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:1 */ 1132 P2_5_PERI_TR_IO_INPUT7 = 26, /* Digital Active - peri.tr_io_input[7]:0 */ 1133 1134 /* P3.0 */ 1135 P3_0_GPIO = 0, /* GPIO controls 'out' */ 1136 P3_0_AMUXA = 4, /* Analog mux bus A */ 1137 P3_0_AMUXB = 5, /* Analog mux bus B */ 1138 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1139 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1140 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 1141 P3_0_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 1142 P3_0_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ 1143 P3_0_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:1 */ 1144 P3_0_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:0 */ 1145 P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ 1146 P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ 1147 P3_0_CANFD0_TTCAN_TX3 = 21, /* Digital Active - canfd[0].ttcan_tx[3]:0 */ 1148 P3_0_ETH0_MDIO = 24, /* Digital Active - eth[0].mdio:0 */ 1149 P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 1150 1151 /* P3.1 */ 1152 P3_1_GPIO = 0, /* GPIO controls 'out' */ 1153 P3_1_AMUXA = 4, /* Analog mux bus A */ 1154 P3_1_AMUXB = 5, /* Analog mux bus B */ 1155 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1156 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1157 P3_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 1158 P3_1_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 1159 P3_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ 1160 P3_1_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:1 */ 1161 P3_1_TCPWM0_LINE_COMPL519 = 16, /* Digital Active - tcpwm[0].line_compl[519]:0 */ 1162 P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ 1163 P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ 1164 P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ 1165 P3_1_CANFD0_TTCAN_RX3 = 21, /* Digital Active - canfd[0].ttcan_rx[3]:0 */ 1166 P3_1_ETH0_MDC = 24, /* Digital Active - eth[0].mdc:0 */ 1167 P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 1168 1169 /* P3.2 */ 1170 P3_2_GPIO = 0, /* GPIO controls 'out' */ 1171 P3_2_AMUXA = 4, /* Analog mux bus A */ 1172 P3_2_AMUXB = 5, /* Analog mux bus B */ 1173 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1174 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1175 P3_2_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:1 */ 1176 P3_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 1177 P3_2_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:1 */ 1178 P3_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ 1179 P3_2_TCPWM0_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1549]:0 */ 1180 P3_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:0 */ 1181 P3_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:0 */ 1182 P3_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:0 */ 1183 1184 /* P3.3 */ 1185 P3_3_GPIO = 0, /* GPIO controls 'out' */ 1186 P3_3_AMUXA = 4, /* Analog mux bus A */ 1187 P3_3_AMUXB = 5, /* Analog mux bus B */ 1188 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1189 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1190 P3_3_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:1 */ 1191 P3_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ 1192 P3_3_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:1 */ 1193 P3_3_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:1 */ 1194 P3_3_TCPWM0_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1552]:0 */ 1195 P3_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:0 */ 1196 P3_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:0 */ 1197 1198 /* P3.4 */ 1199 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1200 P3_4_AMUXA = 4, /* Analog mux bus A */ 1201 P3_4_AMUXB = 5, /* Analog mux bus B */ 1202 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1203 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1204 P3_4_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:1 */ 1205 P3_4_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ 1206 P3_4_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:1 */ 1207 P3_4_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:1 */ 1208 P3_4_TCPWM0_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1555]:0 */ 1209 P3_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:0 */ 1210 P3_4_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:2 */ 1211 1212 /* P3.5 */ 1213 P3_5_GPIO = 0, /* GPIO controls 'out' */ 1214 P3_5_AMUXA = 4, /* Analog mux bus A */ 1215 P3_5_AMUXB = 5, /* Analog mux bus B */ 1216 P3_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1217 P3_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1218 P3_5_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:1 */ 1219 P3_5_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ 1220 P3_5_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:1 */ 1221 P3_5_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:1 */ 1222 P3_5_TCPWM0_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1558]:0 */ 1223 P3_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:0 */ 1224 P3_5_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:2 */ 1225 1226 /* P4.0 */ 1227 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1228 P4_0_AMUXA = 4, /* Analog mux bus A */ 1229 P4_0_AMUXB = 5, /* Analog mux bus B */ 1230 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1231 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1232 P4_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 1233 P4_0_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ 1234 P4_0_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:0 */ 1235 P4_0_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:1 */ 1236 P4_0_PASS0_SAR_EXT_MUX_SEL0 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[0] */ 1237 P4_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:0 */ 1238 P4_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:0 */ 1239 P4_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:1 */ 1240 P4_0_PERI_TR_IO_INPUT10 = 26, /* Digital Active - peri.tr_io_input[10]:0 */ 1241 1242 /* P4.1 */ 1243 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1244 P4_1_AMUXA = 4, /* Analog mux bus A */ 1245 P4_1_AMUXB = 5, /* Analog mux bus B */ 1246 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1247 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1248 P4_1_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 1249 P4_1_TCPWM0_LINE_COMPL4 = 9, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 1250 P4_1_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:0 */ 1251 P4_1_TCPWM0_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[13]:0 */ 1252 P4_1_PASS0_SAR_EXT_MUX_SEL1 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[1] */ 1253 P4_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:0 */ 1254 P4_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:0 */ 1255 P4_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:0 */ 1256 P4_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:1 */ 1257 P4_1_PERI_TR_IO_INPUT11 = 26, /* Digital Active - peri.tr_io_input[11]:0 */ 1258 1259 /* P4.2 */ 1260 P4_2_GPIO = 0, /* GPIO controls 'out' */ 1261 P4_2_AMUXA = 4, /* Analog mux bus A */ 1262 P4_2_AMUXB = 5, /* Analog mux bus B */ 1263 P4_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1264 P4_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1265 P4_2_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ 1266 P4_2_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:0 */ 1267 P4_2_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:0 */ 1268 P4_2_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:0 */ 1269 P4_2_PASS0_SAR_EXT_MUX_SEL2 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[2] */ 1270 P4_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:0 */ 1271 P4_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:0 */ 1272 P4_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:0 */ 1273 P4_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:1 */ 1274 P4_2_PERI_TR_IO_INPUT12 = 26, /* Digital Active - peri.tr_io_input[12]:0 */ 1275 1276 /* P4.3 */ 1277 P4_3_GPIO = 0, /* GPIO controls 'out' */ 1278 P4_3_AMUXA = 4, /* Analog mux bus A */ 1279 P4_3_AMUXB = 5, /* Analog mux bus B */ 1280 P4_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1281 P4_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1282 P4_3_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 1283 P4_3_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:0 */ 1284 P4_3_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:0 */ 1285 P4_3_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:0 */ 1286 P4_3_PASS0_SAR_EXT_MUX_EN0 = 16, /* Digital Active - pass[0].sar_ext_mux_en[0] */ 1287 P4_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:0 */ 1288 P4_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:0 */ 1289 P4_3_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:1 */ 1290 P4_3_PERI_TR_IO_INPUT13 = 26, /* Digital Active - peri.tr_io_input[13]:0 */ 1291 1292 /* P4.4 */ 1293 P4_4_GPIO = 0, /* GPIO controls 'out' */ 1294 P4_4_AMUXA = 4, /* Analog mux bus A */ 1295 P4_4_AMUXB = 5, /* Analog mux bus B */ 1296 P4_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1297 P4_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1298 P4_4_TCPWM0_LINE8 = 8, /* Digital Active - tcpwm[0].line[8]:0 */ 1299 P4_4_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:0 */ 1300 P4_4_TCPWM0_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[24]:0 */ 1301 P4_4_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:0 */ 1302 P4_4_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:1 */ 1303 P4_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:0 */ 1304 P4_4_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:1 */ 1305 1306 /* P5.0 */ 1307 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1308 P5_0_AMUXA = 4, /* Analog mux bus A */ 1309 P5_0_AMUXB = 5, /* Analog mux bus B */ 1310 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1311 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1312 P5_0_TCPWM0_LINE9 = 8, /* Digital Active - tcpwm[0].line[9]:0 */ 1313 P5_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:0 */ 1314 P5_0_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ 1315 P5_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ 1316 P5_0_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:1 */ 1317 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 1318 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 1319 1320 /* P5.1 */ 1321 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1322 P5_1_AMUXA = 4, /* Analog mux bus A */ 1323 P5_1_AMUXB = 5, /* Analog mux bus B */ 1324 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1325 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1326 P5_1_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:0 */ 1327 P5_1_TCPWM0_LINE_COMPL9 = 9, /* Digital Active - tcpwm[0].line_compl[9]:0 */ 1328 P5_1_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ 1329 P5_1_TCPWM0_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ 1330 P5_1_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:1 */ 1331 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 1332 1333 /* P5.2 */ 1334 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1335 P5_2_AMUXA = 4, /* Analog mux bus A */ 1336 P5_2_AMUXB = 5, /* Analog mux bus B */ 1337 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1338 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1339 P5_2_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:0 */ 1340 P5_2_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:0 */ 1341 P5_2_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:0 */ 1342 P5_2_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:0 */ 1343 P5_2_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:2 */ 1344 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 1345 1346 /* P5.3 */ 1347 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1348 P5_3_AMUXA = 4, /* Analog mux bus A */ 1349 P5_3_AMUXB = 5, /* Analog mux bus B */ 1350 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1351 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1352 P5_3_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:0 */ 1353 P5_3_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:0 */ 1354 P5_3_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:0 */ 1355 P5_3_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:0 */ 1356 P5_3_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:2 */ 1357 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 1358 1359 /* P5.4 */ 1360 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1361 P5_4_AMUXA = 4, /* Analog mux bus A */ 1362 P5_4_AMUXB = 5, /* Analog mux bus B */ 1363 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1364 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1365 P5_4_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:0 */ 1366 P5_4_TCPWM0_LINE_COMPL12 = 9, /* Digital Active - tcpwm[0].line_compl[12]:0 */ 1367 P5_4_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:0 */ 1368 P5_4_TCPWM0_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:0 */ 1369 P5_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:0 */ 1370 P5_4_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:1 */ 1371 1372 /* P5.5 */ 1373 P5_5_GPIO = 0, /* GPIO controls 'out' */ 1374 P5_5_AMUXA = 4, /* Analog mux bus A */ 1375 P5_5_AMUXB = 5, /* Analog mux bus B */ 1376 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1377 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1378 P5_5_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:0 */ 1379 P5_5_TCPWM0_LINE_COMPL13 = 9, /* Digital Active - tcpwm[0].line_compl[13]:0 */ 1380 P5_5_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:0 */ 1381 P5_5_TCPWM0_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[40]:0 */ 1382 P5_5_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:0 */ 1383 P5_5_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:1 */ 1384 1385 /* P6.0 */ 1386 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1387 P6_0_AMUXA = 4, /* Analog mux bus A */ 1388 P6_0_AMUXB = 5, /* Analog mux bus B */ 1389 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1390 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1391 P6_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ 1392 P6_0_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:0 */ 1393 P6_0_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:0 */ 1394 P6_0_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:0 */ 1395 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 1396 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 1397 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 1398 P6_0_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:1 */ 1399 1400 /* P6.1 */ 1401 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1402 P6_1_AMUXA = 4, /* Analog mux bus A */ 1403 P6_1_AMUXB = 5, /* Analog mux bus B */ 1404 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1405 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1406 P6_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 1407 P6_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 1408 P6_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 1409 P6_1_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:0 */ 1410 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 1411 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 1412 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 1413 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 1414 1415 /* P6.2 */ 1416 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1417 P6_2_AMUXA = 4, /* Analog mux bus A */ 1418 P6_2_AMUXB = 5, /* Analog mux bus B */ 1419 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1420 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1421 P6_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ 1422 P6_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 1423 P6_2_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:0 */ 1424 P6_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 1425 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 1426 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 1427 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 1428 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 1429 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 1430 P6_2_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:0 */ 1431 1432 /* P6.3 */ 1433 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1434 P6_3_AMUXA = 4, /* Analog mux bus A */ 1435 P6_3_AMUXB = 5, /* Analog mux bus B */ 1436 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1437 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1438 P6_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 1439 P6_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 1440 P6_3_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 1441 P6_3_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:0 */ 1442 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 1443 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 1444 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 1445 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 1446 P6_3_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:0 */ 1447 P6_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:0 */ 1448 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 1449 1450 /* P6.4 */ 1451 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1452 P6_4_AMUXA = 4, /* Analog mux bus A */ 1453 P6_4_AMUXB = 5, /* Analog mux bus B */ 1454 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1455 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1456 P6_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ 1457 P6_4_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 1458 P6_4_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:0 */ 1459 P6_4_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:0 */ 1460 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 1461 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 1462 P6_4_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:0 */ 1463 P6_4_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:0 */ 1464 1465 /* P6.5 */ 1466 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1467 P6_5_AMUXA = 4, /* Analog mux bus A */ 1468 P6_5_AMUXB = 5, /* Analog mux bus B */ 1469 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1470 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1471 P6_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 1472 P6_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 1473 P6_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:0 */ 1474 P6_5_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:0 */ 1475 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 1476 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 1477 P6_5_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:0 */ 1478 P6_5_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:0 */ 1479 1480 /* P6.6 */ 1481 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1482 P6_6_AMUXA = 4, /* Analog mux bus A */ 1483 P6_6_AMUXB = 5, /* Analog mux bus B */ 1484 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1485 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1486 P6_6_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:0 */ 1487 P6_6_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 1488 P6_6_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:0 */ 1489 P6_6_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:0 */ 1490 P6_6_SCB4_SPI_SELECT3 = 19, /* Digital Active - scb[4].spi_select3:0 */ 1491 P6_6_PERI_TR_IO_INPUT8 = 26, /* Digital Active - peri.tr_io_input[8]:0 */ 1492 1493 /* P6.7 */ 1494 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1495 P6_7_AMUXA = 4, /* Analog mux bus A */ 1496 P6_7_AMUXB = 5, /* Analog mux bus B */ 1497 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1498 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1499 P6_7_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 1500 P6_7_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ 1501 P6_7_TCPWM0_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[9]:0 */ 1502 P6_7_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:0 */ 1503 P6_7_PERI_TR_IO_INPUT9 = 26, /* Digital Active - peri.tr_io_input[9]:0 */ 1504 1505 /* P7.0 */ 1506 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1507 P7_0_AMUXA = 4, /* Analog mux bus A */ 1508 P7_0_AMUXB = 5, /* Analog mux bus B */ 1509 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1510 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1511 P7_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ 1512 P7_0_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 1513 P7_0_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:0 */ 1514 P7_0_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:0 */ 1515 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 1516 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 1517 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 1518 P7_0_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:0 */ 1519 P7_0_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:0 */ 1520 1521 /* P7.1 */ 1522 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1523 P7_1_AMUXA = 4, /* Analog mux bus A */ 1524 P7_1_AMUXB = 5, /* Analog mux bus B */ 1525 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1526 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1527 P7_1_TCPWM0_LINE15 = 8, /* Digital Active - tcpwm[0].line[15]:0 */ 1528 P7_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 1529 P7_1_TCPWM0_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[45]:0 */ 1530 P7_1_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:0 */ 1531 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 1532 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 1533 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 1534 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 1535 P7_1_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:0 */ 1536 P7_1_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:0 */ 1537 1538 /* P7.2 */ 1539 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1540 P7_2_AMUXA = 4, /* Analog mux bus A */ 1541 P7_2_AMUXB = 5, /* Analog mux bus B */ 1542 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1543 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1544 P7_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ 1545 P7_2_TCPWM0_LINE_COMPL15 = 9, /* Digital Active - tcpwm[0].line_compl[15]:0 */ 1546 P7_2_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:0 */ 1547 P7_2_TCPWM0_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[46]:0 */ 1548 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 1549 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 1550 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 1551 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 1552 P7_2_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:0 */ 1553 P7_2_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:0 */ 1554 1555 /* P7.3 */ 1556 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1557 P7_3_AMUXA = 4, /* Analog mux bus A */ 1558 P7_3_AMUXB = 5, /* Analog mux bus B */ 1559 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1560 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1561 P7_3_TCPWM0_LINE16 = 8, /* Digital Active - tcpwm[0].line[16]:0 */ 1562 P7_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 1563 P7_3_TCPWM0_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[48]:0 */ 1564 P7_3_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:0 */ 1565 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 1566 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 1567 P7_3_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:0 */ 1568 P7_3_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:0 */ 1569 1570 /* P7.4 */ 1571 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1572 P7_4_AMUXA = 4, /* Analog mux bus A */ 1573 P7_4_AMUXB = 5, /* Analog mux bus B */ 1574 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1575 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1576 P7_4_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:0 */ 1577 P7_4_TCPWM0_LINE_COMPL16 = 9, /* Digital Active - tcpwm[0].line_compl[16]:0 */ 1578 P7_4_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:0 */ 1579 P7_4_TCPWM0_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[49]:0 */ 1580 P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ 1581 P7_4_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:0 */ 1582 P7_4_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:0 */ 1583 1584 /* P7.5 */ 1585 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1586 P7_5_AMUXA = 4, /* Analog mux bus A */ 1587 P7_5_AMUXB = 5, /* Analog mux bus B */ 1588 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1589 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1590 P7_5_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:0 */ 1591 P7_5_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 1592 P7_5_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:0 */ 1593 P7_5_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:0 */ 1594 P7_5_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:0 */ 1595 P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ 1596 P7_5_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:0 */ 1597 P7_5_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:0 */ 1598 1599 /* P7.6 */ 1600 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1601 P7_6_AMUXA = 4, /* Analog mux bus A */ 1602 P7_6_AMUXB = 5, /* Analog mux bus B */ 1603 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1604 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1605 P7_6_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:0 */ 1606 P7_6_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:0 */ 1607 P7_6_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:0 */ 1608 P7_6_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:0 */ 1609 P7_6_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:0 */ 1610 P7_6_PERI_TR_IO_INPUT16 = 26, /* Digital Active - peri.tr_io_input[16]:0 */ 1611 1612 /* P7.7 */ 1613 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1614 P7_7_AMUXA = 4, /* Analog mux bus A */ 1615 P7_7_AMUXB = 5, /* Analog mux bus B */ 1616 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1617 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1618 P7_7_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:0 */ 1619 P7_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ 1620 P7_7_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:0 */ 1621 P7_7_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:0 */ 1622 P7_7_LIN0_LIN_EN10 = 18, /* Digital Active - lin[0].lin_en[10]:0 */ 1623 P7_7_PERI_TR_IO_INPUT17 = 26, /* Digital Active - peri.tr_io_input[17]:0 */ 1624 1625 /* P8.0 */ 1626 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1627 P8_0_AMUXA = 4, /* Analog mux bus A */ 1628 P8_0_AMUXB = 5, /* Analog mux bus B */ 1629 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1630 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1631 P8_0_TCPWM0_LINE19 = 8, /* Digital Active - tcpwm[0].line[19]:0 */ 1632 P8_0_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:0 */ 1633 P8_0_TCPWM0_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[57]:0 */ 1634 P8_0_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:0 */ 1635 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 1636 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 1637 P8_0_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:0 */ 1638 P8_0_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:0 */ 1639 1640 /* P8.1 */ 1641 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1642 P8_1_AMUXA = 4, /* Analog mux bus A */ 1643 P8_1_AMUXB = 5, /* Analog mux bus B */ 1644 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1645 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1646 P8_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ 1647 P8_1_TCPWM0_LINE_COMPL19 = 9, /* Digital Active - tcpwm[0].line_compl[19]:0 */ 1648 P8_1_TCPWM0_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[60]:0 */ 1649 P8_1_TCPWM0_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[58]:0 */ 1650 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 1651 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 1652 P8_1_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:0 */ 1653 P8_1_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:0 */ 1654 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 1655 1656 /* P8.2 */ 1657 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1658 P8_2_AMUXA = 4, /* Analog mux bus A */ 1659 P8_2_AMUXB = 5, /* Analog mux bus B */ 1660 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1661 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1662 P8_2_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:0 */ 1663 P8_2_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:0 */ 1664 P8_2_TCPWM0_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[63]:0 */ 1665 P8_2_TCPWM0_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[61]:0 */ 1666 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 1667 P8_2_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:0 */ 1668 P8_2_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:0 */ 1669 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 1670 1671 /* P8.3 */ 1672 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1673 P8_3_AMUXA = 4, /* Analog mux bus A */ 1674 P8_3_AMUXB = 5, /* Analog mux bus B */ 1675 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1676 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1677 P8_3_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:0 */ 1678 P8_3_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:0 */ 1679 P8_3_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:0 */ 1680 P8_3_TCPWM0_TR_ONE_CNT_IN64 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[64]:0 */ 1681 P8_3_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:1 */ 1682 1683 /* P8.4 */ 1684 P8_4_GPIO = 0, /* GPIO controls 'out' */ 1685 P8_4_AMUXA = 4, /* Analog mux bus A */ 1686 P8_4_AMUXB = 5, /* Analog mux bus B */ 1687 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1688 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1689 P8_4_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:0 */ 1690 P8_4_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:0 */ 1691 P8_4_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:0 */ 1692 P8_4_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:0 */ 1693 P8_4_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:1 */ 1694 1695 /* P9.0 */ 1696 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1697 P9_0_AMUXA = 4, /* Analog mux bus A */ 1698 P9_0_AMUXB = 5, /* Analog mux bus B */ 1699 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1700 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1701 P9_0_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:0 */ 1702 P9_0_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:0 */ 1703 P9_0_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:0 */ 1704 P9_0_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:0 */ 1705 1706 /* P9.1 */ 1707 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1708 P9_1_AMUXA = 4, /* Analog mux bus A */ 1709 P9_1_AMUXB = 5, /* Analog mux bus B */ 1710 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1711 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1712 P9_1_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:0 */ 1713 P9_1_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:0 */ 1714 P9_1_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:0 */ 1715 P9_1_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:0 */ 1716 P9_1_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:0 */ 1717 1718 /* P9.2 */ 1719 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1720 P9_2_AMUXA = 4, /* Analog mux bus A */ 1721 P9_2_AMUXB = 5, /* Analog mux bus B */ 1722 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1723 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1724 P9_2_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:0 */ 1725 P9_2_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:0 */ 1726 P9_2_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:0 */ 1727 P9_2_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:0 */ 1728 P9_2_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:0 */ 1729 1730 /* P9.3 */ 1731 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1732 P9_3_AMUXA = 4, /* Analog mux bus A */ 1733 P9_3_AMUXB = 5, /* Analog mux bus B */ 1734 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1735 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1736 P9_3_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:0 */ 1737 P9_3_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:0 */ 1738 P9_3_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:0 */ 1739 P9_3_TCPWM0_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[79]:0 */ 1740 P9_3_LIN0_LIN_EN12 = 21, /* Digital Active - lin[0].lin_en[12]:0 */ 1741 1742 /* P10.0 */ 1743 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1744 P10_0_AMUXA = 4, /* Analog mux bus A */ 1745 P10_0_AMUXB = 5, /* Analog mux bus B */ 1746 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1747 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1748 P10_0_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:0 */ 1749 P10_0_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:0 */ 1750 P10_0_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:0 */ 1751 P10_0_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:0 */ 1752 P10_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:1 */ 1753 P10_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:1 */ 1754 P10_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:2 */ 1755 P10_0_PERI_TR_IO_INPUT18 = 26, /* Digital Active - peri.tr_io_input[18]:0 */ 1756 1757 /* P10.1 */ 1758 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1759 P10_1_AMUXA = 4, /* Analog mux bus A */ 1760 P10_1_AMUXB = 5, /* Analog mux bus B */ 1761 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1762 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1763 P10_1_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:0 */ 1764 P10_1_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:0 */ 1765 P10_1_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:0 */ 1766 P10_1_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:0 */ 1767 P10_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:1 */ 1768 P10_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:1 */ 1769 P10_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:1 */ 1770 P10_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:2 */ 1771 P10_1_PERI_TR_IO_INPUT19 = 26, /* Digital Active - peri.tr_io_input[19]:0 */ 1772 1773 /* P10.2 */ 1774 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1775 P10_2_AMUXA = 4, /* Analog mux bus A */ 1776 P10_2_AMUXB = 5, /* Analog mux bus B */ 1777 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1778 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1779 P10_2_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:0 */ 1780 P10_2_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:0 */ 1781 P10_2_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:0 */ 1782 P10_2_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:0 */ 1783 P10_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:1 */ 1784 P10_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:1 */ 1785 P10_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:1 */ 1786 P10_2_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:1 */ 1787 1788 /* P10.3 */ 1789 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1790 P10_3_AMUXA = 4, /* Analog mux bus A */ 1791 P10_3_AMUXB = 5, /* Analog mux bus B */ 1792 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1793 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1794 P10_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:0 */ 1795 P10_3_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:0 */ 1796 P10_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:0 */ 1797 P10_3_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:0 */ 1798 P10_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:1 */ 1799 P10_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:1 */ 1800 P10_3_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:1 */ 1801 1802 /* P10.4 */ 1803 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1804 P10_4_AMUXA = 4, /* Analog mux bus A */ 1805 P10_4_AMUXB = 5, /* Analog mux bus B */ 1806 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1807 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1808 P10_4_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:0 */ 1809 P10_4_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:0 */ 1810 P10_4_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:0 */ 1811 P10_4_TCPWM0_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[94]:0 */ 1812 P10_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:1 */ 1813 P10_4_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:1 */ 1814 1815 /* P10.5 */ 1816 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1817 P10_5_AMUXA = 4, /* Analog mux bus A */ 1818 P10_5_AMUXB = 5, /* Analog mux bus B */ 1819 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1820 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1821 P10_5_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:0 */ 1822 P10_5_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:0 */ 1823 P10_5_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:0 */ 1824 P10_5_TCPWM0_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[97]:0 */ 1825 P10_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:1 */ 1826 P10_5_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:0 */ 1827 1828 /* P10.6 */ 1829 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1830 P10_6_AMUXA = 4, /* Analog mux bus A */ 1831 P10_6_AMUXB = 5, /* Analog mux bus B */ 1832 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1833 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1834 P10_6_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:0 */ 1835 P10_6_TCPWM0_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[100]:0 */ 1836 P10_6_TCPWM0_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:0 */ 1837 P10_6_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:0 */ 1838 P10_6_TCPWM0_LINE34 = 22, /* Digital Active - tcpwm[0].line[34]:0 */ 1839 1840 /* P10.7 */ 1841 P10_7_GPIO = 0, /* GPIO controls 'out' */ 1842 P10_7_AMUXA = 4, /* Analog mux bus A */ 1843 P10_7_AMUXB = 5, /* Analog mux bus B */ 1844 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1845 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1846 P10_7_TCPWM0_LINE35 = 8, /* Digital Active - tcpwm[0].line[35]:0 */ 1847 P10_7_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:0 */ 1848 P10_7_TCPWM0_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[105]:0 */ 1849 P10_7_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:0 */ 1850 P10_7_LIN0_LIN_EN13 = 21, /* Digital Active - lin[0].lin_en[13]:0 */ 1851 1852 /* P11.0 */ 1853 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1854 P11_0_AMUXA = 4, /* Analog mux bus A */ 1855 P11_0_AMUXB = 5, /* Analog mux bus B */ 1856 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1857 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1858 P11_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:2 */ 1859 P11_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:2 */ 1860 P11_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:2 */ 1861 P11_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:2 */ 1862 P11_0_AUDIOSS0_MCLK = 25, /* Digital Active - audioss[0].mclk:0 */ 1863 1864 /* P11.1 */ 1865 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1866 P11_1_AMUXA = 4, /* Analog mux bus A */ 1867 P11_1_AMUXB = 5, /* Analog mux bus B */ 1868 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1869 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1870 P11_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:2 */ 1871 P11_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:2 */ 1872 P11_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:2 */ 1873 P11_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:2 */ 1874 P11_1_AUDIOSS0_TX_SCK = 25, /* Digital Active - audioss[0].tx_sck:0 */ 1875 1876 /* P11.2 */ 1877 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1878 P11_2_AMUXA = 4, /* Analog mux bus A */ 1879 P11_2_AMUXB = 5, /* Analog mux bus B */ 1880 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1881 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1882 P11_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:2 */ 1883 P11_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:2 */ 1884 P11_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:2 */ 1885 P11_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:2 */ 1886 P11_2_AUDIOSS0_TX_WS = 25, /* Digital Active - audioss[0].tx_ws:0 */ 1887 1888 /* P12.0 */ 1889 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1890 P12_0_AMUXA = 4, /* Analog mux bus A */ 1891 P12_0_AMUXB = 5, /* Analog mux bus B */ 1892 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1893 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1894 P12_0_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ 1895 P12_0_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:0 */ 1896 P12_0_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:0 */ 1897 P12_0_TCPWM0_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:0 */ 1898 P12_0_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:0 */ 1899 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 1900 P12_0_TCPWM0_LINE_COMPL35 = 23, /* Digital Active - tcpwm[0].line_compl[35]:0 */ 1901 P12_0_AUDIOSS0_TX_SDO = 25, /* Digital Active - audioss[0].tx_sdo:0 */ 1902 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 1903 1904 /* P12.1 */ 1905 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1906 P12_1_AMUXA = 4, /* Analog mux bus A */ 1907 P12_1_AMUXB = 5, /* Analog mux bus B */ 1908 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1909 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1910 P12_1_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ 1911 P12_1_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ 1912 P12_1_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:0 */ 1913 P12_1_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:0 */ 1914 P12_1_SCB8_UART_TX = 17, /* Digital Active - scb[8].uart_tx:0 */ 1915 P12_1_SCB8_I2C_SDA = 18, /* Digital Active - scb[8].i2c_sda:0 */ 1916 P12_1_SCB8_SPI_MOSI = 19, /* Digital Active - scb[8].spi_mosi:0 */ 1917 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 1918 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 1919 P12_1_AUDIOSS0_CLK_I2S_IF = 25, /* Digital Active - audioss[0].clk_i2s_if:0 */ 1920 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 1921 1922 /* P12.2 */ 1923 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1924 P12_2_AMUXA = 4, /* Analog mux bus A */ 1925 P12_2_AMUXB = 5, /* Analog mux bus B */ 1926 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1927 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1928 P12_2_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:0 */ 1929 P12_2_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:0 */ 1930 P12_2_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:0 */ 1931 P12_2_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:0 */ 1932 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 1933 P12_2_SCB8_UART_RTS = 17, /* Digital Active - scb[8].uart_rts:0 */ 1934 P12_2_SCB8_I2C_SCL = 18, /* Digital Active - scb[8].i2c_scl:0 */ 1935 P12_2_SCB8_SPI_CLK = 19, /* Digital Active - scb[8].spi_clk:0 */ 1936 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 1937 P12_2_AUDIOSS0_RX_SCK = 25, /* Digital Active - audioss[0].rx_sck:0 */ 1938 1939 /* P12.3 */ 1940 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1941 P12_3_AMUXA = 4, /* Analog mux bus A */ 1942 P12_3_AMUXB = 5, /* Analog mux bus B */ 1943 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1944 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1945 P12_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:0 */ 1946 P12_3_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:0 */ 1947 P12_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:0 */ 1948 P12_3_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:0 */ 1949 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 1950 P12_3_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:0 */ 1951 P12_3_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:0 */ 1952 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 1953 P12_3_AUDIOSS0_RX_WS = 25, /* Digital Active - audioss[0].rx_ws:0 */ 1954 1955 /* P12.4 */ 1956 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1957 P12_4_AMUXA = 4, /* Analog mux bus A */ 1958 P12_4_AMUXB = 5, /* Analog mux bus B */ 1959 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1960 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1961 P12_4_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:0 */ 1962 P12_4_TCPWM0_LINE_COMPL39 = 9, /* Digital Active - tcpwm[0].line_compl[39]:0 */ 1963 P12_4_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:0 */ 1964 P12_4_TCPWM0_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[118]:0 */ 1965 P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 1966 P12_4_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:0 */ 1967 P12_4_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:2 */ 1968 P12_4_AUDIOSS0_RX_SDI = 25, /* Digital Active - audioss[0].rx_sdi:0 */ 1969 1970 /* P12.5 */ 1971 P12_5_GPIO = 0, /* GPIO controls 'out' */ 1972 P12_5_AMUXA = 4, /* Analog mux bus A */ 1973 P12_5_AMUXB = 5, /* Analog mux bus B */ 1974 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1975 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1976 P12_5_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:0 */ 1977 P12_5_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:0 */ 1978 P12_5_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:0 */ 1979 P12_5_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:0 */ 1980 P12_5_PASS0_SAR_EXT_MUX_SEL5 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[5] */ 1981 P12_5_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:2 */ 1982 1983 /* P12.6 */ 1984 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1985 P12_6_AMUXA = 4, /* Analog mux bus A */ 1986 P12_6_AMUXB = 5, /* Analog mux bus B */ 1987 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1988 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1989 P12_6_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:0 */ 1990 P12_6_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:0 */ 1991 P12_6_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:0 */ 1992 P12_6_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:0 */ 1993 1994 /* P12.7 */ 1995 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1996 P12_7_AMUXA = 4, /* Analog mux bus A */ 1997 P12_7_AMUXB = 5, /* Analog mux bus B */ 1998 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1999 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2000 P12_7_TCPWM0_LINE43 = 8, /* Digital Active - tcpwm[0].line[43]:0 */ 2001 P12_7_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:0 */ 2002 P12_7_TCPWM0_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[129]:0 */ 2003 P12_7_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:0 */ 2004 2005 /* P13.0 */ 2006 P13_0_GPIO = 0, /* GPIO controls 'out' */ 2007 P13_0_AMUXA = 4, /* Analog mux bus A */ 2008 P13_0_AMUXB = 5, /* Analog mux bus B */ 2009 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2010 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2011 P13_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ 2012 P13_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:0 */ 2013 P13_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:0 */ 2014 P13_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:0 */ 2015 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 2016 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 2017 P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ 2018 P13_0_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:0 */ 2019 P13_0_AUDIOSS1_MCLK = 25, /* Digital Active - audioss[1].mclk:0 */ 2020 2021 /* P13.1 */ 2022 P13_1_GPIO = 0, /* GPIO controls 'out' */ 2023 P13_1_AMUXA = 4, /* Analog mux bus A */ 2024 P13_1_AMUXB = 5, /* Analog mux bus B */ 2025 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2026 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2027 P13_1_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:0 */ 2028 P13_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ 2029 P13_1_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:0 */ 2030 P13_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:0 */ 2031 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 2032 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 2033 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 2034 P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ 2035 P13_1_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:0 */ 2036 P13_1_AUDIOSS1_TX_SCK = 25, /* Digital Active - audioss[1].tx_sck:0 */ 2037 2038 /* P13.2 */ 2039 P13_2_GPIO = 0, /* GPIO controls 'out' */ 2040 P13_2_AMUXA = 4, /* Analog mux bus A */ 2041 P13_2_AMUXB = 5, /* Analog mux bus B */ 2042 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2043 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2044 P13_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ 2045 P13_2_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:0 */ 2046 P13_2_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:0 */ 2047 P13_2_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:0 */ 2048 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 2049 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 2050 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 2051 P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ 2052 P13_2_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:0 */ 2053 P13_2_AUDIOSS1_TX_WS = 25, /* Digital Active - audioss[1].tx_ws:0 */ 2054 2055 /* P13.3 */ 2056 P13_3_GPIO = 0, /* GPIO controls 'out' */ 2057 P13_3_AMUXA = 4, /* Analog mux bus A */ 2058 P13_3_AMUXB = 5, /* Analog mux bus B */ 2059 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2060 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2061 P13_3_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:0 */ 2062 P13_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ 2063 P13_3_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:0 */ 2064 P13_3_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:0 */ 2065 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 2066 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 2067 P13_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:2 */ 2068 P13_3_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:0 */ 2069 P13_3_AUDIOSS1_TX_SDO = 25, /* Digital Active - audioss[1].tx_sdo:0 */ 2070 2071 /* P13.4 */ 2072 P13_4_GPIO = 0, /* GPIO controls 'out' */ 2073 P13_4_AMUXA = 4, /* Analog mux bus A */ 2074 P13_4_AMUXB = 5, /* Analog mux bus B */ 2075 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2076 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2077 P13_4_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:0 */ 2078 P13_4_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:0 */ 2079 P13_4_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:0 */ 2080 P13_4_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:0 */ 2081 P13_4_TCPWM0_LINE516 = 16, /* Digital Active - tcpwm[0].line[516]:1 */ 2082 P13_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:2 */ 2083 P13_4_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:0 */ 2084 P13_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:0 */ 2085 P13_4_AUDIOSS1_CLK_I2S_IF = 25, /* Digital Active - audioss[1].clk_i2s_if:0 */ 2086 2087 /* P13.5 */ 2088 P13_5_GPIO = 0, /* GPIO controls 'out' */ 2089 P13_5_AMUXA = 4, /* Analog mux bus A */ 2090 P13_5_AMUXB = 5, /* Analog mux bus B */ 2091 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2092 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2093 P13_5_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:0 */ 2094 P13_5_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:0 */ 2095 P13_5_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:0 */ 2096 P13_5_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:0 */ 2097 P13_5_TCPWM0_LINE_COMPL516 = 16, /* Digital Active - tcpwm[0].line_compl[516]:1 */ 2098 P13_5_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:0 */ 2099 P13_5_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:0 */ 2100 P13_5_AUDIOSS1_RX_SCK = 25, /* Digital Active - audioss[1].rx_sck:0 */ 2101 2102 /* P13.6 */ 2103 P13_6_GPIO = 0, /* GPIO controls 'out' */ 2104 P13_6_AMUXA = 4, /* Analog mux bus A */ 2105 P13_6_AMUXB = 5, /* Analog mux bus B */ 2106 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2107 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2108 P13_6_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:0 */ 2109 P13_6_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:0 */ 2110 P13_6_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:0 */ 2111 P13_6_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:0 */ 2112 P13_6_TCPWM0_LINE517 = 16, /* Digital Active - tcpwm[0].line[517]:1 */ 2113 P13_6_SCB3_SPI_SELECT3 = 21, /* Digital Active - scb[3].spi_select3:0 */ 2114 P13_6_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:0 */ 2115 P13_6_AUDIOSS1_RX_WS = 25, /* Digital Active - audioss[1].rx_ws:0 */ 2116 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 2117 2118 /* P13.7 */ 2119 P13_7_GPIO = 0, /* GPIO controls 'out' */ 2120 P13_7_AMUXA = 4, /* Analog mux bus A */ 2121 P13_7_AMUXB = 5, /* Analog mux bus B */ 2122 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2123 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2124 P13_7_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:0 */ 2125 P13_7_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:0 */ 2126 P13_7_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:0 */ 2127 P13_7_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:0 */ 2128 P13_7_TCPWM0_LINE_COMPL517 = 16, /* Digital Active - tcpwm[0].line_compl[517]:1 */ 2129 P13_7_AUDIOSS1_RX_SDI = 25, /* Digital Active - audioss[1].rx_sdi:0 */ 2130 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 2131 2132 /* P14.0 */ 2133 P14_0_GPIO = 0, /* GPIO controls 'out' */ 2134 P14_0_AMUXA = 4, /* Analog mux bus A */ 2135 P14_0_AMUXB = 5, /* Analog mux bus B */ 2136 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2137 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2138 P14_0_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:0 */ 2139 P14_0_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:0 */ 2140 P14_0_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:0 */ 2141 P14_0_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:0 */ 2142 P14_0_TCPWM0_LINE518 = 16, /* Digital Active - tcpwm[0].line[518]:1 */ 2143 P14_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:0 */ 2144 P14_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:0 */ 2145 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 2146 P14_0_AUDIOSS2_MCLK = 25, /* Digital Active - audioss[2].mclk:0 */ 2147 2148 /* P14.1 */ 2149 P14_1_GPIO = 0, /* GPIO controls 'out' */ 2150 P14_1_AMUXA = 4, /* Analog mux bus A */ 2151 P14_1_AMUXB = 5, /* Analog mux bus B */ 2152 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2153 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2154 P14_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:0 */ 2155 P14_1_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:0 */ 2156 P14_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:0 */ 2157 P14_1_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:0 */ 2158 P14_1_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:1 */ 2159 P14_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:0 */ 2160 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 2161 P14_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:0 */ 2162 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 2163 P14_1_AUDIOSS2_TX_SCK = 25, /* Digital Active - audioss[2].tx_sck:0 */ 2164 2165 /* P14.2 */ 2166 P14_2_GPIO = 0, /* GPIO controls 'out' */ 2167 P14_2_AMUXA = 4, /* Analog mux bus A */ 2168 P14_2_AMUXB = 5, /* Analog mux bus B */ 2169 P14_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2170 P14_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2171 P14_2_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:0 */ 2172 P14_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:0 */ 2173 P14_2_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:0 */ 2174 P14_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:0 */ 2175 P14_2_TCPWM0_LINE519 = 16, /* Digital Active - tcpwm[0].line[519]:1 */ 2176 P14_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:0 */ 2177 P14_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:0 */ 2178 P14_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:0 */ 2179 P14_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:1 */ 2180 2181 /* P14.3 */ 2182 P14_3_GPIO = 0, /* GPIO controls 'out' */ 2183 P14_3_AMUXA = 4, /* Analog mux bus A */ 2184 P14_3_AMUXB = 5, /* Analog mux bus B */ 2185 P14_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2186 P14_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2187 P14_3_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:0 */ 2188 P14_3_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:0 */ 2189 P14_3_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:0 */ 2190 P14_3_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:0 */ 2191 P14_3_TCPWM0_LINE_COMPL519 = 16, /* Digital Active - tcpwm[0].line_compl[519]:1 */ 2192 P14_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:0 */ 2193 P14_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:0 */ 2194 P14_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:1 */ 2195 2196 /* P14.4 */ 2197 P14_4_GPIO = 0, /* GPIO controls 'out' */ 2198 P14_4_AMUXA = 4, /* Analog mux bus A */ 2199 P14_4_AMUXB = 5, /* Analog mux bus B */ 2200 P14_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2201 P14_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2202 P14_4_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:0 */ 2203 P14_4_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:0 */ 2204 P14_4_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:0 */ 2205 P14_4_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:0 */ 2206 P14_4_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:1 */ 2207 P14_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:0 */ 2208 P14_4_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:1 */ 2209 P14_4_AUDIOSS2_TX_WS = 25, /* Digital Active - audioss[2].tx_ws:0 */ 2210 2211 /* P14.5 */ 2212 P14_5_GPIO = 0, /* GPIO controls 'out' */ 2213 P14_5_AMUXA = 4, /* Analog mux bus A */ 2214 P14_5_AMUXB = 5, /* Analog mux bus B */ 2215 P14_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2216 P14_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2217 P14_5_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:0 */ 2218 P14_5_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:0 */ 2219 P14_5_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:0 */ 2220 P14_5_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:0 */ 2221 P14_5_TCPWM0_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1549]:1 */ 2222 P14_5_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:0 */ 2223 P14_5_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:0 */ 2224 P14_5_AUDIOSS2_TX_SDO = 25, /* Digital Active - audioss[2].tx_sdo:0 */ 2225 2226 /* P14.6 */ 2227 P14_6_GPIO = 0, /* GPIO controls 'out' */ 2228 P14_6_AMUXA = 4, /* Analog mux bus A */ 2229 P14_6_AMUXB = 5, /* Analog mux bus B */ 2230 P14_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2231 P14_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2232 P14_6_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:0 */ 2233 P14_6_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:0 */ 2234 P14_6_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:0 */ 2235 P14_6_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:0 */ 2236 P14_6_TCPWM0_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1551]:1 */ 2237 P14_6_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:0 */ 2238 P14_6_PERI_TR_IO_INPUT24 = 26, /* Digital Active - peri.tr_io_input[24]:0 */ 2239 2240 /* P14.7 */ 2241 P14_7_GPIO = 0, /* GPIO controls 'out' */ 2242 P14_7_AMUXA = 4, /* Analog mux bus A */ 2243 P14_7_AMUXB = 5, /* Analog mux bus B */ 2244 P14_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2245 P14_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2246 P14_7_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:0 */ 2247 P14_7_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:0 */ 2248 P14_7_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:0 */ 2249 P14_7_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:0 */ 2250 P14_7_TCPWM0_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1552]:1 */ 2251 P14_7_LIN0_LIN_EN14 = 18, /* Digital Active - lin[0].lin_en[14]:0 */ 2252 P14_7_PERI_TR_IO_INPUT25 = 26, /* Digital Active - peri.tr_io_input[25]:0 */ 2253 2254 /* P15.0 */ 2255 P15_0_GPIO = 0, /* GPIO controls 'out' */ 2256 P15_0_AMUXA = 4, /* Analog mux bus A */ 2257 P15_0_AMUXB = 5, /* Analog mux bus B */ 2258 P15_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2259 P15_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2260 P15_0_TCPWM0_LINE56 = 8, /* Digital Active - tcpwm[0].line[56]:0 */ 2261 P15_0_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:0 */ 2262 P15_0_TCPWM0_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[168]:0 */ 2263 P15_0_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:0 */ 2264 P15_0_TCPWM0_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1554]:1 */ 2265 P15_0_SCB9_UART_RX = 17, /* Digital Active - scb[9].uart_rx:0 */ 2266 P15_0_SCB9_SPI_MISO = 19, /* Digital Active - scb[9].spi_miso:0 */ 2267 P15_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:1 */ 2268 P15_0_AUDIOSS2_CLK_I2S_IF = 25, /* Digital Active - audioss[2].clk_i2s_if:0 */ 2269 2270 /* P15.1 */ 2271 P15_1_GPIO = 0, /* GPIO controls 'out' */ 2272 P15_1_AMUXA = 4, /* Analog mux bus A */ 2273 P15_1_AMUXB = 5, /* Analog mux bus B */ 2274 P15_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2275 P15_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2276 P15_1_TCPWM0_LINE57 = 8, /* Digital Active - tcpwm[0].line[57]:0 */ 2277 P15_1_TCPWM0_LINE_COMPL56 = 9, /* Digital Active - tcpwm[0].line_compl[56]:0 */ 2278 P15_1_TCPWM0_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[171]:0 */ 2279 P15_1_TCPWM0_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[169]:0 */ 2280 P15_1_TCPWM0_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1555]:1 */ 2281 P15_1_SCB9_UART_TX = 17, /* Digital Active - scb[9].uart_tx:0 */ 2282 P15_1_SCB9_I2C_SDA = 18, /* Digital Active - scb[9].i2c_sda:0 */ 2283 P15_1_SCB9_SPI_MOSI = 19, /* Digital Active - scb[9].spi_mosi:0 */ 2284 P15_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:1 */ 2285 P15_1_AUDIOSS2_RX_SCK = 25, /* Digital Active - audioss[2].rx_sck:0 */ 2286 2287 /* P15.2 */ 2288 P15_2_GPIO = 0, /* GPIO controls 'out' */ 2289 P15_2_AMUXA = 4, /* Analog mux bus A */ 2290 P15_2_AMUXB = 5, /* Analog mux bus B */ 2291 P15_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2292 P15_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2293 P15_2_TCPWM0_LINE58 = 8, /* Digital Active - tcpwm[0].line[58]:0 */ 2294 P15_2_TCPWM0_LINE_COMPL57 = 9, /* Digital Active - tcpwm[0].line_compl[57]:0 */ 2295 P15_2_TCPWM0_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[174]:0 */ 2296 P15_2_TCPWM0_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[172]:0 */ 2297 P15_2_TCPWM0_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1557]:1 */ 2298 P15_2_SCB9_UART_RTS = 17, /* Digital Active - scb[9].uart_rts:0 */ 2299 P15_2_SCB9_I2C_SCL = 18, /* Digital Active - scb[9].i2c_scl:0 */ 2300 P15_2_SCB9_SPI_CLK = 19, /* Digital Active - scb[9].spi_clk:0 */ 2301 P15_2_AUDIOSS2_RX_WS = 25, /* Digital Active - audioss[2].rx_ws:0 */ 2302 2303 /* P15.3 */ 2304 P15_3_GPIO = 0, /* GPIO controls 'out' */ 2305 P15_3_AMUXA = 4, /* Analog mux bus A */ 2306 P15_3_AMUXB = 5, /* Analog mux bus B */ 2307 P15_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2308 P15_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2309 P15_3_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:0 */ 2310 P15_3_TCPWM0_LINE_COMPL58 = 9, /* Digital Active - tcpwm[0].line_compl[58]:0 */ 2311 P15_3_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:0 */ 2312 P15_3_TCPWM0_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[175]:0 */ 2313 P15_3_TCPWM0_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1558]:1 */ 2314 P15_3_SCB9_UART_CTS = 17, /* Digital Active - scb[9].uart_cts:0 */ 2315 P15_3_SCB9_SPI_SELECT0 = 19, /* Digital Active - scb[9].spi_select0:0 */ 2316 P15_3_AUDIOSS2_RX_SDI = 25, /* Digital Active - audioss[2].rx_sdi:0 */ 2317 2318 /* P16.3 */ 2319 P16_3_GPIO = 0, /* GPIO controls 'out' */ 2320 P16_3_AMUXA = 4, /* Analog mux bus A */ 2321 P16_3_AMUXB = 5, /* Analog mux bus B */ 2322 P16_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2323 P16_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2324 P16_3_TCPWM0_LINE62 = 8, /* Digital Active - tcpwm[0].line[62]:1 */ 2325 P16_3_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:0 */ 2326 P16_3_TCPWM0_TR_ONE_CNT_IN186 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[186]:1 */ 2327 P16_3_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:0 */ 2328 P16_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:1 */ 2329 2330 /* P17.0 */ 2331 P17_0_GPIO = 0, /* GPIO controls 'out' */ 2332 P17_0_AMUXA = 4, /* Analog mux bus A */ 2333 P17_0_AMUXB = 5, /* Analog mux bus B */ 2334 P17_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2335 P17_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2336 P17_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:1 */ 2337 P17_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:1 */ 2338 P17_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:1 */ 2339 P17_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:1 */ 2340 P17_0_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:2 */ 2341 P17_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:0 */ 2342 2343 /* P17.1 */ 2344 P17_1_GPIO = 0, /* GPIO controls 'out' */ 2345 P17_1_AMUXA = 4, /* Analog mux bus A */ 2346 P17_1_AMUXB = 5, /* Analog mux bus B */ 2347 P17_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2348 P17_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2349 P17_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:1 */ 2350 P17_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:1 */ 2351 P17_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:1 */ 2352 P17_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:1 */ 2353 P17_1_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:1 */ 2354 P17_1_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:2 */ 2355 P17_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:0 */ 2356 2357 /* P17.2 */ 2358 P17_2_GPIO = 0, /* GPIO controls 'out' */ 2359 P17_2_AMUXA = 4, /* Analog mux bus A */ 2360 P17_2_AMUXB = 5, /* Analog mux bus B */ 2361 P17_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2362 P17_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2363 P17_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:1 */ 2364 P17_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:1 */ 2365 P17_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:1 */ 2366 P17_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:1 */ 2367 P17_2_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:1 */ 2368 P17_2_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:1 */ 2369 P17_2_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:2 */ 2370 2371 /* P17.3 */ 2372 P17_3_GPIO = 0, /* GPIO controls 'out' */ 2373 P17_3_AMUXA = 4, /* Analog mux bus A */ 2374 P17_3_AMUXB = 5, /* Analog mux bus B */ 2375 P17_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2376 P17_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2377 P17_3_TCPWM0_LINE58 = 8, /* Digital Active - tcpwm[0].line[58]:1 */ 2378 P17_3_TCPWM0_LINE_COMPL59 = 9, /* Digital Active - tcpwm[0].line_compl[59]:1 */ 2379 P17_3_TCPWM0_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[174]:1 */ 2380 P17_3_TCPWM0_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[178]:1 */ 2381 P17_3_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:1 */ 2382 P17_3_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:1 */ 2383 P17_3_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:1 */ 2384 P17_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:1 */ 2385 P17_3_PERI_TR_IO_INPUT26 = 26, /* Digital Active - peri.tr_io_input[26]:0 */ 2386 2387 /* P17.4 */ 2388 P17_4_GPIO = 0, /* GPIO controls 'out' */ 2389 P17_4_AMUXA = 4, /* Analog mux bus A */ 2390 P17_4_AMUXB = 5, /* Analog mux bus B */ 2391 P17_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2392 P17_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2393 P17_4_TCPWM0_LINE57 = 8, /* Digital Active - tcpwm[0].line[57]:1 */ 2394 P17_4_TCPWM0_LINE_COMPL58 = 9, /* Digital Active - tcpwm[0].line_compl[58]:1 */ 2395 P17_4_TCPWM0_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[171]:1 */ 2396 P17_4_TCPWM0_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[175]:1 */ 2397 P17_4_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:1 */ 2398 P17_4_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:1 */ 2399 P17_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:1 */ 2400 P17_4_PERI_TR_IO_INPUT27 = 26, /* Digital Active - peri.tr_io_input[27]:0 */ 2401 2402 /* P17.5 */ 2403 P17_5_GPIO = 0, /* GPIO controls 'out' */ 2404 P17_5_AMUXA = 4, /* Analog mux bus A */ 2405 P17_5_AMUXB = 5, /* Analog mux bus B */ 2406 P17_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2407 P17_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2408 P17_5_TCPWM0_LINE56 = 8, /* Digital Active - tcpwm[0].line[56]:1 */ 2409 P17_5_TCPWM0_LINE_COMPL57 = 9, /* Digital Active - tcpwm[0].line_compl[57]:1 */ 2410 P17_5_TCPWM0_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[168]:1 */ 2411 P17_5_TCPWM0_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[172]:1 */ 2412 P17_5_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:1 */ 2413 P17_5_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:0 */ 2414 P17_5_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:1 */ 2415 2416 /* P17.6 */ 2417 P17_6_GPIO = 0, /* GPIO controls 'out' */ 2418 P17_6_AMUXA = 4, /* Analog mux bus A */ 2419 P17_6_AMUXB = 5, /* Analog mux bus B */ 2420 P17_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2421 P17_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2422 P17_6_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:1 */ 2423 P17_6_TCPWM0_LINE_COMPL56 = 9, /* Digital Active - tcpwm[0].line_compl[56]:1 */ 2424 P17_6_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:1 */ 2425 P17_6_TCPWM0_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[169]:1 */ 2426 P17_6_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:1 */ 2427 P17_6_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:0 */ 2428 P17_6_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:1 */ 2429 2430 /* P17.7 */ 2431 P17_7_GPIO = 0, /* GPIO controls 'out' */ 2432 P17_7_AMUXA = 4, /* Analog mux bus A */ 2433 P17_7_AMUXB = 5, /* Analog mux bus B */ 2434 P17_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2435 P17_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2436 P17_7_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:1 */ 2437 P17_7_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ 2438 P17_7_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:1 */ 2439 P17_7_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:1 */ 2440 P17_7_LIN0_LIN_EN15 = 18, /* Digital Active - lin[0].lin_en[15]:0 */ 2441 P17_7_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:1 */ 2442 2443 /* P18.0 */ 2444 P18_0_GPIO = 0, /* GPIO controls 'out' */ 2445 P18_0_AMUXA = 4, /* Analog mux bus A */ 2446 P18_0_AMUXB = 5, /* Analog mux bus B */ 2447 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2448 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2449 P18_0_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:1 */ 2450 P18_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 2451 P18_0_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:1 */ 2452 P18_0_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:1 */ 2453 P18_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:0 */ 2454 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 2455 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 2456 P18_0_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:1 */ 2457 P18_0_ETH0_REF_CLK = 24, /* Digital Active - eth[0].ref_clk:0 */ 2458 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 2459 2460 /* P18.1 */ 2461 P18_1_GPIO = 0, /* GPIO controls 'out' */ 2462 P18_1_AMUXA = 4, /* Analog mux bus A */ 2463 P18_1_AMUXB = 5, /* Analog mux bus B */ 2464 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2465 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2466 P18_1_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:1 */ 2467 P18_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 2468 P18_1_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:1 */ 2469 P18_1_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:1 */ 2470 P18_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:0 */ 2471 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 2472 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 2473 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 2474 P18_1_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:1 */ 2475 P18_1_ETH0_TX_CTL = 24, /* Digital Active - eth[0].tx_ctl:0 */ 2476 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 2477 2478 /* P18.2 */ 2479 P18_2_GPIO = 0, /* GPIO controls 'out' */ 2480 P18_2_AMUXA = 4, /* Analog mux bus A */ 2481 P18_2_AMUXB = 5, /* Analog mux bus B */ 2482 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2483 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2484 P18_2_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:1 */ 2485 P18_2_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ 2486 P18_2_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:1 */ 2487 P18_2_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:1 */ 2488 P18_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:0 */ 2489 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 2490 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 2491 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 2492 P18_2_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:1 */ 2493 P18_2_ETH0_TX_ER = 24, /* Digital Active - eth[0].tx_er:0 */ 2494 2495 /* P18.3 */ 2496 P18_3_GPIO = 0, /* GPIO controls 'out' */ 2497 P18_3_AMUXA = 4, /* Analog mux bus A */ 2498 P18_3_AMUXB = 5, /* Analog mux bus B */ 2499 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2500 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2501 P18_3_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:1 */ 2502 P18_3_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:1 */ 2503 P18_3_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:1 */ 2504 P18_3_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:1 */ 2505 P18_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:0 */ 2506 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 2507 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 2508 P18_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:2 */ 2509 P18_3_ETH0_TX_CLK = 24, /* Digital Active - eth[0].tx_clk:0 */ 2510 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 2511 2512 /* P18.4 */ 2513 P18_4_GPIO = 0, /* GPIO controls 'out' */ 2514 P18_4_AMUXA = 4, /* Analog mux bus A */ 2515 P18_4_AMUXB = 5, /* Analog mux bus B */ 2516 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2517 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2518 P18_4_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:1 */ 2519 P18_4_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:1 */ 2520 P18_4_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:1 */ 2521 P18_4_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:1 */ 2522 P18_4_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:0 */ 2523 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 2524 P18_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:2 */ 2525 P18_4_ETH0_TXD0 = 24, /* Digital Active - eth[0].txd[0]:0 */ 2526 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 2527 2528 /* P18.5 */ 2529 P18_5_GPIO = 0, /* GPIO controls 'out' */ 2530 P18_5_AMUXA = 4, /* Analog mux bus A */ 2531 P18_5_AMUXB = 5, /* Analog mux bus B */ 2532 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2533 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2534 P18_5_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:1 */ 2535 P18_5_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:1 */ 2536 P18_5_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:1 */ 2537 P18_5_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:1 */ 2538 P18_5_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:0 */ 2539 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 2540 P18_5_ETH0_TXD1 = 24, /* Digital Active - eth[0].txd[1]:0 */ 2541 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 2542 2543 /* P18.6 */ 2544 P18_6_GPIO = 0, /* GPIO controls 'out' */ 2545 P18_6_AMUXA = 4, /* Analog mux bus A */ 2546 P18_6_AMUXB = 5, /* Analog mux bus B */ 2547 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2548 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2549 P18_6_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:1 */ 2550 P18_6_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:1 */ 2551 P18_6_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:1 */ 2552 P18_6_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:1 */ 2553 P18_6_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:0 */ 2554 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 2555 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 2556 P18_6_ETH0_TXD2 = 24, /* Digital Active - eth[0].txd[2]:0 */ 2557 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 2558 2559 /* P18.7 */ 2560 P18_7_GPIO = 0, /* GPIO controls 'out' */ 2561 P18_7_AMUXA = 4, /* Analog mux bus A */ 2562 P18_7_AMUXB = 5, /* Analog mux bus B */ 2563 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2564 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2565 P18_7_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:1 */ 2566 P18_7_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:1 */ 2567 P18_7_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:1 */ 2568 P18_7_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:1 */ 2569 P18_7_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:0 */ 2570 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 2571 P18_7_ETH0_TXD3 = 24, /* Digital Active - eth[0].txd[3]:0 */ 2572 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 2573 2574 /* P19.0 */ 2575 P19_0_GPIO = 0, /* GPIO controls 'out' */ 2576 P19_0_AMUXA = 4, /* Analog mux bus A */ 2577 P19_0_AMUXB = 5, /* Analog mux bus B */ 2578 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2579 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2580 P19_0_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:2 */ 2581 P19_0_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:1 */ 2582 P19_0_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:2 */ 2583 P19_0_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:1 */ 2584 P19_0_TCPWM0_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536]:0 */ 2585 P19_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:1 */ 2586 P19_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:1 */ 2587 P19_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:0 */ 2588 P19_0_ETH0_RXD0 = 24, /* Digital Active - eth[0].rxd[0]:0 */ 2589 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 2590 2591 /* P19.1 */ 2592 P19_1_GPIO = 0, /* GPIO controls 'out' */ 2593 P19_1_AMUXA = 4, /* Analog mux bus A */ 2594 P19_1_AMUXB = 5, /* Analog mux bus B */ 2595 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2596 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2597 P19_1_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:1 */ 2598 P19_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ 2599 P19_1_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:1 */ 2600 P19_1_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:2 */ 2601 P19_1_TCPWM0_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537]:0 */ 2602 P19_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:1 */ 2603 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 2604 P19_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:1 */ 2605 P19_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:0 */ 2606 P19_1_ETH0_RXD1 = 24, /* Digital Active - eth[0].rxd[1]:0 */ 2607 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 2608 2609 /* P19.2 */ 2610 P19_2_GPIO = 0, /* GPIO controls 'out' */ 2611 P19_2_AMUXA = 4, /* Analog mux bus A */ 2612 P19_2_AMUXB = 5, /* Analog mux bus B */ 2613 P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2614 P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2615 P19_2_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:2 */ 2616 P19_2_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:1 */ 2617 P19_2_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:2 */ 2618 P19_2_TCPWM0_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[79]:1 */ 2619 P19_2_TCPWM0_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539]:0 */ 2620 P19_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:1 */ 2621 P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ 2622 P19_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:1 */ 2623 P19_2_ETH0_RXD2 = 24, /* Digital Active - eth[0].rxd[2]:0 */ 2624 P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ 2625 2626 /* P19.3 */ 2627 P19_3_GPIO = 0, /* GPIO controls 'out' */ 2628 P19_3_AMUXA = 4, /* Analog mux bus A */ 2629 P19_3_AMUXB = 5, /* Analog mux bus B */ 2630 P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2631 P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2632 P19_3_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:2 */ 2633 P19_3_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:2 */ 2634 P19_3_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:2 */ 2635 P19_3_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:2 */ 2636 P19_3_TCPWM0_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540]:0 */ 2637 P19_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:1 */ 2638 P19_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:1 */ 2639 P19_3_ETH0_RXD3 = 24, /* Digital Active - eth[0].rxd[3]:0 */ 2640 P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ 2641 2642 /* P19.4 */ 2643 P19_4_GPIO = 0, /* GPIO controls 'out' */ 2644 P19_4_AMUXA = 4, /* Analog mux bus A */ 2645 P19_4_AMUXB = 5, /* Analog mux bus B */ 2646 P19_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2647 P19_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2648 P19_4_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:2 */ 2649 P19_4_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:2 */ 2650 P19_4_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:2 */ 2651 P19_4_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:2 */ 2652 P19_4_TCPWM0_TR_ONE_CNT_IN1542 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1542]:0 */ 2653 P19_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:1 */ 2654 2655 /* P20.0 */ 2656 P20_0_GPIO = 0, /* GPIO controls 'out' */ 2657 P20_0_AMUXA = 4, /* Analog mux bus A */ 2658 P20_0_AMUXB = 5, /* Analog mux bus B */ 2659 P20_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2660 P20_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2661 P20_0_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:2 */ 2662 P20_0_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:2 */ 2663 P20_0_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:2 */ 2664 P20_0_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:2 */ 2665 P20_0_TCPWM0_TR_ONE_CNT_IN1543 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1543]:0 */ 2666 P20_0_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:1 */ 2667 P20_0_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:0 */ 2668 2669 /* P20.1 */ 2670 P20_1_GPIO = 0, /* GPIO controls 'out' */ 2671 P20_1_AMUXA = 4, /* Analog mux bus A */ 2672 P20_1_AMUXB = 5, /* Analog mux bus B */ 2673 P20_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2674 P20_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2675 P20_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:1 */ 2676 P20_1_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:2 */ 2677 P20_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:1 */ 2678 P20_1_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:2 */ 2679 P20_1_TCPWM0_TR_ONE_CNT_IN1545 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1545]:0 */ 2680 P20_1_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:0 */ 2681 2682 /* P20.2 */ 2683 P20_2_GPIO = 0, /* GPIO controls 'out' */ 2684 P20_2_AMUXA = 4, /* Analog mux bus A */ 2685 P20_2_AMUXB = 5, /* Analog mux bus B */ 2686 P20_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2687 P20_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2688 P20_2_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:1 */ 2689 P20_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:1 */ 2690 P20_2_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:1 */ 2691 P20_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:1 */ 2692 P20_2_TCPWM0_TR_ONE_CNT_IN1546 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1546]:0 */ 2693 P20_2_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:0 */ 2694 2695 /* P20.3 */ 2696 P20_3_GPIO = 0, /* GPIO controls 'out' */ 2697 P20_3_AMUXA = 4, /* Analog mux bus A */ 2698 P20_3_AMUXB = 5, /* Analog mux bus B */ 2699 P20_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2700 P20_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2701 P20_3_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:1 */ 2702 P20_3_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:1 */ 2703 P20_3_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:1 */ 2704 P20_3_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:1 */ 2705 P20_3_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:1 */ 2706 P20_3_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:1 */ 2707 P20_3_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:1 */ 2708 2709 /* P20.4 */ 2710 P20_4_GPIO = 0, /* GPIO controls 'out' */ 2711 P20_4_AMUXA = 4, /* Analog mux bus A */ 2712 P20_4_AMUXB = 5, /* Analog mux bus B */ 2713 P20_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2714 P20_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2715 P20_4_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:1 */ 2716 P20_4_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:1 */ 2717 P20_4_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:1 */ 2718 P20_4_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:1 */ 2719 P20_4_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:1 */ 2720 P20_4_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:1 */ 2721 P20_4_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:1 */ 2722 P20_4_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:1 */ 2723 2724 /* P20.5 */ 2725 P20_5_GPIO = 0, /* GPIO controls 'out' */ 2726 P20_5_AMUXA = 4, /* Analog mux bus A */ 2727 P20_5_AMUXB = 5, /* Analog mux bus B */ 2728 P20_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2729 P20_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2730 P20_5_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:1 */ 2731 P20_5_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:1 */ 2732 P20_5_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:1 */ 2733 P20_5_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:1 */ 2734 P20_5_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:1 */ 2735 P20_5_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:1 */ 2736 P20_5_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:1 */ 2737 2738 /* P20.6 */ 2739 P20_6_GPIO = 0, /* GPIO controls 'out' */ 2740 P20_6_AMUXA = 4, /* Analog mux bus A */ 2741 P20_6_AMUXB = 5, /* Analog mux bus B */ 2742 P20_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2743 P20_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2744 P20_6_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:1 */ 2745 P20_6_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:1 */ 2746 P20_6_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:1 */ 2747 P20_6_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:1 */ 2748 P20_6_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:1 */ 2749 P20_6_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:1 */ 2750 2751 /* P20.7 */ 2752 P20_7_GPIO = 0, /* GPIO controls 'out' */ 2753 P20_7_AMUXA = 4, /* Analog mux bus A */ 2754 P20_7_AMUXB = 5, /* Analog mux bus B */ 2755 P20_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2756 P20_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2757 P20_7_TCPWM0_LINE43 = 8, /* Digital Active - tcpwm[0].line[43]:1 */ 2758 P20_7_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:1 */ 2759 P20_7_TCPWM0_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[129]:1 */ 2760 P20_7_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:1 */ 2761 P20_7_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:1 */ 2762 2763 /* P21.0 */ 2764 P21_0_GPIO = 0, /* GPIO controls 'out' */ 2765 P21_0_AMUXA = 4, /* Analog mux bus A */ 2766 P21_0_AMUXB = 5, /* Analog mux bus B */ 2767 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2768 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2769 P21_0_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:1 */ 2770 P21_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:1 */ 2771 P21_0_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:1 */ 2772 P21_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:1 */ 2773 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 2774 2775 /* P21.1 */ 2776 P21_1_GPIO = 0, /* GPIO controls 'out' */ 2777 P21_1_AMUXA = 4, /* Analog mux bus A */ 2778 P21_1_AMUXB = 5, /* Analog mux bus B */ 2779 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2780 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2781 P21_1_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:1 */ 2782 P21_1_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:1 */ 2783 P21_1_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:1 */ 2784 P21_1_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:1 */ 2785 2786 /* P21.2 */ 2787 P21_2_GPIO = 0, /* GPIO controls 'out' */ 2788 P21_2_AMUXA = 4, /* Analog mux bus A */ 2789 P21_2_AMUXB = 5, /* Analog mux bus B */ 2790 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2791 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2792 P21_2_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:1 */ 2793 P21_2_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:1 */ 2794 P21_2_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:1 */ 2795 P21_2_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:1 */ 2796 P21_2_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:0 */ 2797 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 2798 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 2799 2800 /* P21.3 */ 2801 P21_3_GPIO = 0, /* GPIO controls 'out' */ 2802 P21_3_AMUXA = 4, /* Analog mux bus A */ 2803 P21_3_AMUXB = 5, /* Analog mux bus B */ 2804 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2805 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2806 P21_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:1 */ 2807 P21_3_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:1 */ 2808 P21_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:1 */ 2809 P21_3_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:1 */ 2810 2811 /* P21.4 */ 2812 P21_4_GPIO = 0, /* GPIO controls 'out' */ 2813 P21_4_AMUXA = 4, /* Analog mux bus A */ 2814 P21_4_AMUXB = 5, /* Analog mux bus B */ 2815 P21_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2816 P21_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2817 P21_4_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:1 */ 2818 P21_4_TCPWM0_LINE_COMPL39 = 9, /* Digital Active - tcpwm[0].line_compl[39]:1 */ 2819 P21_4_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:1 */ 2820 P21_4_TCPWM0_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[118]:1 */ 2821 2822 /* P21.5 */ 2823 P21_5_GPIO = 0, /* GPIO controls 'out' */ 2824 P21_5_AMUXA = 4, /* Analog mux bus A */ 2825 P21_5_AMUXB = 5, /* Analog mux bus B */ 2826 P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2827 P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2828 P21_5_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:1 */ 2829 P21_5_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:1 */ 2830 P21_5_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:1 */ 2831 P21_5_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:1 */ 2832 P21_5_TCPWM0_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:1 */ 2833 P21_5_TCPWM0_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:1 */ 2834 P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ 2835 P21_5_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 2836 P21_5_TCPWM0_LINE34 = 22, /* Digital Active - tcpwm[0].line[34]:1 */ 2837 P21_5_TCPWM0_LINE_COMPL35 = 23, /* Digital Active - tcpwm[0].line_compl[35]:1 */ 2838 P21_5_ETH0_RX_CTL = 24, /* Digital Active - eth[0].rx_ctl:0 */ 2839 P21_5_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 2840 2841 /* P21.6 */ 2842 P21_6_GPIO = 0, /* GPIO controls 'out' */ 2843 P21_6_AMUXA = 4, /* Analog mux bus A */ 2844 P21_6_AMUXB = 5, /* Analog mux bus B */ 2845 P21_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2846 P21_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2847 P21_6_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:1 */ 2848 P21_6_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:1 */ 2849 P21_6_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:1 */ 2850 P21_6_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:1 */ 2851 P21_6_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:1 */ 2852 P21_6_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:1 */ 2853 P21_6_CPUSS_CLK_FM_PUMP = 26, /* Digital Active - cpuss.clk_fm_pump */ 2854 2855 /* P21.7 */ 2856 P21_7_GPIO = 0, /* GPIO controls 'out' */ 2857 P21_7_AMUXA = 4, /* Analog mux bus A */ 2858 P21_7_AMUXB = 5, /* Analog mux bus B */ 2859 P21_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2860 P21_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2861 P21_7_TCPWM0_LINE35 = 8, /* Digital Active - tcpwm[0].line[35]:1 */ 2862 P21_7_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:1 */ 2863 P21_7_TCPWM0_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[105]:1 */ 2864 P21_7_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:1 */ 2865 P21_7_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ 2866 P21_7_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ 2867 P21_7_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:1 */ 2868 P21_7_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:1 */ 2869 P21_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:1 */ 2870 P21_7_SRSS_CAL_WAVE = 29, /* Digital Deep Sleep - srss.cal_wave:0 */ 2871 2872 /* P22.1 */ 2873 P22_1_GPIO = 0, /* GPIO controls 'out' */ 2874 P22_1_AMUXA = 4, /* Analog mux bus A */ 2875 P22_1_AMUXB = 5, /* Analog mux bus B */ 2876 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2877 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2878 P22_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:1 */ 2879 P22_1_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:1 */ 2880 P22_1_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:1 */ 2881 P22_1_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:1 */ 2882 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 2883 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 2884 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 2885 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 2886 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 2887 2888 /* P22.2 */ 2889 P22_2_GPIO = 0, /* GPIO controls 'out' */ 2890 P22_2_AMUXA = 4, /* Analog mux bus A */ 2891 P22_2_AMUXB = 5, /* Analog mux bus B */ 2892 P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2893 P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2894 P22_2_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:1 */ 2895 P22_2_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:1 */ 2896 P22_2_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:1 */ 2897 P22_2_TCPWM0_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[100]:1 */ 2898 P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ 2899 P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ 2900 P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ 2901 P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 2902 2903 /* P22.3 */ 2904 P22_3_GPIO = 0, /* GPIO controls 'out' */ 2905 P22_3_AMUXA = 4, /* Analog mux bus A */ 2906 P22_3_AMUXB = 5, /* Analog mux bus B */ 2907 P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2908 P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2909 P22_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:1 */ 2910 P22_3_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:1 */ 2911 P22_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:1 */ 2912 P22_3_TCPWM0_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[97]:1 */ 2913 P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ 2914 P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ 2915 P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 2916 2917 /* P22.4 */ 2918 P22_4_GPIO = 0, /* GPIO controls 'out' */ 2919 P22_4_AMUXA = 4, /* Analog mux bus A */ 2920 P22_4_AMUXB = 5, /* Analog mux bus B */ 2921 P22_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2922 P22_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2923 P22_4_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:1 */ 2924 P22_4_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:1 */ 2925 P22_4_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:1 */ 2926 P22_4_TCPWM0_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[94]:1 */ 2927 P22_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:1 */ 2928 P22_4_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:1 */ 2929 2930 /* P22.5 */ 2931 P22_5_GPIO = 0, /* GPIO controls 'out' */ 2932 P22_5_AMUXA = 4, /* Analog mux bus A */ 2933 P22_5_AMUXB = 5, /* Analog mux bus B */ 2934 P22_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2935 P22_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2936 P22_5_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:1 */ 2937 P22_5_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:1 */ 2938 P22_5_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:1 */ 2939 P22_5_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:1 */ 2940 P22_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:1 */ 2941 P22_5_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:1 */ 2942 2943 /* P22.6 */ 2944 P22_6_GPIO = 0, /* GPIO controls 'out' */ 2945 P22_6_AMUXA = 4, /* Analog mux bus A */ 2946 P22_6_AMUXB = 5, /* Analog mux bus B */ 2947 P22_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2948 P22_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2949 P22_6_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:1 */ 2950 P22_6_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:1 */ 2951 P22_6_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:1 */ 2952 P22_6_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:1 */ 2953 P22_6_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:1 */ 2954 2955 /* P22.7 */ 2956 P22_7_GPIO = 0, /* GPIO controls 'out' */ 2957 P22_7_AMUXA = 4, /* Analog mux bus A */ 2958 P22_7_AMUXB = 5, /* Analog mux bus B */ 2959 P22_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2960 P22_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2961 P22_7_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:1 */ 2962 P22_7_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:1 */ 2963 P22_7_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:1 */ 2964 P22_7_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:1 */ 2965 P22_7_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:1 */ 2966 P22_7_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:1 */ 2967 2968 /* P23.0 */ 2969 P23_0_GPIO = 0, /* GPIO controls 'out' */ 2970 P23_0_AMUXA = 4, /* Analog mux bus A */ 2971 P23_0_AMUXB = 5, /* Analog mux bus B */ 2972 P23_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2973 P23_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2974 P23_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:1 */ 2975 P23_0_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:1 */ 2976 P23_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:1 */ 2977 P23_0_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:1 */ 2978 P23_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:1 */ 2979 P23_0_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:1 */ 2980 P23_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:1 */ 2981 P23_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:1 */ 2982 P23_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:1 */ 2983 2984 /* P23.1 */ 2985 P23_1_GPIO = 0, /* GPIO controls 'out' */ 2986 P23_1_AMUXA = 4, /* Analog mux bus A */ 2987 P23_1_AMUXB = 5, /* Analog mux bus B */ 2988 P23_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2989 P23_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2990 P23_1_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:1 */ 2991 P23_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:1 */ 2992 P23_1_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:1 */ 2993 P23_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:1 */ 2994 P23_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:1 */ 2995 P23_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:1 */ 2996 P23_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:1 */ 2997 P23_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:1 */ 2998 P23_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:1 */ 2999 3000 /* P23.2 */ 3001 P23_2_GPIO = 0, /* GPIO controls 'out' */ 3002 P23_2_AMUXA = 4, /* Analog mux bus A */ 3003 P23_2_AMUXB = 5, /* Analog mux bus B */ 3004 P23_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3005 P23_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3006 P23_2_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:1 */ 3007 P23_2_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:1 */ 3008 P23_2_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:1 */ 3009 P23_2_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:1 */ 3010 P23_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:1 */ 3011 P23_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:1 */ 3012 P23_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:1 */ 3013 P23_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:2 */ 3014 P23_2_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:1 */ 3015 3016 /* P23.3 */ 3017 P23_3_GPIO = 0, /* GPIO controls 'out' */ 3018 P23_3_AMUXA = 4, /* Analog mux bus A */ 3019 P23_3_AMUXB = 5, /* Analog mux bus B */ 3020 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3021 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3022 P23_3_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:1 */ 3023 P23_3_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:1 */ 3024 P23_3_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:1 */ 3025 P23_3_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:1 */ 3026 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 3027 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 3028 P23_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:2 */ 3029 P23_3_ETH0_RX_CLK = 24, /* Digital Active - eth[0].rx_clk:0 */ 3030 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 3031 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 3032 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 3033 3034 /* P23.4 */ 3035 P23_4_GPIO = 0, /* GPIO controls 'out' */ 3036 P23_4_AMUXA = 4, /* Analog mux bus A */ 3037 P23_4_AMUXB = 5, /* Analog mux bus B */ 3038 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3039 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3040 P23_4_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ 3041 P23_4_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:1 */ 3042 P23_4_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:1 */ 3043 P23_4_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:1 */ 3044 P23_4_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:2 */ 3045 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 3046 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 3047 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 3048 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 3049 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 3050 3051 /* P23.5 */ 3052 P23_5_GPIO = 0, /* GPIO controls 'out' */ 3053 P23_5_AMUXA = 4, /* Analog mux bus A */ 3054 P23_5_AMUXB = 5, /* Analog mux bus B */ 3055 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3056 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3057 P23_5_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ 3058 P23_5_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ 3059 P23_5_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:1 */ 3060 P23_5_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:1 */ 3061 P23_5_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:2 */ 3062 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 3063 P23_5_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:0 */ 3064 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 3065 3066 /* P23.6 */ 3067 P23_6_GPIO = 0, /* GPIO controls 'out' */ 3068 P23_6_AMUXA = 4, /* Analog mux bus A */ 3069 P23_6_AMUXB = 5, /* Analog mux bus B */ 3070 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3071 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3072 P23_6_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ 3073 P23_6_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ 3074 P23_6_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:1 */ 3075 P23_6_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:1 */ 3076 P23_6_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:2 */ 3077 P23_6_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:0 */ 3078 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 3079 3080 /* P23.7 */ 3081 P23_7_GPIO = 0, /* GPIO controls 'out' */ 3082 P23_7_AMUXA = 4, /* Analog mux bus A */ 3083 P23_7_AMUXB = 5, /* Analog mux bus B */ 3084 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3085 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3086 P23_7_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ 3087 P23_7_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ 3088 P23_7_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:1 */ 3089 P23_7_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:1 */ 3090 P23_7_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:2 */ 3091 P23_7_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:1 */ 3092 P23_7_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:0 */ 3093 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 3094 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 3095 P23_7_SRSS_DDFT_PIN_IN0 = 31 /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 3096 } en_hsiom_sel_t; 3097 3098 #endif /* _GPIO_XMC7100_176_TEQFP_H_ */ 3099 3100 3101 /* [] END OF FILE */ 3102
