1 /*
2 * Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT xlnx_xps_gpio_1_00_a
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/sys/sys_io.h>
13
14 #include <zephyr/drivers/gpio/gpio_utils.h>
15
16 /* AXI GPIO v2 register offsets (See Xilinx PG144 for details) */
17 #define GPIO_DATA_OFFSET 0x0000
18 #define GPIO_TRI_OFFSET 0x0004
19 #define GPIO2_OFFSET 0x0008
20 #define GPIO2_DATA_OFFSET 0x0008
21 #define GPIO2_TRI_OFFSET 0x000c
22 #define GIER_OFFSET 0x011c
23 #define IPISR_OFFSET 0x0120
24 #define IPIER_OFFSET 0x0128
25
26 /* GIER bit definitions */
27 #define GIER_GIE BIT(31)
28
29 /* IPISR and IPIER bit definitions */
30 #define IPIXX_CH1_IE BIT(0)
31 #define IPIXX_CH2_IE BIT(1)
32
33 /* Maximum number of GPIOs supported per channel */
34 #define MAX_GPIOS 32
35
36 struct gpio_xlnx_axi_config {
37 /* gpio_driver_config needs to be first */
38 struct gpio_driver_config common;
39 mm_reg_t base;
40 uint8_t channel;
41 bool all_inputs: 1;
42 bool all_outputs: 1;
43 bool interrupts_available: 1;
44 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
45 void (*irq_config_func)(const struct device *dev);
46 #endif
47 };
48
49 struct gpio_xlnx_axi_data {
50 /* gpio_driver_data needs to be first */
51 struct gpio_driver_data common;
52 /* Shadow registers for data out and tristate */
53 uint32_t dout;
54 uint32_t tri;
55 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
56 uint32_t previous_data_reading;
57 sys_slist_t callbacks;
58 uint32_t rising_edge_interrupts;
59 uint32_t falling_edge_interrupts;
60 /* Workaround to handle channel 2 interrupts from channel 1*/
61 const struct device *other_channel_device;
62 #endif
63 };
64
gpio_xlnx_axi_read_data(const struct device * dev)65 static inline uint32_t gpio_xlnx_axi_read_data(const struct device *dev)
66 {
67 const struct gpio_xlnx_axi_config *config = dev->config;
68
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET);
70 }
71
gpio_xlnx_axi_write_data(const struct device * dev,uint32_t val)72 static inline void gpio_xlnx_axi_write_data(const struct device *dev, uint32_t val)
73 {
74 const struct gpio_xlnx_axi_config *config = dev->config;
75
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET);
77 }
78
gpio_xlnx_axi_write_tri(const struct device * dev,uint32_t val)79 static inline void gpio_xlnx_axi_write_tri(const struct device *dev, uint32_t val)
80 {
81 const struct gpio_xlnx_axi_config *config = dev->config;
82
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET);
84 }
85
gpio_xlnx_axi_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)86 static int gpio_xlnx_axi_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
87 {
88 const struct gpio_xlnx_axi_config *config = dev->config;
89 struct gpio_xlnx_axi_data *data = dev->data;
90 unsigned int key;
91
92 if (!(BIT(pin) & config->common.port_pin_mask)) {
93 return -EINVAL;
94 }
95
96 if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
97 return -ENOTSUP;
98 }
99
100 if ((flags & GPIO_SINGLE_ENDED) != 0) {
101 return -ENOTSUP;
102 }
103
104 if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
105 return -ENOTSUP;
106 }
107
108 if (((flags & GPIO_INPUT) != 0) && config->all_outputs) {
109 return -ENOTSUP;
110 }
111
112 if (((flags & GPIO_OUTPUT) != 0) && config->all_inputs) {
113 return -ENOTSUP;
114 }
115
116 key = irq_lock();
117
118 switch (flags & GPIO_DIR_MASK) {
119 case GPIO_INPUT:
120 data->tri |= BIT(pin);
121 break;
122 case GPIO_OUTPUT:
123 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
124 data->dout |= BIT(pin);
125 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
126 data->dout &= ~BIT(pin);
127 }
128 data->tri &= ~BIT(pin);
129 break;
130 default:
131 return -ENOTSUP;
132 }
133
134 gpio_xlnx_axi_write_data(dev, data->dout);
135 gpio_xlnx_axi_write_tri(dev, data->tri);
136
137 irq_unlock(key);
138
139 return 0;
140 }
141
gpio_xlnx_axi_port_get_raw(const struct device * dev,gpio_port_value_t * value)142 static int gpio_xlnx_axi_port_get_raw(const struct device *dev, gpio_port_value_t *value)
143 {
144 *value = gpio_xlnx_axi_read_data(dev);
145 return 0;
146 }
147
gpio_xlnx_axi_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)148 static int gpio_xlnx_axi_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
149 gpio_port_value_t value)
150 {
151 struct gpio_xlnx_axi_data *data = dev->data;
152 unsigned int key;
153
154 key = irq_lock();
155 data->dout = (data->dout & ~mask) | (mask & value);
156 gpio_xlnx_axi_write_data(dev, data->dout);
157 irq_unlock(key);
158
159 return 0;
160 }
161
gpio_xlnx_axi_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)162 static int gpio_xlnx_axi_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
163 {
164 struct gpio_xlnx_axi_data *data = dev->data;
165 unsigned int key;
166
167 key = irq_lock();
168 data->dout |= pins;
169 gpio_xlnx_axi_write_data(dev, data->dout);
170 irq_unlock(key);
171
172 return 0;
173 }
174
gpio_xlnx_axi_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)175 static int gpio_xlnx_axi_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
176 {
177 struct gpio_xlnx_axi_data *data = dev->data;
178 unsigned int key;
179
180 key = irq_lock();
181 data->dout &= ~pins;
182 gpio_xlnx_axi_write_data(dev, data->dout);
183 irq_unlock(key);
184
185 return 0;
186 }
187
gpio_xlnx_axi_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)188 static int gpio_xlnx_axi_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
189 {
190 struct gpio_xlnx_axi_data *data = dev->data;
191 unsigned int key;
192
193 key = irq_lock();
194 data->dout ^= pins;
195 gpio_xlnx_axi_write_data(dev, data->dout);
196 irq_unlock(key);
197
198 return 0;
199 }
200
201 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
202 /**
203 * Enables interrupts for the given pins on the channel
204 * The axi gpio can only enable interrupts for an entire port, so we need to track
205 * the pins and modes ourselves.
206 */
gpio_xlnx_axi_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)207 static int gpio_xlnx_axi_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
208 enum gpio_int_mode mode, enum gpio_int_trig trig)
209 {
210 const struct gpio_xlnx_axi_config *config = dev->config;
211 struct gpio_xlnx_axi_data *data = dev->data;
212 const uint32_t pin_mask = BIT(pin);
213 const uint32_t chan_mask = BIT(config->channel);
214 unsigned int key;
215 uint32_t enabled_interrupts;
216
217 if (!config->interrupts_available) {
218 return -ENOTSUP;
219 }
220
221 if ((mode & GPIO_INT_ENABLE) && !(mode & GPIO_INT_EDGE)) {
222 /* only edge detection is supported */
223 return -ENOTSUP;
224 }
225
226 key = irq_lock();
227
228 data->rising_edge_interrupts &= ~pin_mask;
229 data->falling_edge_interrupts &= ~pin_mask;
230
231 if (mode & GPIO_INT_ENABLE) {
232 if (trig & GPIO_INT_HIGH_1) {
233 data->rising_edge_interrupts |= pin_mask;
234 }
235 if (trig & GPIO_INT_LOW_0) {
236 data->falling_edge_interrupts |= pin_mask;
237 }
238 }
239
240 /* if there's at least one pin interrupt enabled on the channel, enable the interrupts
241 * for that entire channel without changing the other channel
242 */
243 enabled_interrupts = sys_read32(config->base + IPIER_OFFSET);
244 if (data->rising_edge_interrupts || data->falling_edge_interrupts) {
245 if (!(enabled_interrupts & chan_mask)) {
246 /* Clear any pending interrupts and update last state before enabling
247 * interrupt
248 */
249 if (sys_read32(config->base + IPISR_OFFSET) & chan_mask) {
250 sys_write32(chan_mask, config->base + IPISR_OFFSET);
251 }
252 data->previous_data_reading = gpio_xlnx_axi_read_data(dev);
253
254 enabled_interrupts |= chan_mask;
255 }
256 } else {
257 enabled_interrupts &= ~chan_mask;
258 }
259 sys_write32(enabled_interrupts, config->base + IPIER_OFFSET);
260
261 irq_unlock(key);
262 return 0;
263 #else
264 ARG_UNUSED(dev);
265 ARG_UNUSED(pin);
266 ARG_UNUSED(mode);
267 ARG_UNUSED(trig);
268
269 return -ENOTSUP;
270 #endif
271 }
272
gpio_xlnx_axi_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)273 static int gpio_xlnx_axi_manage_callback(const struct device *dev, struct gpio_callback *callback,
274 bool set)
275 {
276 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
277 struct gpio_xlnx_axi_data *data = dev->data;
278
279 return gpio_manage_callback(&data->callbacks, callback, set);
280 #else
281 ARG_UNUSED(dev);
282 ARG_UNUSED(callback);
283 ARG_UNUSED(set);
284
285 return -ENOTSUP;
286 #endif
287 }
288
289 /**
290 * Returns the pins on this devices channel which changed and also have an interrupt enabled on that
291 * pin. Also clears the pending interrupt for that channel.
292 */
gpio_xlnx_axi_get_pending_int(const struct device * dev)293 static uint32_t gpio_xlnx_axi_get_pending_int(const struct device *dev)
294 {
295 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
296 const struct gpio_xlnx_axi_config *config = dev->config;
297 struct gpio_xlnx_axi_data *data = dev->data;
298 const uint32_t chan_mask = BIT(config->channel);
299 unsigned int key;
300 uint32_t interrupt_flags;
301 uint32_t current_data;
302 uint32_t changed_pins;
303 uint32_t changed_and_rising_edge;
304 uint32_t changed_and_falling_edge;
305 uint32_t interrupts;
306
307 key = irq_lock();
308
309 /* make sure interrupt was for this channel */
310 interrupt_flags = sys_read32(config->base + IPISR_OFFSET);
311
312 if (!(interrupt_flags & chan_mask)) {
313 irq_unlock(key);
314 return 0;
315 }
316
317 /* clear pending interrupt for the whole channel */
318 sys_write32(chan_mask, config->base + IPISR_OFFSET);
319
320 /* find which pins changed and also have an interrupt enabled */
321 current_data = gpio_xlnx_axi_read_data(dev);
322 changed_pins = current_data ^ data->previous_data_reading;
323 data->previous_data_reading = current_data;
324 changed_and_rising_edge = (changed_pins & current_data);
325 changed_and_falling_edge = (changed_pins & ~current_data);
326 interrupts = (changed_and_rising_edge & data->rising_edge_interrupts) |
327 (changed_and_falling_edge & data->falling_edge_interrupts);
328
329 irq_unlock(key);
330 return interrupts;
331 #else
332 ARG_UNUSED(dev);
333
334 return 0;
335 #endif
336 }
337
338 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
gpio_xlnx_axi_isr(const struct device * dev)339 static void gpio_xlnx_axi_isr(const struct device *dev)
340 {
341 struct gpio_xlnx_axi_data *data = dev->data;
342
343 gpio_fire_callbacks(&data->callbacks, dev, gpio_xlnx_axi_get_pending_int(dev));
344
345 /* Since both channels use the same interrupt, only the first channel registers the ISR.
346 * If the second channel is also enabled, then check for any events on it as well.
347 */
348 if (data->other_channel_device) {
349 struct gpio_xlnx_axi_data *other_data = data->other_channel_device->data;
350
351 gpio_fire_callbacks(&other_data->callbacks, data->other_channel_device,
352 gpio_xlnx_axi_get_pending_int(data->other_channel_device));
353 }
354 }
355 #endif
356
gpio_xlnx_axi_init(const struct device * dev)357 static int gpio_xlnx_axi_init(const struct device *dev)
358 {
359 struct gpio_xlnx_axi_data *data = dev->data;
360
361 gpio_xlnx_axi_write_data(dev, data->dout);
362 gpio_xlnx_axi_write_tri(dev, data->tri);
363
364 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
365 const struct gpio_xlnx_axi_config *config = dev->config;
366
367 if (config->irq_config_func != NULL) {
368 /* Note: This is only called for the first channel, even if the second is enabled.
369 * Need to perform the setup for both channels.
370 * Disable all interrupts.
371 */
372 sys_write32(0x0, config->base + IPIER_OFFSET);
373
374 /* Clear all pending interrupts */
375 sys_write32(sys_read32(config->base + IPISR_OFFSET), config->base + IPISR_OFFSET);
376
377 /* Enable global interrupts for this gpio device */
378 sys_write32(GIER_GIE, config->base + GIER_OFFSET);
379
380 config->irq_config_func(dev);
381 }
382 #endif
383 return 0;
384 }
385
386 static const struct gpio_driver_api gpio_xlnx_axi_driver_api = {
387 .pin_configure = gpio_xlnx_axi_pin_configure,
388 .port_get_raw = gpio_xlnx_axi_port_get_raw,
389 .port_set_masked_raw = gpio_xlnx_axi_port_set_masked_raw,
390 .port_set_bits_raw = gpio_xlnx_axi_port_set_bits_raw,
391 .port_clear_bits_raw = gpio_xlnx_axi_port_clear_bits_raw,
392 .port_toggle_bits = gpio_xlnx_axi_port_toggle_bits,
393 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
394 .pin_interrupt_configure = gpio_xlnx_axi_pin_interrupt_configure,
395 .manage_callback = gpio_xlnx_axi_manage_callback,
396 .get_pending_int = gpio_xlnx_axi_get_pending_int,
397 #endif
398 };
399
400 #define GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n) \
401 UTIL_AND(DT_NODE_HAS_COMPAT(DT_INST_CHILD(n, gpio2), xlnx_xps_gpio_1_00_a_gpio2), \
402 DT_NODE_HAS_STATUS(DT_INST_CHILD(n, gpio2), okay))
403
404 #define GPIO_XLNX_AXI_GPIO2_COND_INIT(n) \
405 IF_ENABLED(UTIL_AND(DT_INST_PROP_OR(n, xlnx_is_dual, 1), \
406 GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n)), \
407 (GPIO_XLNX_AXI_GPIO2_INIT(n)));
408
409 #define GPIO_XLNX_AXI_GPIO2_INIT(n) \
410 static struct gpio_xlnx_axi_data gpio_xlnx_axi_##n##_2_data = { \
411 .dout = DT_INST_PROP_OR(n, xlnx_dout_default_2, 0), \
412 .tri = DT_INST_PROP_OR(n, xlnx_tri_default_2, GENMASK(MAX_GPIOS - 1, 0)), \
413 }; \
414 \
415 static const struct gpio_xlnx_axi_config gpio_xlnx_axi_##n##_2_config = { \
416 .common = \
417 { \
418 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS( \
419 DT_INST_PROP_OR(n, xlnx_gpio2_width, MAX_GPIOS)), \
420 }, \
421 .base = DT_INST_REG_ADDR(n), \
422 .channel = 1, \
423 .all_inputs = DT_INST_PROP_OR(n, xlnx_all_inputs_2, 0), \
424 .all_outputs = DT_INST_PROP_OR(n, xlnx_all_outputs_2, 0), \
425 .interrupts_available = DT_INST_NODE_HAS_PROP(n, interrupts)}; \
426 \
427 DEVICE_DT_DEFINE(DT_INST_CHILD(n, gpio2), &gpio_xlnx_axi_init, NULL, \
428 &gpio_xlnx_axi_##n##_2_data, &gpio_xlnx_axi_##n##_2_config, PRE_KERNEL_1, \
429 CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_axi_driver_api);
430
431 #define GPIO_XLNX_AXI_INIT(n) \
432 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, interrupts), \
433 (static void gpio_xlnx_axi_##n##_irq_config(const struct device *dev);)) \
434 \
435 GPIO_XLNX_AXI_GPIO2_COND_INIT(n); \
436 \
437 static struct gpio_xlnx_axi_data gpio_xlnx_axi_##n##_data = { \
438 .dout = DT_INST_PROP_OR(n, xlnx_dout_default, 0), \
439 .tri = DT_INST_PROP_OR(n, xlnx_tri_default, GENMASK(MAX_GPIOS - 1, 0)), \
440 IF_ENABLED(UTIL_AND(UTIL_AND(DT_INST_NODE_HAS_PROP(n, interrupts), \
441 DT_INST_PROP_OR(n, xlnx_is_dual, 1)), \
442 GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n)), \
443 (.other_channel_device = DEVICE_DT_GET(DT_INST_CHILD(n, gpio2))))}; \
444 \
445 static const struct gpio_xlnx_axi_config gpio_xlnx_axi_##n##_config = { \
446 .common = \
447 { \
448 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS( \
449 DT_INST_PROP_OR(n, xlnx_gpio_width, MAX_GPIOS)), \
450 }, \
451 .base = DT_INST_REG_ADDR(n), \
452 .channel = 0, \
453 .all_inputs = DT_INST_PROP_OR(n, xlnx_all_inputs, 0), \
454 .all_outputs = DT_INST_PROP_OR(n, xlnx_all_outputs, 0), \
455 .interrupts_available = DT_INST_NODE_HAS_PROP(n, interrupts), \
456 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, interrupts), \
457 (.irq_config_func = gpio_xlnx_axi_##n##_irq_config))}; \
458 \
459 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, interrupts), \
460 (static void gpio_xlnx_axi_##n##_irq_config(const struct device *dev) \
461 { \
462 ARG_UNUSED(dev); \
463 \
464 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
465 gpio_xlnx_axi_isr, DEVICE_DT_INST_GET(n), 0); \
466 \
467 irq_enable(DT_INST_IRQN(n)); \
468 })) \
469 \
470 DEVICE_DT_INST_DEFINE(n, &gpio_xlnx_axi_init, NULL, &gpio_xlnx_axi_##n##_data, \
471 &gpio_xlnx_axi_##n##_config, PRE_KERNEL_1, \
472 CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_axi_driver_api);
473
474 DT_INST_FOREACH_STATUS_OKAY(GPIO_XLNX_AXI_INIT)
475
