1 /***************************************************************************//** 2 * \file gpio_tviibe4m_64_lqfp.h 3 * 4 * \brief 5 * TVIIBE4M device GPIO header for 64-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_TVIIBE4M_64_LQFP_H_ 28 #define _GPIO_TVIIBE4M_64_LQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_LQFP 44 #define CY_GPIO_PIN_COUNT 64u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_EFUSE, 50 AMUXBUS_MAIN, 51 AMUXBUS_TEST, 52 AMUXBUS_TESTECT, 53 AMUXBUS_TESTSRSS, 54 }; 55 56 /* AMUX Splitter Controls */ 57 typedef enum 58 { 59 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_EFUSE */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 0 (GPIO) */ 66 #define P0_0_PORT GPIO_PRT0 67 #define P0_0_PIN 0u 68 #define P0_0_NUM 0u 69 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 70 #define P0_1_PORT GPIO_PRT0 71 #define P0_1_PIN 1u 72 #define P0_1_NUM 1u 73 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 78 #define P0_3_PORT GPIO_PRT0 79 #define P0_3_PIN 3u 80 #define P0_3_NUM 3u 81 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 82 83 /* PORT 2 (GPIO) */ 84 #define P2_0_PORT GPIO_PRT2 85 #define P2_0_PIN 0u 86 #define P2_0_NUM 0u 87 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 88 #define P2_1_PORT GPIO_PRT2 89 #define P2_1_PIN 1u 90 #define P2_1_NUM 1u 91 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 92 93 /* PORT 5 (GPIO) */ 94 #define P5_0_PORT GPIO_PRT5 95 #define P5_0_PIN 0u 96 #define P5_0_NUM 0u 97 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 98 #define P5_1_PORT GPIO_PRT5 99 #define P5_1_PIN 1u 100 #define P5_1_NUM 1u 101 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 102 103 /* PORT 6 (GPIO) */ 104 #define P6_0_PORT GPIO_PRT6 105 #define P6_0_PIN 0u 106 #define P6_0_NUM 0u 107 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 108 #define P6_1_PORT GPIO_PRT6 109 #define P6_1_PIN 1u 110 #define P6_1_NUM 1u 111 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 112 #define P6_2_PORT GPIO_PRT6 113 #define P6_2_PIN 2u 114 #define P6_2_NUM 2u 115 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 116 #define P6_3_PORT GPIO_PRT6 117 #define P6_3_PIN 3u 118 #define P6_3_NUM 3u 119 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 120 #define P6_4_PORT GPIO_PRT6 121 #define P6_4_PIN 4u 122 #define P6_4_NUM 4u 123 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 124 #define P6_5_PORT GPIO_PRT6 125 #define P6_5_PIN 5u 126 #define P6_5_NUM 5u 127 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 128 #define P6_6_PORT GPIO_PRT6 129 #define P6_6_PIN 6u 130 #define P6_6_NUM 6u 131 #define P6_6_AMUXSEGMENT AMUXBUS_MAIN 132 133 /* PORT 7 (GPIO) */ 134 #define P7_0_PORT GPIO_PRT7 135 #define P7_0_PIN 0u 136 #define P7_0_NUM 0u 137 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 138 #define P7_1_PORT GPIO_PRT7 139 #define P7_1_PIN 1u 140 #define P7_1_NUM 1u 141 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 142 #define P7_2_PORT GPIO_PRT7 143 #define P7_2_PIN 2u 144 #define P7_2_NUM 2u 145 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 146 147 /* PORT 8 (GPIO) */ 148 #define P8_0_PORT GPIO_PRT8 149 #define P8_0_PIN 0u 150 #define P8_0_NUM 0u 151 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 152 #define P8_1_PORT GPIO_PRT8 153 #define P8_1_PIN 1u 154 #define P8_1_NUM 1u 155 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 156 157 /* PORT 11 (GPIO) */ 158 #define P11_0_PORT GPIO_PRT11 159 #define P11_0_PIN 0u 160 #define P11_0_NUM 0u 161 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 162 #define P11_1_PORT GPIO_PRT11 163 #define P11_1_PIN 1u 164 #define P11_1_NUM 1u 165 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 166 #define P11_2_PORT GPIO_PRT11 167 #define P11_2_PIN 2u 168 #define P11_2_NUM 2u 169 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 170 171 /* PORT 12 (GPIO) */ 172 #define P12_0_PORT GPIO_PRT12 173 #define P12_0_PIN 0u 174 #define P12_0_NUM 0u 175 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 176 #define P12_1_PORT GPIO_PRT12 177 #define P12_1_PIN 1u 178 #define P12_1_NUM 1u 179 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 180 181 /* PORT 13 (GPIO) */ 182 #define P13_0_PORT GPIO_PRT13 183 #define P13_0_PIN 0u 184 #define P13_0_NUM 0u 185 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 186 #define P13_1_PORT GPIO_PRT13 187 #define P13_1_PIN 1u 188 #define P13_1_NUM 1u 189 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 190 #define P13_2_PORT GPIO_PRT13 191 #define P13_2_PIN 2u 192 #define P13_2_NUM 2u 193 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 194 #define P13_3_PORT GPIO_PRT13 195 #define P13_3_PIN 3u 196 #define P13_3_NUM 3u 197 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 198 199 /* PORT 14 (GPIO) */ 200 #define P14_0_PORT GPIO_PRT14 201 #define P14_0_PIN 0u 202 #define P14_0_NUM 0u 203 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 204 #define P14_1_PORT GPIO_PRT14 205 #define P14_1_PIN 1u 206 #define P14_1_NUM 1u 207 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 208 #define P14_2_PORT GPIO_PRT14 209 #define P14_2_PIN 2u 210 #define P14_2_NUM 2u 211 #define P14_2_AMUXSEGMENT AMUXBUS_MAIN 212 213 /* PORT 18 (GPIO) */ 214 #define P18_0_PORT GPIO_PRT18 215 #define P18_0_PIN 0u 216 #define P18_0_NUM 0u 217 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 218 #define P18_1_PORT GPIO_PRT18 219 #define P18_1_PIN 1u 220 #define P18_1_NUM 1u 221 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 222 #define P18_3_PORT GPIO_PRT18 223 #define P18_3_PIN 3u 224 #define P18_3_NUM 3u 225 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 226 #define P18_4_PORT GPIO_PRT18 227 #define P18_4_PIN 4u 228 #define P18_4_NUM 4u 229 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 230 #define P18_5_PORT GPIO_PRT18 231 #define P18_5_PIN 5u 232 #define P18_5_NUM 5u 233 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 234 #define P18_6_PORT GPIO_PRT18 235 #define P18_6_PIN 6u 236 #define P18_6_NUM 6u 237 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 238 #define P18_7_PORT GPIO_PRT18 239 #define P18_7_PIN 7u 240 #define P18_7_NUM 7u 241 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 242 243 /* PORT 21 (GPIO) */ 244 #define P21_0_PORT GPIO_PRT21 245 #define P21_0_PIN 0u 246 #define P21_0_NUM 0u 247 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 248 #define P21_1_PORT GPIO_PRT21 249 #define P21_1_PIN 1u 250 #define P21_1_NUM 1u 251 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 252 #define P21_2_PORT GPIO_PRT21 253 #define P21_2_PIN 2u 254 #define P21_2_NUM 2u 255 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 256 #define P21_3_PORT GPIO_PRT21 257 #define P21_3_PIN 3u 258 #define P21_3_NUM 3u 259 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 260 261 /* PORT 22 (GPIO) */ 262 #define P22_0_PORT GPIO_PRT22 263 #define P22_0_PIN 0u 264 #define P22_0_NUM 0u 265 #define P22_0_AMUXSEGMENT AMUXBUS_MAIN 266 267 /* PORT 23 (GPIO) */ 268 #define P23_3_PORT GPIO_PRT23 269 #define P23_3_PIN 3u 270 #define P23_3_NUM 3u 271 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 272 #define P23_4_PORT GPIO_PRT23 273 #define P23_4_PIN 4u 274 #define P23_4_NUM 4u 275 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 276 #define P23_5_PORT GPIO_PRT23 277 #define P23_5_PIN 5u 278 #define P23_5_NUM 5u 279 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 280 #define P23_6_PORT GPIO_PRT23 281 #define P23_6_PIN 6u 282 #define P23_6_NUM 6u 283 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 284 #define P23_7_PORT GPIO_PRT23 285 #define P23_7_PIN 7u 286 #define P23_7_NUM 7u 287 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 288 289 /* Analog Connections */ 290 #define PASS0_I_TEMP_KELVIN_PORT 21u 291 #define PASS0_I_TEMP_KELVIN_PIN 2u 292 #define PASS0_SARMUX_MOTOR0_PORT 11u 293 #define PASS0_SARMUX_MOTOR0_PIN 0u 294 #define PASS0_SARMUX_MOTOR1_PORT 11u 295 #define PASS0_SARMUX_MOTOR1_PIN 1u 296 #define PASS0_SARMUX_MOTOR2_PORT 11u 297 #define PASS0_SARMUX_MOTOR2_PIN 2u 298 #define PASS0_SARMUX_PADS0_PORT 6u 299 #define PASS0_SARMUX_PADS0_PIN 0u 300 #define PASS0_SARMUX_PADS1_PORT 6u 301 #define PASS0_SARMUX_PADS1_PIN 1u 302 #define PASS0_SARMUX_PADS10_PORT 7u 303 #define PASS0_SARMUX_PADS10_PIN 2u 304 #define PASS0_SARMUX_PADS16_PORT 8u 305 #define PASS0_SARMUX_PADS16_PIN 1u 306 #define PASS0_SARMUX_PADS2_PORT 6u 307 #define PASS0_SARMUX_PADS2_PIN 2u 308 #define PASS0_SARMUX_PADS3_PORT 6u 309 #define PASS0_SARMUX_PADS3_PIN 3u 310 #define PASS0_SARMUX_PADS36_PORT 12u 311 #define PASS0_SARMUX_PADS36_PIN 0u 312 #define PASS0_SARMUX_PADS37_PORT 12u 313 #define PASS0_SARMUX_PADS37_PIN 1u 314 #define PASS0_SARMUX_PADS4_PORT 6u 315 #define PASS0_SARMUX_PADS4_PIN 4u 316 #define PASS0_SARMUX_PADS44_PORT 13u 317 #define PASS0_SARMUX_PADS44_PIN 0u 318 #define PASS0_SARMUX_PADS45_PORT 13u 319 #define PASS0_SARMUX_PADS45_PIN 1u 320 #define PASS0_SARMUX_PADS46_PORT 13u 321 #define PASS0_SARMUX_PADS46_PIN 2u 322 #define PASS0_SARMUX_PADS47_PORT 13u 323 #define PASS0_SARMUX_PADS47_PIN 3u 324 #define PASS0_SARMUX_PADS5_PORT 6u 325 #define PASS0_SARMUX_PADS5_PIN 5u 326 #define PASS0_SARMUX_PADS52_PORT 14u 327 #define PASS0_SARMUX_PADS52_PIN 0u 328 #define PASS0_SARMUX_PADS53_PORT 14u 329 #define PASS0_SARMUX_PADS53_PIN 1u 330 #define PASS0_SARMUX_PADS54_PORT 14u 331 #define PASS0_SARMUX_PADS54_PIN 2u 332 #define PASS0_SARMUX_PADS6_PORT 6u 333 #define PASS0_SARMUX_PADS6_PIN 6u 334 #define PASS0_SARMUX_PADS64_PORT 18u 335 #define PASS0_SARMUX_PADS64_PIN 0u 336 #define PASS0_SARMUX_PADS65_PORT 18u 337 #define PASS0_SARMUX_PADS65_PIN 1u 338 #define PASS0_SARMUX_PADS67_PORT 18u 339 #define PASS0_SARMUX_PADS67_PIN 3u 340 #define PASS0_SARMUX_PADS68_PORT 18u 341 #define PASS0_SARMUX_PADS68_PIN 4u 342 #define PASS0_SARMUX_PADS69_PORT 18u 343 #define PASS0_SARMUX_PADS69_PIN 5u 344 #define PASS0_SARMUX_PADS70_PORT 18u 345 #define PASS0_SARMUX_PADS70_PIN 6u 346 #define PASS0_SARMUX_PADS71_PORT 18u 347 #define PASS0_SARMUX_PADS71_PIN 7u 348 #define PASS0_SARMUX_PADS8_PORT 7u 349 #define PASS0_SARMUX_PADS8_PIN 0u 350 #define PASS0_SARMUX_PADS9_PORT 7u 351 #define PASS0_SARMUX_PADS9_PIN 1u 352 #define PASS0_VE_TEMP_KELVIN_PORT 23u 353 #define PASS0_VE_TEMP_KELVIN_PIN 4u 354 #define SRSS_ADFT_PIN0_PORT 23u 355 #define SRSS_ADFT_PIN0_PIN 4u 356 #define SRSS_ADFT_PIN1_PORT 23u 357 #define SRSS_ADFT_PIN1_PIN 3u 358 #define SRSS_ECO_IN_PORT 21u 359 #define SRSS_ECO_IN_PIN 2u 360 #define SRSS_ECO_OUT_PORT 21u 361 #define SRSS_ECO_OUT_PIN 3u 362 #define SRSS_VEXT_REF_REG_PORT 21u 363 #define SRSS_VEXT_REF_REG_PIN 3u 364 #define SRSS_WCO_IN_PORT 21u 365 #define SRSS_WCO_IN_PIN 0u 366 #define SRSS_WCO_OUT_PORT 21u 367 #define SRSS_WCO_OUT_PIN 1u 368 369 /* HSIOM Connections */ 370 typedef enum 371 { 372 /* Generic HSIOM connections */ 373 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 374 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 375 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 376 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 377 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 378 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 379 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 380 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 381 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 382 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 383 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 384 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 385 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 386 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 387 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 388 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 389 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 390 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 391 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 392 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 393 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 394 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 395 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 396 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 397 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 398 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 399 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 400 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 401 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 402 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 403 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 404 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 405 406 /* P0.0 */ 407 P0_0_GPIO = 0, /* GPIO controls 'out' */ 408 P0_0_AMUXA = 4, /* Analog mux bus A */ 409 P0_0_AMUXB = 5, /* Analog mux bus B */ 410 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 411 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 412 P0_0_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:1 */ 413 P0_0_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ 414 P0_0_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:1 */ 415 P0_0_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:1 */ 416 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 417 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 418 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 419 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 420 421 /* P0.1 */ 422 P0_1_GPIO = 0, /* GPIO controls 'out' */ 423 P0_1_AMUXA = 4, /* Analog mux bus A */ 424 P0_1_AMUXB = 5, /* Analog mux bus B */ 425 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 426 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 427 P0_1_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:1 */ 428 P0_1_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:1 */ 429 P0_1_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:1 */ 430 P0_1_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:1 */ 431 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 432 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 433 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 434 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 435 436 /* P0.2 */ 437 P0_2_GPIO = 0, /* GPIO controls 'out' */ 438 P0_2_AMUXA = 4, /* Analog mux bus A */ 439 P0_2_AMUXB = 5, /* Analog mux bus B */ 440 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 441 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 442 P0_2_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:1 */ 443 P0_2_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:1 */ 444 P0_2_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:1 */ 445 P0_2_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:1 */ 446 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 447 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 448 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 449 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 450 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 451 452 /* P0.3 */ 453 P0_3_GPIO = 0, /* GPIO controls 'out' */ 454 P0_3_AMUXA = 4, /* Analog mux bus A */ 455 P0_3_AMUXB = 5, /* Analog mux bus B */ 456 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 457 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 458 P0_3_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:1 */ 459 P0_3_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:1 */ 460 P0_3_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:1 */ 461 P0_3_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:1 */ 462 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 463 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 464 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 465 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 466 467 /* P2.0 */ 468 P2_0_GPIO = 0, /* GPIO controls 'out' */ 469 P2_0_AMUXA = 4, /* Analog mux bus A */ 470 P2_0_AMUXB = 5, /* Analog mux bus B */ 471 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 472 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 473 P2_0_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 474 P2_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:1 */ 475 P2_0_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ 476 P2_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ 477 P2_0_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:0 */ 478 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 479 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 480 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 481 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 482 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 483 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 484 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 485 486 /* P2.1 */ 487 P2_1_GPIO = 0, /* GPIO controls 'out' */ 488 P2_1_AMUXA = 4, /* Analog mux bus A */ 489 P2_1_AMUXB = 5, /* Analog mux bus B */ 490 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 491 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 492 P2_1_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 493 P2_1_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 494 P2_1_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:1 */ 495 P2_1_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ 496 P2_1_TCPWM0_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1551]:0 */ 497 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 498 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 499 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 500 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 501 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 502 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 503 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 504 505 /* P5.0 */ 506 P5_0_GPIO = 0, /* GPIO controls 'out' */ 507 P5_0_AMUXA = 4, /* Analog mux bus A */ 508 P5_0_AMUXB = 5, /* Analog mux bus B */ 509 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 510 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 511 P5_0_TCPWM0_LINE9 = 8, /* Digital Active - tcpwm[0].line[9]:0 */ 512 P5_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:0 */ 513 P5_0_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ 514 P5_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ 515 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 516 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 517 518 /* P5.1 */ 519 P5_1_GPIO = 0, /* GPIO controls 'out' */ 520 P5_1_AMUXA = 4, /* Analog mux bus A */ 521 P5_1_AMUXB = 5, /* Analog mux bus B */ 522 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 523 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 524 P5_1_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:0 */ 525 P5_1_TCPWM0_LINE_COMPL9 = 9, /* Digital Active - tcpwm[0].line_compl[9]:0 */ 526 P5_1_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ 527 P5_1_TCPWM0_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ 528 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 529 530 /* P6.0 */ 531 P6_0_GPIO = 0, /* GPIO controls 'out' */ 532 P6_0_AMUXA = 4, /* Analog mux bus A */ 533 P6_0_AMUXB = 5, /* Analog mux bus B */ 534 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 535 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 536 P6_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ 537 P6_0_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:0 */ 538 P6_0_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:0 */ 539 P6_0_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:0 */ 540 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 541 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 542 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 543 544 /* P6.1 */ 545 P6_1_GPIO = 0, /* GPIO controls 'out' */ 546 P6_1_AMUXA = 4, /* Analog mux bus A */ 547 P6_1_AMUXB = 5, /* Analog mux bus B */ 548 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 549 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 550 P6_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 551 P6_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 552 P6_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 553 P6_1_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:0 */ 554 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 555 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 556 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 557 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 558 559 /* P6.2 */ 560 P6_2_GPIO = 0, /* GPIO controls 'out' */ 561 P6_2_AMUXA = 4, /* Analog mux bus A */ 562 P6_2_AMUXB = 5, /* Analog mux bus B */ 563 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 564 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 565 P6_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ 566 P6_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 567 P6_2_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:0 */ 568 P6_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 569 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 570 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 571 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 572 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 573 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 574 575 /* P6.3 */ 576 P6_3_GPIO = 0, /* GPIO controls 'out' */ 577 P6_3_AMUXA = 4, /* Analog mux bus A */ 578 P6_3_AMUXB = 5, /* Analog mux bus B */ 579 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 580 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 581 P6_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 582 P6_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 583 P6_3_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 584 P6_3_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:0 */ 585 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 586 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 587 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 588 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 589 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 590 591 /* P6.4 */ 592 P6_4_GPIO = 0, /* GPIO controls 'out' */ 593 P6_4_AMUXA = 4, /* Analog mux bus A */ 594 P6_4_AMUXB = 5, /* Analog mux bus B */ 595 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 596 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 597 P6_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ 598 P6_4_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 599 P6_4_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:0 */ 600 P6_4_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:0 */ 601 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 602 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 603 604 /* P6.5 */ 605 P6_5_GPIO = 0, /* GPIO controls 'out' */ 606 P6_5_AMUXA = 4, /* Analog mux bus A */ 607 P6_5_AMUXB = 5, /* Analog mux bus B */ 608 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 609 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 610 P6_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 611 P6_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 612 P6_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:0 */ 613 P6_5_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:0 */ 614 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 615 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 616 617 /* P6.6 */ 618 P6_6_GPIO = 0, /* GPIO controls 'out' */ 619 P6_6_AMUXA = 4, /* Analog mux bus A */ 620 P6_6_AMUXB = 5, /* Analog mux bus B */ 621 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 622 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 623 P6_6_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:0 */ 624 P6_6_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 625 P6_6_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:0 */ 626 P6_6_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:0 */ 627 P6_6_SCB4_SPI_SELECT3 = 19, /* Digital Active - scb[4].spi_select3:0 */ 628 P6_6_PERI_TR_IO_INPUT8 = 26, /* Digital Active - peri.tr_io_input[8]:0 */ 629 630 /* P7.0 */ 631 P7_0_GPIO = 0, /* GPIO controls 'out' */ 632 P7_0_AMUXA = 4, /* Analog mux bus A */ 633 P7_0_AMUXB = 5, /* Analog mux bus B */ 634 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 635 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 636 P7_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ 637 P7_0_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 638 P7_0_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:0 */ 639 P7_0_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:0 */ 640 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 641 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 642 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 643 P7_0_CXPI0_CXPI_RX0 = 22, /* Digital Active - cxpi[0].cxpi_rx[0]:0 */ 644 645 /* P7.1 */ 646 P7_1_GPIO = 0, /* GPIO controls 'out' */ 647 P7_1_AMUXA = 4, /* Analog mux bus A */ 648 P7_1_AMUXB = 5, /* Analog mux bus B */ 649 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 650 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 651 P7_1_TCPWM0_LINE15 = 8, /* Digital Active - tcpwm[0].line[15]:0 */ 652 P7_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 653 P7_1_TCPWM0_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[45]:0 */ 654 P7_1_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:0 */ 655 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 656 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 657 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 658 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 659 P7_1_CXPI0_CXPI_TX0 = 22, /* Digital Active - cxpi[0].cxpi_tx[0]:0 */ 660 661 /* P7.2 */ 662 P7_2_GPIO = 0, /* GPIO controls 'out' */ 663 P7_2_AMUXA = 4, /* Analog mux bus A */ 664 P7_2_AMUXB = 5, /* Analog mux bus B */ 665 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 666 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 667 P7_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ 668 P7_2_TCPWM0_LINE_COMPL15 = 9, /* Digital Active - tcpwm[0].line_compl[15]:0 */ 669 P7_2_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:0 */ 670 P7_2_TCPWM0_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[46]:0 */ 671 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 672 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 673 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 674 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 675 P7_2_CXPI0_CXPI_EN0 = 22, /* Digital Active - cxpi[0].cxpi_en[0]:0 */ 676 677 /* P8.0 */ 678 P8_0_GPIO = 0, /* GPIO controls 'out' */ 679 P8_0_AMUXA = 4, /* Analog mux bus A */ 680 P8_0_AMUXB = 5, /* Analog mux bus B */ 681 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 682 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 683 P8_0_TCPWM0_LINE19 = 8, /* Digital Active - tcpwm[0].line[19]:0 */ 684 P8_0_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:0 */ 685 P8_0_TCPWM0_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[57]:0 */ 686 P8_0_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:0 */ 687 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 688 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 689 690 /* P8.1 */ 691 P8_1_GPIO = 0, /* GPIO controls 'out' */ 692 P8_1_AMUXA = 4, /* Analog mux bus A */ 693 P8_1_AMUXB = 5, /* Analog mux bus B */ 694 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 695 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 696 P8_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ 697 P8_1_TCPWM0_LINE_COMPL19 = 9, /* Digital Active - tcpwm[0].line_compl[19]:0 */ 698 P8_1_TCPWM0_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[60]:0 */ 699 P8_1_TCPWM0_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[58]:0 */ 700 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 701 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 702 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 703 704 /* P11.0 */ 705 P11_0_GPIO = 0, /* GPIO controls 'out' */ 706 P11_0_AMUXA = 4, /* Analog mux bus A */ 707 P11_0_AMUXB = 5, /* Analog mux bus B */ 708 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 709 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 710 711 /* P11.1 */ 712 P11_1_GPIO = 0, /* GPIO controls 'out' */ 713 P11_1_AMUXA = 4, /* Analog mux bus A */ 714 P11_1_AMUXB = 5, /* Analog mux bus B */ 715 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 716 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 717 718 /* P11.2 */ 719 P11_2_GPIO = 0, /* GPIO controls 'out' */ 720 P11_2_AMUXA = 4, /* Analog mux bus A */ 721 P11_2_AMUXB = 5, /* Analog mux bus B */ 722 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 723 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 724 725 /* P12.0 */ 726 P12_0_GPIO = 0, /* GPIO controls 'out' */ 727 P12_0_AMUXA = 4, /* Analog mux bus A */ 728 P12_0_AMUXB = 5, /* Analog mux bus B */ 729 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 730 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 731 P12_0_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ 732 P12_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:0 */ 733 P12_0_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:0 */ 734 P12_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:0 */ 735 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 736 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 737 738 /* P12.1 */ 739 P12_1_GPIO = 0, /* GPIO controls 'out' */ 740 P12_1_AMUXA = 4, /* Analog mux bus A */ 741 P12_1_AMUXB = 5, /* Analog mux bus B */ 742 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 743 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 744 P12_1_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ 745 P12_1_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ 746 P12_1_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:0 */ 747 P12_1_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:0 */ 748 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 749 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 750 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 751 752 /* P13.0 */ 753 P13_0_GPIO = 0, /* GPIO controls 'out' */ 754 P13_0_AMUXA = 4, /* Analog mux bus A */ 755 P13_0_AMUXB = 5, /* Analog mux bus B */ 756 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 757 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 758 P13_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ 759 P13_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:0 */ 760 P13_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:0 */ 761 P13_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:0 */ 762 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 763 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 764 P13_0_SCB3_SPI_MISO = 19, /* Digital Active - scb[3].spi_miso:0 */ 765 P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ 766 P13_0_CXPI0_CXPI_RX1 = 22, /* Digital Active - cxpi[0].cxpi_rx[1]:0 */ 767 768 /* P13.1 */ 769 P13_1_GPIO = 0, /* GPIO controls 'out' */ 770 P13_1_AMUXA = 4, /* Analog mux bus A */ 771 P13_1_AMUXB = 5, /* Analog mux bus B */ 772 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 773 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 774 P13_1_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:0 */ 775 P13_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ 776 P13_1_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:0 */ 777 P13_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:0 */ 778 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 779 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 780 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 781 P13_1_SCB3_SPI_MOSI = 19, /* Digital Active - scb[3].spi_mosi:0 */ 782 P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ 783 P13_1_CXPI0_CXPI_TX1 = 22, /* Digital Active - cxpi[0].cxpi_tx[1]:0 */ 784 785 /* P13.2 */ 786 P13_2_GPIO = 0, /* GPIO controls 'out' */ 787 P13_2_AMUXA = 4, /* Analog mux bus A */ 788 P13_2_AMUXB = 5, /* Analog mux bus B */ 789 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 790 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 791 P13_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ 792 P13_2_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:0 */ 793 P13_2_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:0 */ 794 P13_2_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:0 */ 795 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 796 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 797 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 798 P13_2_SCB3_SPI_CLK = 19, /* Digital Active - scb[3].spi_clk:0 */ 799 P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ 800 P13_2_CXPI0_CXPI_EN1 = 22, /* Digital Active - cxpi[0].cxpi_en[1]:0 */ 801 802 /* P13.3 */ 803 P13_3_GPIO = 0, /* GPIO controls 'out' */ 804 P13_3_AMUXA = 4, /* Analog mux bus A */ 805 P13_3_AMUXB = 5, /* Analog mux bus B */ 806 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 807 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 808 P13_3_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:0 */ 809 P13_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ 810 P13_3_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:0 */ 811 P13_3_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:0 */ 812 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 813 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 814 P13_3_SCB3_SPI_SELECT0 = 19, /* Digital Active - scb[3].spi_select0:0 */ 815 816 /* P14.0 */ 817 P14_0_GPIO = 0, /* GPIO controls 'out' */ 818 P14_0_AMUXA = 4, /* Analog mux bus A */ 819 P14_0_AMUXB = 5, /* Analog mux bus B */ 820 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 821 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 822 P14_0_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:0 */ 823 P14_0_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:0 */ 824 P14_0_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:0 */ 825 P14_0_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:0 */ 826 P14_0_TCPWM0_LINE518 = 16, /* Digital Active - tcpwm[0].line[518]:1 */ 827 P14_0_SCB2_UART_RX = 17, /* Digital Active - scb[2].uart_rx:0 */ 828 P14_0_SCB2_SPI_MISO = 19, /* Digital Active - scb[2].spi_miso:0 */ 829 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 830 831 /* P14.1 */ 832 P14_1_GPIO = 0, /* GPIO controls 'out' */ 833 P14_1_AMUXA = 4, /* Analog mux bus A */ 834 P14_1_AMUXB = 5, /* Analog mux bus B */ 835 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 836 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 837 P14_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:0 */ 838 P14_1_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:0 */ 839 P14_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:0 */ 840 P14_1_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:0 */ 841 P14_1_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:1 */ 842 P14_1_SCB2_UART_TX = 17, /* Digital Active - scb[2].uart_tx:0 */ 843 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 844 P14_1_SCB2_SPI_MOSI = 19, /* Digital Active - scb[2].spi_mosi:0 */ 845 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 846 847 /* P14.2 */ 848 P14_2_GPIO = 0, /* GPIO controls 'out' */ 849 P14_2_AMUXA = 4, /* Analog mux bus A */ 850 P14_2_AMUXB = 5, /* Analog mux bus B */ 851 P14_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 852 P14_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 853 P14_2_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:0 */ 854 P14_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:0 */ 855 P14_2_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:0 */ 856 P14_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:0 */ 857 P14_2_TCPWM0_LINE519 = 16, /* Digital Active - tcpwm[0].line[519]:1 */ 858 P14_2_SCB2_UART_RTS = 17, /* Digital Active - scb[2].uart_rts:0 */ 859 P14_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:0 */ 860 P14_2_SCB2_SPI_CLK = 19, /* Digital Active - scb[2].spi_clk:0 */ 861 P14_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:1 */ 862 863 /* P18.0 */ 864 P18_0_GPIO = 0, /* GPIO controls 'out' */ 865 P18_0_AMUXA = 4, /* Analog mux bus A */ 866 P18_0_AMUXB = 5, /* Analog mux bus B */ 867 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 868 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 869 P18_0_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:1 */ 870 P18_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 871 P18_0_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:1 */ 872 P18_0_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:1 */ 873 P18_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:0 */ 874 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 875 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 876 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 877 878 /* P18.1 */ 879 P18_1_GPIO = 0, /* GPIO controls 'out' */ 880 P18_1_AMUXA = 4, /* Analog mux bus A */ 881 P18_1_AMUXB = 5, /* Analog mux bus B */ 882 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 883 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 884 P18_1_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:1 */ 885 P18_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 886 P18_1_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:1 */ 887 P18_1_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:1 */ 888 P18_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:0 */ 889 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 890 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 891 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 892 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 893 894 /* P18.3 */ 895 P18_3_GPIO = 0, /* GPIO controls 'out' */ 896 P18_3_AMUXA = 4, /* Analog mux bus A */ 897 P18_3_AMUXB = 5, /* Analog mux bus B */ 898 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 899 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 900 P18_3_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:1 */ 901 P18_3_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:1 */ 902 P18_3_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:1 */ 903 P18_3_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:1 */ 904 P18_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:0 */ 905 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 906 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 907 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 908 909 /* P18.4 */ 910 P18_4_GPIO = 0, /* GPIO controls 'out' */ 911 P18_4_AMUXA = 4, /* Analog mux bus A */ 912 P18_4_AMUXB = 5, /* Analog mux bus B */ 913 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 914 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 915 P18_4_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:1 */ 916 P18_4_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:1 */ 917 P18_4_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:1 */ 918 P18_4_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:1 */ 919 P18_4_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:0 */ 920 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 921 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 922 923 /* P18.5 */ 924 P18_5_GPIO = 0, /* GPIO controls 'out' */ 925 P18_5_AMUXA = 4, /* Analog mux bus A */ 926 P18_5_AMUXB = 5, /* Analog mux bus B */ 927 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 928 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 929 P18_5_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:1 */ 930 P18_5_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:1 */ 931 P18_5_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:1 */ 932 P18_5_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:1 */ 933 P18_5_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:0 */ 934 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 935 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 936 937 /* P18.6 */ 938 P18_6_GPIO = 0, /* GPIO controls 'out' */ 939 P18_6_AMUXA = 4, /* Analog mux bus A */ 940 P18_6_AMUXB = 5, /* Analog mux bus B */ 941 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 942 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 943 P18_6_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:1 */ 944 P18_6_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:1 */ 945 P18_6_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:1 */ 946 P18_6_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:1 */ 947 P18_6_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:0 */ 948 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 949 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 950 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 951 952 /* P18.7 */ 953 P18_7_GPIO = 0, /* GPIO controls 'out' */ 954 P18_7_AMUXA = 4, /* Analog mux bus A */ 955 P18_7_AMUXB = 5, /* Analog mux bus B */ 956 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 957 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 958 P18_7_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:1 */ 959 P18_7_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:1 */ 960 P18_7_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:1 */ 961 P18_7_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:1 */ 962 P18_7_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:0 */ 963 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 964 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 965 966 /* P21.0 */ 967 P21_0_GPIO = 0, /* GPIO controls 'out' */ 968 P21_0_AMUXA = 4, /* Analog mux bus A */ 969 P21_0_AMUXB = 5, /* Analog mux bus B */ 970 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 971 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 972 P21_0_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:1 */ 973 P21_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:1 */ 974 P21_0_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:1 */ 975 P21_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:1 */ 976 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 977 978 /* P21.1 */ 979 P21_1_GPIO = 0, /* GPIO controls 'out' */ 980 P21_1_AMUXA = 4, /* Analog mux bus A */ 981 P21_1_AMUXB = 5, /* Analog mux bus B */ 982 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 983 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 984 P21_1_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:1 */ 985 P21_1_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:1 */ 986 P21_1_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:1 */ 987 P21_1_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:1 */ 988 989 /* P21.2 */ 990 P21_2_GPIO = 0, /* GPIO controls 'out' */ 991 P21_2_AMUXA = 4, /* Analog mux bus A */ 992 P21_2_AMUXB = 5, /* Analog mux bus B */ 993 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 994 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 995 P21_2_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:1 */ 996 P21_2_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:1 */ 997 P21_2_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:1 */ 998 P21_2_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:1 */ 999 P21_2_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:0 */ 1000 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 1001 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1002 1003 /* P21.3 */ 1004 P21_3_GPIO = 0, /* GPIO controls 'out' */ 1005 P21_3_AMUXA = 4, /* Analog mux bus A */ 1006 P21_3_AMUXB = 5, /* Analog mux bus B */ 1007 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1008 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1009 P21_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:1 */ 1010 P21_3_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:1 */ 1011 P21_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:1 */ 1012 P21_3_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:1 */ 1013 1014 /* P22.0 */ 1015 P22_0_GPIO = 0, /* GPIO controls 'out' */ 1016 P22_0_AMUXA = 4, /* Analog mux bus A */ 1017 P22_0_AMUXB = 5, /* Analog mux bus B */ 1018 P22_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1019 P22_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1020 P22_0_TCPWM0_LINE34 = 8, /* Digital Active - tcpwm[0].line[34]:1 */ 1021 P22_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:1 */ 1022 P22_0_TCPWM0_TR_ONE_CNT_IN102 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:1 */ 1023 P22_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:1 */ 1024 P22_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ 1025 P22_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ 1026 P22_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 1027 P22_0_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1028 1029 /* P23.3 */ 1030 P23_3_GPIO = 0, /* GPIO controls 'out' */ 1031 P23_3_AMUXA = 4, /* Analog mux bus A */ 1032 P23_3_AMUXB = 5, /* Analog mux bus B */ 1033 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1034 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1035 P23_3_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:1 */ 1036 P23_3_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:1 */ 1037 P23_3_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:1 */ 1038 P23_3_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:1 */ 1039 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 1040 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 1041 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 1042 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 1043 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1044 1045 /* P23.4 */ 1046 P23_4_GPIO = 0, /* GPIO controls 'out' */ 1047 P23_4_AMUXA = 4, /* Analog mux bus A */ 1048 P23_4_AMUXB = 5, /* Analog mux bus B */ 1049 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1050 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1051 P23_4_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ 1052 P23_4_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:1 */ 1053 P23_4_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:1 */ 1054 P23_4_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:1 */ 1055 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 1056 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 1057 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 1058 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 1059 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 1060 1061 /* P23.5 */ 1062 P23_5_GPIO = 0, /* GPIO controls 'out' */ 1063 P23_5_AMUXA = 4, /* Analog mux bus A */ 1064 P23_5_AMUXB = 5, /* Analog mux bus B */ 1065 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1066 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1067 P23_5_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ 1068 P23_5_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ 1069 P23_5_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:1 */ 1070 P23_5_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:1 */ 1071 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 1072 P23_5_LIN0_LIN_RX9 = 20, /* Digital Active - lin[0].lin_rx[9]:0 */ 1073 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 1074 1075 /* P23.6 */ 1076 P23_6_GPIO = 0, /* GPIO controls 'out' */ 1077 P23_6_AMUXA = 4, /* Analog mux bus A */ 1078 P23_6_AMUXB = 5, /* Analog mux bus B */ 1079 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1080 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1081 P23_6_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ 1082 P23_6_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ 1083 P23_6_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:1 */ 1084 P23_6_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:1 */ 1085 P23_6_LIN0_LIN_TX9 = 20, /* Digital Active - lin[0].lin_tx[9]:0 */ 1086 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 1087 1088 /* P23.7 */ 1089 P23_7_GPIO = 0, /* GPIO controls 'out' */ 1090 P23_7_AMUXA = 4, /* Analog mux bus A */ 1091 P23_7_AMUXB = 5, /* Analog mux bus B */ 1092 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1093 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1094 P23_7_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ 1095 P23_7_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ 1096 P23_7_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:1 */ 1097 P23_7_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:1 */ 1098 P23_7_LIN0_LIN_EN9 = 20, /* Digital Active - lin[0].lin_en[9]:0 */ 1099 P23_7_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:1 */ 1100 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 1101 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 1102 P23_7_SRSS_DDFT_PIN_IN0 = 31 /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1103 } en_hsiom_sel_t; 1104 1105 #endif /* _GPIO_TVIIBE4M_64_LQFP_H_ */ 1106 1107 1108 /* [] END OF FILE */ 1109
