1 /***************************************************************************//** 2 * \file gpio_tviibe1m_144_lqfp.h 3 * 4 * \brief 5 * TVIIBE1M device GPIO header for 144-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_TVIIBE1M_144_LQFP_H_ 28 #define _GPIO_TVIIBE1M_144_LQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_LQFP 44 #define CY_GPIO_PIN_COUNT 144u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_EFUSE, 50 AMUXBUS_MAIN, 51 AMUXBUS_TEST, 52 AMUXBUS_TESTECT, 53 AMUXBUS_TESTSRSS, 54 }; 55 56 /* AMUX Splitter Controls */ 57 typedef enum 58 { 59 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_EFUSE */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 0 (GPIO) */ 66 #define P0_0_PORT GPIO_PRT0 67 #define P0_0_PIN 0u 68 #define P0_0_NUM 0u 69 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 70 #define P0_1_PORT GPIO_PRT0 71 #define P0_1_PIN 1u 72 #define P0_1_NUM 1u 73 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 78 #define P0_3_PORT GPIO_PRT0 79 #define P0_3_PIN 3u 80 #define P0_3_NUM 3u 81 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 82 83 /* PORT 1 (GPIO) */ 84 #define P1_0_PORT GPIO_PRT1 85 #define P1_0_PIN 0u 86 #define P1_0_NUM 0u 87 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 88 #define P1_1_PORT GPIO_PRT1 89 #define P1_1_PIN 1u 90 #define P1_1_NUM 1u 91 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 92 93 /* PORT 2 (GPIO) */ 94 #define P2_0_PORT GPIO_PRT2 95 #define P2_0_PIN 0u 96 #define P2_0_NUM 0u 97 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 98 #define P2_1_PORT GPIO_PRT2 99 #define P2_1_PIN 1u 100 #define P2_1_NUM 1u 101 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 102 #define P2_2_PORT GPIO_PRT2 103 #define P2_2_PIN 2u 104 #define P2_2_NUM 2u 105 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 106 #define P2_3_PORT GPIO_PRT2 107 #define P2_3_PIN 3u 108 #define P2_3_NUM 3u 109 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 110 #define P2_4_PORT GPIO_PRT2 111 #define P2_4_PIN 4u 112 #define P2_4_NUM 4u 113 #define P2_4_AMUXSEGMENT AMUXBUS_MAIN 114 115 /* PORT 3 (GPIO) */ 116 #define P3_0_PORT GPIO_PRT3 117 #define P3_0_PIN 0u 118 #define P3_0_NUM 0u 119 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 120 #define P3_1_PORT GPIO_PRT3 121 #define P3_1_PIN 1u 122 #define P3_1_NUM 1u 123 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 124 #define P3_2_PORT GPIO_PRT3 125 #define P3_2_PIN 2u 126 #define P3_2_NUM 2u 127 #define P3_2_AMUXSEGMENT AMUXBUS_MAIN 128 #define P3_3_PORT GPIO_PRT3 129 #define P3_3_PIN 3u 130 #define P3_3_NUM 3u 131 #define P3_3_AMUXSEGMENT AMUXBUS_MAIN 132 #define P3_4_PORT GPIO_PRT3 133 #define P3_4_PIN 4u 134 #define P3_4_NUM 4u 135 #define P3_4_AMUXSEGMENT AMUXBUS_MAIN 136 137 /* PORT 4 (GPIO) */ 138 #define P4_0_PORT GPIO_PRT4 139 #define P4_0_PIN 0u 140 #define P4_0_NUM 0u 141 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 142 #define P4_1_PORT GPIO_PRT4 143 #define P4_1_PIN 1u 144 #define P4_1_NUM 1u 145 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 146 147 /* PORT 5 (GPIO) */ 148 #define P5_0_PORT GPIO_PRT5 149 #define P5_0_PIN 0u 150 #define P5_0_NUM 0u 151 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 152 #define P5_1_PORT GPIO_PRT5 153 #define P5_1_PIN 1u 154 #define P5_1_NUM 1u 155 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 156 #define P5_2_PORT GPIO_PRT5 157 #define P5_2_PIN 2u 158 #define P5_2_NUM 2u 159 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 160 #define P5_3_PORT GPIO_PRT5 161 #define P5_3_PIN 3u 162 #define P5_3_NUM 3u 163 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 164 #define P5_4_PORT GPIO_PRT5 165 #define P5_4_PIN 4u 166 #define P5_4_NUM 4u 167 #define P5_4_AMUXSEGMENT AMUXBUS_MAIN 168 169 /* PORT 6 (GPIO) */ 170 #define P6_0_PORT GPIO_PRT6 171 #define P6_0_PIN 0u 172 #define P6_0_NUM 0u 173 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 174 #define P6_1_PORT GPIO_PRT6 175 #define P6_1_PIN 1u 176 #define P6_1_NUM 1u 177 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 178 #define P6_2_PORT GPIO_PRT6 179 #define P6_2_PIN 2u 180 #define P6_2_NUM 2u 181 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 182 #define P6_3_PORT GPIO_PRT6 183 #define P6_3_PIN 3u 184 #define P6_3_NUM 3u 185 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 186 #define P6_4_PORT GPIO_PRT6 187 #define P6_4_PIN 4u 188 #define P6_4_NUM 4u 189 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 190 #define P6_5_PORT GPIO_PRT6 191 #define P6_5_PIN 5u 192 #define P6_5_NUM 5u 193 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 194 #define P6_6_PORT GPIO_PRT6 195 #define P6_6_PIN 6u 196 #define P6_6_NUM 6u 197 #define P6_6_AMUXSEGMENT AMUXBUS_MAIN 198 #define P6_7_PORT GPIO_PRT6 199 #define P6_7_PIN 7u 200 #define P6_7_NUM 7u 201 #define P6_7_AMUXSEGMENT AMUXBUS_MAIN 202 203 /* PORT 7 (GPIO) */ 204 #define P7_0_PORT GPIO_PRT7 205 #define P7_0_PIN 0u 206 #define P7_0_NUM 0u 207 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 208 #define P7_1_PORT GPIO_PRT7 209 #define P7_1_PIN 1u 210 #define P7_1_NUM 1u 211 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 212 #define P7_2_PORT GPIO_PRT7 213 #define P7_2_PIN 2u 214 #define P7_2_NUM 2u 215 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 216 #define P7_3_PORT GPIO_PRT7 217 #define P7_3_PIN 3u 218 #define P7_3_NUM 3u 219 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 220 #define P7_4_PORT GPIO_PRT7 221 #define P7_4_PIN 4u 222 #define P7_4_NUM 4u 223 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 224 #define P7_5_PORT GPIO_PRT7 225 #define P7_5_PIN 5u 226 #define P7_5_NUM 5u 227 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 228 #define P7_6_PORT GPIO_PRT7 229 #define P7_6_PIN 6u 230 #define P7_6_NUM 6u 231 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 232 #define P7_7_PORT GPIO_PRT7 233 #define P7_7_PIN 7u 234 #define P7_7_NUM 7u 235 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 236 237 /* PORT 8 (GPIO) */ 238 #define P8_0_PORT GPIO_PRT8 239 #define P8_0_PIN 0u 240 #define P8_0_NUM 0u 241 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 242 #define P8_1_PORT GPIO_PRT8 243 #define P8_1_PIN 1u 244 #define P8_1_NUM 1u 245 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 246 #define P8_2_PORT GPIO_PRT8 247 #define P8_2_PIN 2u 248 #define P8_2_NUM 2u 249 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 250 #define P8_3_PORT GPIO_PRT8 251 #define P8_3_PIN 3u 252 #define P8_3_NUM 3u 253 #define P8_3_AMUXSEGMENT AMUXBUS_MAIN 254 255 /* PORT 9 (GPIO) */ 256 #define P9_0_PORT GPIO_PRT9 257 #define P9_0_PIN 0u 258 #define P9_0_NUM 0u 259 #define P9_0_AMUXSEGMENT AMUXBUS_MAIN 260 #define P9_1_PORT GPIO_PRT9 261 #define P9_1_PIN 1u 262 #define P9_1_NUM 1u 263 #define P9_1_AMUXSEGMENT AMUXBUS_MAIN 264 265 /* PORT 10 (GPIO) */ 266 #define P10_0_PORT GPIO_PRT10 267 #define P10_0_PIN 0u 268 #define P10_0_NUM 0u 269 #define P10_0_AMUXSEGMENT AMUXBUS_MAIN 270 #define P10_1_PORT GPIO_PRT10 271 #define P10_1_PIN 1u 272 #define P10_1_NUM 1u 273 #define P10_1_AMUXSEGMENT AMUXBUS_MAIN 274 #define P10_2_PORT GPIO_PRT10 275 #define P10_2_PIN 2u 276 #define P10_2_NUM 2u 277 #define P10_2_AMUXSEGMENT AMUXBUS_MAIN 278 #define P10_3_PORT GPIO_PRT10 279 #define P10_3_PIN 3u 280 #define P10_3_NUM 3u 281 #define P10_3_AMUXSEGMENT AMUXBUS_MAIN 282 #define P10_4_PORT GPIO_PRT10 283 #define P10_4_PIN 4u 284 #define P10_4_NUM 4u 285 #define P10_4_AMUXSEGMENT AMUXBUS_MAIN 286 287 /* PORT 11 (GPIO) */ 288 #define P11_0_PORT GPIO_PRT11 289 #define P11_0_PIN 0u 290 #define P11_0_NUM 0u 291 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 292 #define P11_1_PORT GPIO_PRT11 293 #define P11_1_PIN 1u 294 #define P11_1_NUM 1u 295 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 296 #define P11_2_PORT GPIO_PRT11 297 #define P11_2_PIN 2u 298 #define P11_2_NUM 2u 299 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 300 301 /* PORT 12 (GPIO) */ 302 #define P12_0_PORT GPIO_PRT12 303 #define P12_0_PIN 0u 304 #define P12_0_NUM 0u 305 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 306 #define P12_1_PORT GPIO_PRT12 307 #define P12_1_PIN 1u 308 #define P12_1_NUM 1u 309 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 310 #define P12_2_PORT GPIO_PRT12 311 #define P12_2_PIN 2u 312 #define P12_2_NUM 2u 313 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 314 #define P12_3_PORT GPIO_PRT12 315 #define P12_3_PIN 3u 316 #define P12_3_NUM 3u 317 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 318 #define P12_4_PORT GPIO_PRT12 319 #define P12_4_PIN 4u 320 #define P12_4_NUM 4u 321 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 322 #define P12_5_PORT GPIO_PRT12 323 #define P12_5_PIN 5u 324 #define P12_5_NUM 5u 325 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 326 327 /* PORT 13 (GPIO) */ 328 #define P13_0_PORT GPIO_PRT13 329 #define P13_0_PIN 0u 330 #define P13_0_NUM 0u 331 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 332 #define P13_1_PORT GPIO_PRT13 333 #define P13_1_PIN 1u 334 #define P13_1_NUM 1u 335 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 336 #define P13_2_PORT GPIO_PRT13 337 #define P13_2_PIN 2u 338 #define P13_2_NUM 2u 339 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 340 #define P13_3_PORT GPIO_PRT13 341 #define P13_3_PIN 3u 342 #define P13_3_NUM 3u 343 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 344 #define P13_4_PORT GPIO_PRT13 345 #define P13_4_PIN 4u 346 #define P13_4_NUM 4u 347 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 348 #define P13_5_PORT GPIO_PRT13 349 #define P13_5_PIN 5u 350 #define P13_5_NUM 5u 351 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 352 #define P13_6_PORT GPIO_PRT13 353 #define P13_6_PIN 6u 354 #define P13_6_NUM 6u 355 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 356 #define P13_7_PORT GPIO_PRT13 357 #define P13_7_PIN 7u 358 #define P13_7_NUM 7u 359 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 360 361 /* PORT 14 (GPIO) */ 362 #define P14_0_PORT GPIO_PRT14 363 #define P14_0_PIN 0u 364 #define P14_0_NUM 0u 365 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 366 #define P14_1_PORT GPIO_PRT14 367 #define P14_1_PIN 1u 368 #define P14_1_NUM 1u 369 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 370 #define P14_2_PORT GPIO_PRT14 371 #define P14_2_PIN 2u 372 #define P14_2_NUM 2u 373 #define P14_2_AMUXSEGMENT AMUXBUS_MAIN 374 #define P14_3_PORT GPIO_PRT14 375 #define P14_3_PIN 3u 376 #define P14_3_NUM 3u 377 #define P14_3_AMUXSEGMENT AMUXBUS_MAIN 378 #define P14_4_PORT GPIO_PRT14 379 #define P14_4_PIN 4u 380 #define P14_4_NUM 4u 381 #define P14_4_AMUXSEGMENT AMUXBUS_MAIN 382 #define P14_5_PORT GPIO_PRT14 383 #define P14_5_PIN 5u 384 #define P14_5_NUM 5u 385 #define P14_5_AMUXSEGMENT AMUXBUS_MAIN 386 387 /* PORT 15 (GPIO) */ 388 #define P15_0_PORT GPIO_PRT15 389 #define P15_0_PIN 0u 390 #define P15_0_NUM 0u 391 #define P15_0_AMUXSEGMENT AMUXBUS_MAIN 392 #define P15_1_PORT GPIO_PRT15 393 #define P15_1_PIN 1u 394 #define P15_1_NUM 1u 395 #define P15_1_AMUXSEGMENT AMUXBUS_MAIN 396 #define P15_2_PORT GPIO_PRT15 397 #define P15_2_PIN 2u 398 #define P15_2_NUM 2u 399 #define P15_2_AMUXSEGMENT AMUXBUS_MAIN 400 #define P15_3_PORT GPIO_PRT15 401 #define P15_3_PIN 3u 402 #define P15_3_NUM 3u 403 #define P15_3_AMUXSEGMENT AMUXBUS_MAIN 404 405 /* PORT 16 (GPIO) */ 406 #define P16_0_PORT GPIO_PRT16 407 #define P16_0_PIN 0u 408 #define P16_0_NUM 0u 409 #define P16_0_AMUXSEGMENT AMUXBUS_MAIN 410 #define P16_1_PORT GPIO_PRT16 411 #define P16_1_PIN 1u 412 #define P16_1_NUM 1u 413 #define P16_1_AMUXSEGMENT AMUXBUS_MAIN 414 #define P16_2_PORT GPIO_PRT16 415 #define P16_2_PIN 2u 416 #define P16_2_NUM 2u 417 #define P16_2_AMUXSEGMENT AMUXBUS_MAIN 418 419 /* PORT 17 (GPIO) */ 420 #define P17_0_PORT GPIO_PRT17 421 #define P17_0_PIN 0u 422 #define P17_0_NUM 0u 423 #define P17_0_AMUXSEGMENT AMUXBUS_MAIN 424 #define P17_1_PORT GPIO_PRT17 425 #define P17_1_PIN 1u 426 #define P17_1_NUM 1u 427 #define P17_1_AMUXSEGMENT AMUXBUS_MAIN 428 #define P17_2_PORT GPIO_PRT17 429 #define P17_2_PIN 2u 430 #define P17_2_NUM 2u 431 #define P17_2_AMUXSEGMENT AMUXBUS_MAIN 432 #define P17_3_PORT GPIO_PRT17 433 #define P17_3_PIN 3u 434 #define P17_3_NUM 3u 435 #define P17_3_AMUXSEGMENT AMUXBUS_MAIN 436 #define P17_4_PORT GPIO_PRT17 437 #define P17_4_PIN 4u 438 #define P17_4_NUM 4u 439 #define P17_4_AMUXSEGMENT AMUXBUS_MAIN 440 441 /* PORT 18 (GPIO) */ 442 #define P18_0_PORT GPIO_PRT18 443 #define P18_0_PIN 0u 444 #define P18_0_NUM 0u 445 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 446 #define P18_1_PORT GPIO_PRT18 447 #define P18_1_PIN 1u 448 #define P18_1_NUM 1u 449 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 450 #define P18_2_PORT GPIO_PRT18 451 #define P18_2_PIN 2u 452 #define P18_2_NUM 2u 453 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 454 #define P18_3_PORT GPIO_PRT18 455 #define P18_3_PIN 3u 456 #define P18_3_NUM 3u 457 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 458 #define P18_4_PORT GPIO_PRT18 459 #define P18_4_PIN 4u 460 #define P18_4_NUM 4u 461 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 462 #define P18_5_PORT GPIO_PRT18 463 #define P18_5_PIN 5u 464 #define P18_5_NUM 5u 465 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 466 #define P18_6_PORT GPIO_PRT18 467 #define P18_6_PIN 6u 468 #define P18_6_NUM 6u 469 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 470 #define P18_7_PORT GPIO_PRT18 471 #define P18_7_PIN 7u 472 #define P18_7_NUM 7u 473 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 474 475 /* PORT 19 (GPIO) */ 476 #define P19_0_PORT GPIO_PRT19 477 #define P19_0_PIN 0u 478 #define P19_0_NUM 0u 479 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 480 #define P19_1_PORT GPIO_PRT19 481 #define P19_1_PIN 1u 482 #define P19_1_NUM 1u 483 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 484 #define P19_2_PORT GPIO_PRT19 485 #define P19_2_PIN 2u 486 #define P19_2_NUM 2u 487 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 488 #define P19_3_PORT GPIO_PRT19 489 #define P19_3_PIN 3u 490 #define P19_3_NUM 3u 491 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 492 #define P19_4_PORT GPIO_PRT19 493 #define P19_4_PIN 4u 494 #define P19_4_NUM 4u 495 #define P19_4_AMUXSEGMENT AMUXBUS_MAIN 496 497 /* PORT 20 (GPIO) */ 498 #define P20_0_PORT GPIO_PRT20 499 #define P20_0_PIN 0u 500 #define P20_0_NUM 0u 501 #define P20_0_AMUXSEGMENT AMUXBUS_MAIN 502 #define P20_1_PORT GPIO_PRT20 503 #define P20_1_PIN 1u 504 #define P20_1_NUM 1u 505 #define P20_1_AMUXSEGMENT AMUXBUS_MAIN 506 #define P20_2_PORT GPIO_PRT20 507 #define P20_2_PIN 2u 508 #define P20_2_NUM 2u 509 #define P20_2_AMUXSEGMENT AMUXBUS_MAIN 510 #define P20_3_PORT GPIO_PRT20 511 #define P20_3_PIN 3u 512 #define P20_3_NUM 3u 513 #define P20_3_AMUXSEGMENT AMUXBUS_MAIN 514 515 /* PORT 21 (GPIO) */ 516 #define P21_0_PORT GPIO_PRT21 517 #define P21_0_PIN 0u 518 #define P21_0_NUM 0u 519 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 520 #define P21_1_PORT GPIO_PRT21 521 #define P21_1_PIN 1u 522 #define P21_1_NUM 1u 523 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 524 #define P21_2_PORT GPIO_PRT21 525 #define P21_2_PIN 2u 526 #define P21_2_NUM 2u 527 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 528 #define P21_3_PORT GPIO_PRT21 529 #define P21_3_PIN 3u 530 #define P21_3_NUM 3u 531 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 532 #define P21_5_PORT GPIO_PRT21 533 #define P21_5_PIN 5u 534 #define P21_5_NUM 5u 535 #define P21_5_AMUXSEGMENT AMUXBUS_MAIN 536 #define P21_6_PORT GPIO_PRT21 537 #define P21_6_PIN 6u 538 #define P21_6_NUM 6u 539 #define P21_6_AMUXSEGMENT AMUXBUS_MAIN 540 541 /* PORT 22 (GPIO) */ 542 #define P22_0_PORT GPIO_PRT22 543 #define P22_0_PIN 0u 544 #define P22_0_NUM 0u 545 #define P22_0_AMUXSEGMENT AMUXBUS_MAIN 546 #define P22_1_PORT GPIO_PRT22 547 #define P22_1_PIN 1u 548 #define P22_1_NUM 1u 549 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 550 #define P22_2_PORT GPIO_PRT22 551 #define P22_2_PIN 2u 552 #define P22_2_NUM 2u 553 #define P22_2_AMUXSEGMENT AMUXBUS_MAIN 554 #define P22_3_PORT GPIO_PRT22 555 #define P22_3_PIN 3u 556 #define P22_3_NUM 3u 557 #define P22_3_AMUXSEGMENT AMUXBUS_MAIN 558 #define P22_4_PORT GPIO_PRT22 559 #define P22_4_PIN 4u 560 #define P22_4_NUM 4u 561 #define P22_4_AMUXSEGMENT AMUXBUS_MAIN 562 #define P22_5_PORT GPIO_PRT22 563 #define P22_5_PIN 5u 564 #define P22_5_NUM 5u 565 #define P22_5_AMUXSEGMENT AMUXBUS_MAIN 566 #define P22_6_PORT GPIO_PRT22 567 #define P22_6_PIN 6u 568 #define P22_6_NUM 6u 569 #define P22_6_AMUXSEGMENT AMUXBUS_MAIN 570 571 /* PORT 23 (GPIO) */ 572 #define P23_0_PORT GPIO_PRT23 573 #define P23_0_PIN 0u 574 #define P23_0_NUM 0u 575 #define P23_0_AMUXSEGMENT AMUXBUS_MAIN 576 #define P23_1_PORT GPIO_PRT23 577 #define P23_1_PIN 1u 578 #define P23_1_NUM 1u 579 #define P23_1_AMUXSEGMENT AMUXBUS_MAIN 580 #define P23_3_PORT GPIO_PRT23 581 #define P23_3_PIN 3u 582 #define P23_3_NUM 3u 583 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 584 #define P23_4_PORT GPIO_PRT23 585 #define P23_4_PIN 4u 586 #define P23_4_NUM 4u 587 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 588 #define P23_5_PORT GPIO_PRT23 589 #define P23_5_PIN 5u 590 #define P23_5_NUM 5u 591 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 592 #define P23_6_PORT GPIO_PRT23 593 #define P23_6_PIN 6u 594 #define P23_6_NUM 6u 595 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 596 #define P23_7_PORT GPIO_PRT23 597 #define P23_7_PIN 7u 598 #define P23_7_NUM 7u 599 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 600 601 /* Analog Connections */ 602 #define PASS0_I_TEMP_KELVIN_PORT 21u 603 #define PASS0_I_TEMP_KELVIN_PIN 2u 604 #define PASS0_SARMUX_MOTOR0_PORT 11u 605 #define PASS0_SARMUX_MOTOR0_PIN 0u 606 #define PASS0_SARMUX_MOTOR1_PORT 11u 607 #define PASS0_SARMUX_MOTOR1_PIN 1u 608 #define PASS0_SARMUX_MOTOR2_PORT 11u 609 #define PASS0_SARMUX_MOTOR2_PIN 2u 610 #define PASS0_SARMUX_PADS0_PORT 6u 611 #define PASS0_SARMUX_PADS0_PIN 0u 612 #define PASS0_SARMUX_PADS1_PORT 6u 613 #define PASS0_SARMUX_PADS1_PIN 1u 614 #define PASS0_SARMUX_PADS10_PORT 7u 615 #define PASS0_SARMUX_PADS10_PIN 2u 616 #define PASS0_SARMUX_PADS11_PORT 7u 617 #define PASS0_SARMUX_PADS11_PIN 3u 618 #define PASS0_SARMUX_PADS12_PORT 7u 619 #define PASS0_SARMUX_PADS12_PIN 4u 620 #define PASS0_SARMUX_PADS13_PORT 7u 621 #define PASS0_SARMUX_PADS13_PIN 5u 622 #define PASS0_SARMUX_PADS14_PORT 7u 623 #define PASS0_SARMUX_PADS14_PIN 6u 624 #define PASS0_SARMUX_PADS15_PORT 7u 625 #define PASS0_SARMUX_PADS15_PIN 7u 626 #define PASS0_SARMUX_PADS16_PORT 8u 627 #define PASS0_SARMUX_PADS16_PIN 1u 628 #define PASS0_SARMUX_PADS17_PORT 8u 629 #define PASS0_SARMUX_PADS17_PIN 2u 630 #define PASS0_SARMUX_PADS18_PORT 8u 631 #define PASS0_SARMUX_PADS18_PIN 3u 632 #define PASS0_SARMUX_PADS2_PORT 6u 633 #define PASS0_SARMUX_PADS2_PIN 2u 634 #define PASS0_SARMUX_PADS20_PORT 9u 635 #define PASS0_SARMUX_PADS20_PIN 0u 636 #define PASS0_SARMUX_PADS21_PORT 9u 637 #define PASS0_SARMUX_PADS21_PIN 1u 638 #define PASS0_SARMUX_PADS3_PORT 6u 639 #define PASS0_SARMUX_PADS3_PIN 3u 640 #define PASS0_SARMUX_PADS32_PORT 10u 641 #define PASS0_SARMUX_PADS32_PIN 4u 642 #define PASS0_SARMUX_PADS36_PORT 12u 643 #define PASS0_SARMUX_PADS36_PIN 0u 644 #define PASS0_SARMUX_PADS37_PORT 12u 645 #define PASS0_SARMUX_PADS37_PIN 1u 646 #define PASS0_SARMUX_PADS38_PORT 12u 647 #define PASS0_SARMUX_PADS38_PIN 2u 648 #define PASS0_SARMUX_PADS39_PORT 12u 649 #define PASS0_SARMUX_PADS39_PIN 3u 650 #define PASS0_SARMUX_PADS4_PORT 6u 651 #define PASS0_SARMUX_PADS4_PIN 4u 652 #define PASS0_SARMUX_PADS40_PORT 12u 653 #define PASS0_SARMUX_PADS40_PIN 4u 654 #define PASS0_SARMUX_PADS41_PORT 12u 655 #define PASS0_SARMUX_PADS41_PIN 5u 656 #define PASS0_SARMUX_PADS44_PORT 13u 657 #define PASS0_SARMUX_PADS44_PIN 0u 658 #define PASS0_SARMUX_PADS45_PORT 13u 659 #define PASS0_SARMUX_PADS45_PIN 1u 660 #define PASS0_SARMUX_PADS46_PORT 13u 661 #define PASS0_SARMUX_PADS46_PIN 2u 662 #define PASS0_SARMUX_PADS47_PORT 13u 663 #define PASS0_SARMUX_PADS47_PIN 3u 664 #define PASS0_SARMUX_PADS48_PORT 13u 665 #define PASS0_SARMUX_PADS48_PIN 4u 666 #define PASS0_SARMUX_PADS49_PORT 13u 667 #define PASS0_SARMUX_PADS49_PIN 5u 668 #define PASS0_SARMUX_PADS5_PORT 6u 669 #define PASS0_SARMUX_PADS5_PIN 5u 670 #define PASS0_SARMUX_PADS50_PORT 13u 671 #define PASS0_SARMUX_PADS50_PIN 6u 672 #define PASS0_SARMUX_PADS51_PORT 13u 673 #define PASS0_SARMUX_PADS51_PIN 7u 674 #define PASS0_SARMUX_PADS52_PORT 14u 675 #define PASS0_SARMUX_PADS52_PIN 0u 676 #define PASS0_SARMUX_PADS53_PORT 14u 677 #define PASS0_SARMUX_PADS53_PIN 1u 678 #define PASS0_SARMUX_PADS54_PORT 14u 679 #define PASS0_SARMUX_PADS54_PIN 2u 680 #define PASS0_SARMUX_PADS55_PORT 14u 681 #define PASS0_SARMUX_PADS55_PIN 3u 682 #define PASS0_SARMUX_PADS56_PORT 14u 683 #define PASS0_SARMUX_PADS56_PIN 4u 684 #define PASS0_SARMUX_PADS57_PORT 14u 685 #define PASS0_SARMUX_PADS57_PIN 5u 686 #define PASS0_SARMUX_PADS6_PORT 6u 687 #define PASS0_SARMUX_PADS6_PIN 6u 688 #define PASS0_SARMUX_PADS60_PORT 15u 689 #define PASS0_SARMUX_PADS60_PIN 0u 690 #define PASS0_SARMUX_PADS61_PORT 15u 691 #define PASS0_SARMUX_PADS61_PIN 1u 692 #define PASS0_SARMUX_PADS62_PORT 15u 693 #define PASS0_SARMUX_PADS62_PIN 2u 694 #define PASS0_SARMUX_PADS63_PORT 15u 695 #define PASS0_SARMUX_PADS63_PIN 3u 696 #define PASS0_SARMUX_PADS64_PORT 18u 697 #define PASS0_SARMUX_PADS64_PIN 0u 698 #define PASS0_SARMUX_PADS65_PORT 18u 699 #define PASS0_SARMUX_PADS65_PIN 1u 700 #define PASS0_SARMUX_PADS66_PORT 18u 701 #define PASS0_SARMUX_PADS66_PIN 2u 702 #define PASS0_SARMUX_PADS67_PORT 18u 703 #define PASS0_SARMUX_PADS67_PIN 3u 704 #define PASS0_SARMUX_PADS68_PORT 18u 705 #define PASS0_SARMUX_PADS68_PIN 4u 706 #define PASS0_SARMUX_PADS69_PORT 18u 707 #define PASS0_SARMUX_PADS69_PIN 5u 708 #define PASS0_SARMUX_PADS7_PORT 6u 709 #define PASS0_SARMUX_PADS7_PIN 7u 710 #define PASS0_SARMUX_PADS70_PORT 18u 711 #define PASS0_SARMUX_PADS70_PIN 6u 712 #define PASS0_SARMUX_PADS71_PORT 18u 713 #define PASS0_SARMUX_PADS71_PIN 7u 714 #define PASS0_SARMUX_PADS8_PORT 7u 715 #define PASS0_SARMUX_PADS8_PIN 0u 716 #define PASS0_SARMUX_PADS9_PORT 7u 717 #define PASS0_SARMUX_PADS9_PIN 1u 718 #define PASS0_VB_TEMP_KELVIN_PORT 10u 719 #define PASS0_VB_TEMP_KELVIN_PIN 4u 720 #define PASS0_VE_TEMP_KELVIN_PORT 23u 721 #define PASS0_VE_TEMP_KELVIN_PIN 4u 722 #define SRSS_ADFT_PIN0_PORT 23u 723 #define SRSS_ADFT_PIN0_PIN 4u 724 #define SRSS_ADFT_PIN1_PORT 23u 725 #define SRSS_ADFT_PIN1_PIN 3u 726 #define SRSS_ECO_IN_PORT 21u 727 #define SRSS_ECO_IN_PIN 2u 728 #define SRSS_ECO_OUT_PORT 21u 729 #define SRSS_ECO_OUT_PIN 3u 730 #define SRSS_VEXT_REF_REG_PORT 21u 731 #define SRSS_VEXT_REF_REG_PIN 3u 732 #define SRSS_WCO_IN_PORT 21u 733 #define SRSS_WCO_IN_PIN 0u 734 #define SRSS_WCO_OUT_PORT 21u 735 #define SRSS_WCO_OUT_PIN 1u 736 737 /* HSIOM Connections */ 738 typedef enum 739 { 740 /* Generic HSIOM connections */ 741 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 742 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 743 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 744 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 745 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 746 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 747 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 748 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 749 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 750 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 751 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 752 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 753 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 754 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 755 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 756 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 757 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 758 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 759 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 760 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 761 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 762 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 763 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 764 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 765 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 766 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 767 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 768 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 769 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 770 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 771 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 772 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 773 774 /* P0.0 */ 775 P0_0_GPIO = 0, /* GPIO controls 'out' */ 776 P0_0_AMUXA = 4, /* Analog mux bus A */ 777 P0_0_AMUXB = 5, /* Analog mux bus B */ 778 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 779 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 780 P0_0_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:1 */ 781 P0_0_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ 782 P0_0_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:1 */ 783 P0_0_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:1 */ 784 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 785 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 786 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 787 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 788 789 /* P0.1 */ 790 P0_1_GPIO = 0, /* GPIO controls 'out' */ 791 P0_1_AMUXA = 4, /* Analog mux bus A */ 792 P0_1_AMUXB = 5, /* Analog mux bus B */ 793 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 794 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 795 P0_1_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:1 */ 796 P0_1_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:1 */ 797 P0_1_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:1 */ 798 P0_1_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:1 */ 799 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 800 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 801 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 802 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 803 804 /* P0.2 */ 805 P0_2_GPIO = 0, /* GPIO controls 'out' */ 806 P0_2_AMUXA = 4, /* Analog mux bus A */ 807 P0_2_AMUXB = 5, /* Analog mux bus B */ 808 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 809 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 810 P0_2_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:1 */ 811 P0_2_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:1 */ 812 P0_2_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:1 */ 813 P0_2_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:1 */ 814 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 815 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 816 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 817 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 818 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 819 820 /* P0.3 */ 821 P0_3_GPIO = 0, /* GPIO controls 'out' */ 822 P0_3_AMUXA = 4, /* Analog mux bus A */ 823 P0_3_AMUXB = 5, /* Analog mux bus B */ 824 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 825 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 826 P0_3_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:1 */ 827 P0_3_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:1 */ 828 P0_3_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:1 */ 829 P0_3_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:1 */ 830 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 831 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 832 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 833 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 834 835 /* P1.0 */ 836 P1_0_GPIO = 0, /* GPIO controls 'out' */ 837 P1_0_AMUXA = 4, /* Analog mux bus A */ 838 P1_0_AMUXB = 5, /* Analog mux bus B */ 839 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 840 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 841 P1_0_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:1 */ 842 P1_0_TCPWM0_LINE_COMPL13 = 9, /* Digital Active - tcpwm[0].line_compl[13]:1 */ 843 P1_0_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:1 */ 844 P1_0_TCPWM0_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[40]:1 */ 845 P1_0_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 846 P1_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 847 848 /* P1.1 */ 849 P1_1_GPIO = 0, /* GPIO controls 'out' */ 850 P1_1_AMUXA = 4, /* Analog mux bus A */ 851 P1_1_AMUXB = 5, /* Analog mux bus B */ 852 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 853 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 854 P1_1_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:1 */ 855 P1_1_TCPWM0_LINE_COMPL12 = 9, /* Digital Active - tcpwm[0].line_compl[12]:1 */ 856 P1_1_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:1 */ 857 P1_1_TCPWM0_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:1 */ 858 P1_1_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 859 P1_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 860 861 /* P2.0 */ 862 P2_0_GPIO = 0, /* GPIO controls 'out' */ 863 P2_0_AMUXA = 4, /* Analog mux bus A */ 864 P2_0_AMUXB = 5, /* Analog mux bus B */ 865 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 866 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 867 P2_0_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 868 P2_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:1 */ 869 P2_0_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ 870 P2_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ 871 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 872 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 873 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 874 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 875 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 876 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 877 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 878 879 /* P2.1 */ 880 P2_1_GPIO = 0, /* GPIO controls 'out' */ 881 P2_1_AMUXA = 4, /* Analog mux bus A */ 882 P2_1_AMUXB = 5, /* Analog mux bus B */ 883 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 884 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 885 P2_1_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 886 P2_1_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 887 P2_1_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:1 */ 888 P2_1_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ 889 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 890 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 891 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 892 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 893 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 894 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 895 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 896 897 /* P2.2 */ 898 P2_2_GPIO = 0, /* GPIO controls 'out' */ 899 P2_2_AMUXA = 4, /* Analog mux bus A */ 900 P2_2_AMUXB = 5, /* Analog mux bus B */ 901 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 902 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 903 P2_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 904 P2_2_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 905 P2_2_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:1 */ 906 P2_2_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:1 */ 907 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 908 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 909 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 910 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 911 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 912 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 913 914 /* P2.3 */ 915 P2_3_GPIO = 0, /* GPIO controls 'out' */ 916 P2_3_AMUXA = 4, /* Analog mux bus A */ 917 P2_3_AMUXB = 5, /* Analog mux bus B */ 918 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 919 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 920 P2_3_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 921 P2_3_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 922 P2_3_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:1 */ 923 P2_3_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:1 */ 924 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 925 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 926 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 927 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 928 929 /* P2.4 */ 930 P2_4_GPIO = 0, /* GPIO controls 'out' */ 931 P2_4_AMUXA = 4, /* Analog mux bus A */ 932 P2_4_AMUXB = 5, /* Analog mux bus B */ 933 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 934 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 935 P2_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 936 P2_4_TCPWM0_LINE_COMPL4 = 9, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 937 P2_4_TCPWM0_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[9]:1 */ 938 P2_4_TCPWM0_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[13]:1 */ 939 P2_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:0 */ 940 P2_4_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:1 */ 941 P2_4_PERI_TR_IO_INPUT6 = 26, /* Digital Active - peri.tr_io_input[6]:0 */ 942 943 /* P3.0 */ 944 P3_0_GPIO = 0, /* GPIO controls 'out' */ 945 P3_0_AMUXA = 4, /* Analog mux bus A */ 946 P3_0_AMUXB = 5, /* Analog mux bus B */ 947 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 948 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 949 P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 950 P3_0_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 951 P3_0_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ 952 P3_0_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:1 */ 953 P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ 954 P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ 955 P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 956 957 /* P3.1 */ 958 P3_1_GPIO = 0, /* GPIO controls 'out' */ 959 P3_1_AMUXA = 4, /* Analog mux bus A */ 960 P3_1_AMUXB = 5, /* Analog mux bus B */ 961 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 962 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 963 P3_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 964 P3_1_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 965 P3_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ 966 P3_1_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:1 */ 967 P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ 968 P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ 969 P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ 970 P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 971 972 /* P3.2 */ 973 P3_2_GPIO = 0, /* GPIO controls 'out' */ 974 P3_2_AMUXA = 4, /* Analog mux bus A */ 975 P3_2_AMUXB = 5, /* Analog mux bus B */ 976 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 977 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 978 P3_2_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:1 */ 979 P3_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 980 P3_2_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:1 */ 981 P3_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ 982 P3_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:0 */ 983 P3_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:0 */ 984 P3_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:0 */ 985 986 /* P3.3 */ 987 P3_3_GPIO = 0, /* GPIO controls 'out' */ 988 P3_3_AMUXA = 4, /* Analog mux bus A */ 989 P3_3_AMUXB = 5, /* Analog mux bus B */ 990 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 991 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 992 P3_3_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:1 */ 993 P3_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ 994 P3_3_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:1 */ 995 P3_3_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:1 */ 996 P3_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:0 */ 997 P3_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:0 */ 998 999 /* P3.4 */ 1000 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1001 P3_4_AMUXA = 4, /* Analog mux bus A */ 1002 P3_4_AMUXB = 5, /* Analog mux bus B */ 1003 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1004 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1005 P3_4_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:1 */ 1006 P3_4_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ 1007 P3_4_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:1 */ 1008 P3_4_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:1 */ 1009 P3_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:0 */ 1010 1011 /* P4.0 */ 1012 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1013 P4_0_AMUXA = 4, /* Analog mux bus A */ 1014 P4_0_AMUXB = 5, /* Analog mux bus B */ 1015 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1016 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1017 P4_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 1018 P4_0_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ 1019 P4_0_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:0 */ 1020 P4_0_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:1 */ 1021 P4_0_PASS0_SAR_EXT_MUX_SEL0 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[0] */ 1022 P4_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:0 */ 1023 P4_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:0 */ 1024 P4_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:1 */ 1025 P4_0_PERI_TR_IO_INPUT10 = 26, /* Digital Active - peri.tr_io_input[10]:0 */ 1026 1027 /* P4.1 */ 1028 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1029 P4_1_AMUXA = 4, /* Analog mux bus A */ 1030 P4_1_AMUXB = 5, /* Analog mux bus B */ 1031 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1032 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1033 P4_1_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 1034 P4_1_TCPWM0_LINE_COMPL4 = 9, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 1035 P4_1_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:0 */ 1036 P4_1_TCPWM0_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[13]:0 */ 1037 P4_1_PASS0_SAR_EXT_MUX_SEL1 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[1] */ 1038 P4_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:0 */ 1039 P4_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:0 */ 1040 P4_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:0 */ 1041 P4_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:1 */ 1042 P4_1_PERI_TR_IO_INPUT11 = 26, /* Digital Active - peri.tr_io_input[11]:0 */ 1043 1044 /* P5.0 */ 1045 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1046 P5_0_AMUXA = 4, /* Analog mux bus A */ 1047 P5_0_AMUXB = 5, /* Analog mux bus B */ 1048 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1049 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1050 P5_0_TCPWM0_LINE9 = 8, /* Digital Active - tcpwm[0].line[9]:0 */ 1051 P5_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:0 */ 1052 P5_0_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ 1053 P5_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ 1054 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 1055 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 1056 1057 /* P5.1 */ 1058 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1059 P5_1_AMUXA = 4, /* Analog mux bus A */ 1060 P5_1_AMUXB = 5, /* Analog mux bus B */ 1061 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1062 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1063 P5_1_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:0 */ 1064 P5_1_TCPWM0_LINE_COMPL9 = 9, /* Digital Active - tcpwm[0].line_compl[9]:0 */ 1065 P5_1_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ 1066 P5_1_TCPWM0_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ 1067 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 1068 1069 /* P5.2 */ 1070 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1071 P5_2_AMUXA = 4, /* Analog mux bus A */ 1072 P5_2_AMUXB = 5, /* Analog mux bus B */ 1073 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1074 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1075 P5_2_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:0 */ 1076 P5_2_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:0 */ 1077 P5_2_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:0 */ 1078 P5_2_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:0 */ 1079 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 1080 1081 /* P5.3 */ 1082 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1083 P5_3_AMUXA = 4, /* Analog mux bus A */ 1084 P5_3_AMUXB = 5, /* Analog mux bus B */ 1085 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1086 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1087 P5_3_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:0 */ 1088 P5_3_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:0 */ 1089 P5_3_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:0 */ 1090 P5_3_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:0 */ 1091 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 1092 1093 /* P5.4 */ 1094 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1095 P5_4_AMUXA = 4, /* Analog mux bus A */ 1096 P5_4_AMUXB = 5, /* Analog mux bus B */ 1097 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1098 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1099 P5_4_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:0 */ 1100 P5_4_TCPWM0_LINE_COMPL12 = 9, /* Digital Active - tcpwm[0].line_compl[12]:0 */ 1101 P5_4_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:0 */ 1102 P5_4_TCPWM0_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:0 */ 1103 P5_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:0 */ 1104 1105 /* P6.0 */ 1106 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1107 P6_0_AMUXA = 4, /* Analog mux bus A */ 1108 P6_0_AMUXB = 5, /* Analog mux bus B */ 1109 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1110 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1111 P6_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ 1112 P6_0_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:0 */ 1113 P6_0_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:0 */ 1114 P6_0_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:0 */ 1115 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 1116 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 1117 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 1118 1119 /* P6.1 */ 1120 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1121 P6_1_AMUXA = 4, /* Analog mux bus A */ 1122 P6_1_AMUXB = 5, /* Analog mux bus B */ 1123 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1124 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1125 P6_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 1126 P6_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 1127 P6_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 1128 P6_1_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:0 */ 1129 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 1130 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 1131 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 1132 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 1133 1134 /* P6.2 */ 1135 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1136 P6_2_AMUXA = 4, /* Analog mux bus A */ 1137 P6_2_AMUXB = 5, /* Analog mux bus B */ 1138 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1139 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1140 P6_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ 1141 P6_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 1142 P6_2_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:0 */ 1143 P6_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 1144 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 1145 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 1146 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 1147 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 1148 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 1149 1150 /* P6.3 */ 1151 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1152 P6_3_AMUXA = 4, /* Analog mux bus A */ 1153 P6_3_AMUXB = 5, /* Analog mux bus B */ 1154 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1155 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1156 P6_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 1157 P6_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 1158 P6_3_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 1159 P6_3_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:0 */ 1160 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 1161 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 1162 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 1163 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 1164 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 1165 1166 /* P6.4 */ 1167 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1168 P6_4_AMUXA = 4, /* Analog mux bus A */ 1169 P6_4_AMUXB = 5, /* Analog mux bus B */ 1170 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1171 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1172 P6_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ 1173 P6_4_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 1174 P6_4_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:0 */ 1175 P6_4_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:0 */ 1176 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 1177 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 1178 1179 /* P6.5 */ 1180 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1181 P6_5_AMUXA = 4, /* Analog mux bus A */ 1182 P6_5_AMUXB = 5, /* Analog mux bus B */ 1183 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1184 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1185 P6_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 1186 P6_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 1187 P6_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:0 */ 1188 P6_5_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:0 */ 1189 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 1190 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 1191 1192 /* P6.6 */ 1193 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1194 P6_6_AMUXA = 4, /* Analog mux bus A */ 1195 P6_6_AMUXB = 5, /* Analog mux bus B */ 1196 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1197 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1198 P6_6_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:0 */ 1199 P6_6_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 1200 P6_6_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:0 */ 1201 P6_6_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:0 */ 1202 P6_6_SCB4_SPI_SELECT3 = 19, /* Digital Active - scb[4].spi_select3:0 */ 1203 P6_6_PERI_TR_IO_INPUT8 = 26, /* Digital Active - peri.tr_io_input[8]:0 */ 1204 1205 /* P6.7 */ 1206 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1207 P6_7_AMUXA = 4, /* Analog mux bus A */ 1208 P6_7_AMUXB = 5, /* Analog mux bus B */ 1209 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1210 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1211 P6_7_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 1212 P6_7_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ 1213 P6_7_TCPWM0_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[9]:0 */ 1214 P6_7_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:0 */ 1215 P6_7_PERI_TR_IO_INPUT9 = 26, /* Digital Active - peri.tr_io_input[9]:0 */ 1216 1217 /* P7.0 */ 1218 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1219 P7_0_AMUXA = 4, /* Analog mux bus A */ 1220 P7_0_AMUXB = 5, /* Analog mux bus B */ 1221 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1222 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1223 P7_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ 1224 P7_0_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 1225 P7_0_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:0 */ 1226 P7_0_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:0 */ 1227 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 1228 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 1229 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 1230 1231 /* P7.1 */ 1232 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1233 P7_1_AMUXA = 4, /* Analog mux bus A */ 1234 P7_1_AMUXB = 5, /* Analog mux bus B */ 1235 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1236 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1237 P7_1_TCPWM0_LINE15 = 8, /* Digital Active - tcpwm[0].line[15]:0 */ 1238 P7_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 1239 P7_1_TCPWM0_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[45]:0 */ 1240 P7_1_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:0 */ 1241 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 1242 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 1243 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 1244 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 1245 1246 /* P7.2 */ 1247 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1248 P7_2_AMUXA = 4, /* Analog mux bus A */ 1249 P7_2_AMUXB = 5, /* Analog mux bus B */ 1250 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1251 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1252 P7_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ 1253 P7_2_TCPWM0_LINE_COMPL15 = 9, /* Digital Active - tcpwm[0].line_compl[15]:0 */ 1254 P7_2_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:0 */ 1255 P7_2_TCPWM0_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[46]:0 */ 1256 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 1257 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 1258 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 1259 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 1260 1261 /* P7.3 */ 1262 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1263 P7_3_AMUXA = 4, /* Analog mux bus A */ 1264 P7_3_AMUXB = 5, /* Analog mux bus B */ 1265 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1266 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1267 P7_3_TCPWM0_LINE16 = 8, /* Digital Active - tcpwm[0].line[16]:0 */ 1268 P7_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 1269 P7_3_TCPWM0_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[48]:0 */ 1270 P7_3_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:0 */ 1271 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 1272 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 1273 1274 /* P7.4 */ 1275 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1276 P7_4_AMUXA = 4, /* Analog mux bus A */ 1277 P7_4_AMUXB = 5, /* Analog mux bus B */ 1278 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1279 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1280 P7_4_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:0 */ 1281 P7_4_TCPWM0_LINE_COMPL16 = 9, /* Digital Active - tcpwm[0].line_compl[16]:0 */ 1282 P7_4_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:0 */ 1283 P7_4_TCPWM0_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[49]:0 */ 1284 P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ 1285 1286 /* P7.5 */ 1287 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1288 P7_5_AMUXA = 4, /* Analog mux bus A */ 1289 P7_5_AMUXB = 5, /* Analog mux bus B */ 1290 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1291 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1292 P7_5_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:0 */ 1293 P7_5_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 1294 P7_5_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:0 */ 1295 P7_5_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:0 */ 1296 P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ 1297 1298 /* P7.6 */ 1299 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1300 P7_6_AMUXA = 4, /* Analog mux bus A */ 1301 P7_6_AMUXB = 5, /* Analog mux bus B */ 1302 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1303 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1304 P7_6_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:0 */ 1305 P7_6_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:0 */ 1306 P7_6_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:0 */ 1307 P7_6_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:0 */ 1308 P7_6_PERI_TR_IO_INPUT16 = 26, /* Digital Active - peri.tr_io_input[16]:0 */ 1309 1310 /* P7.7 */ 1311 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1312 P7_7_AMUXA = 4, /* Analog mux bus A */ 1313 P7_7_AMUXB = 5, /* Analog mux bus B */ 1314 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1315 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1316 P7_7_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:0 */ 1317 P7_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ 1318 P7_7_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:0 */ 1319 P7_7_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:0 */ 1320 P7_7_PERI_TR_IO_INPUT17 = 26, /* Digital Active - peri.tr_io_input[17]:0 */ 1321 1322 /* P8.0 */ 1323 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1324 P8_0_AMUXA = 4, /* Analog mux bus A */ 1325 P8_0_AMUXB = 5, /* Analog mux bus B */ 1326 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1327 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1328 P8_0_TCPWM0_LINE19 = 8, /* Digital Active - tcpwm[0].line[19]:0 */ 1329 P8_0_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:0 */ 1330 P8_0_TCPWM0_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[57]:0 */ 1331 P8_0_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:0 */ 1332 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 1333 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 1334 1335 /* P8.1 */ 1336 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1337 P8_1_AMUXA = 4, /* Analog mux bus A */ 1338 P8_1_AMUXB = 5, /* Analog mux bus B */ 1339 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1340 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1341 P8_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ 1342 P8_1_TCPWM0_LINE_COMPL19 = 9, /* Digital Active - tcpwm[0].line_compl[19]:0 */ 1343 P8_1_TCPWM0_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[60]:0 */ 1344 P8_1_TCPWM0_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[58]:0 */ 1345 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 1346 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 1347 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 1348 1349 /* P8.2 */ 1350 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1351 P8_2_AMUXA = 4, /* Analog mux bus A */ 1352 P8_2_AMUXB = 5, /* Analog mux bus B */ 1353 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1354 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1355 P8_2_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:0 */ 1356 P8_2_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:0 */ 1357 P8_2_TCPWM0_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[63]:0 */ 1358 P8_2_TCPWM0_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[61]:0 */ 1359 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 1360 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 1361 1362 /* P8.3 */ 1363 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1364 P8_3_AMUXA = 4, /* Analog mux bus A */ 1365 P8_3_AMUXB = 5, /* Analog mux bus B */ 1366 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1367 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1368 P8_3_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:0 */ 1369 P8_3_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:0 */ 1370 P8_3_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:0 */ 1371 P8_3_TCPWM0_TR_ONE_CNT_IN64 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[64]:0 */ 1372 P8_3_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:1 */ 1373 1374 /* P9.0 */ 1375 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1376 P9_0_AMUXA = 4, /* Analog mux bus A */ 1377 P9_0_AMUXB = 5, /* Analog mux bus B */ 1378 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1379 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1380 P9_0_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:0 */ 1381 P9_0_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:0 */ 1382 P9_0_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:0 */ 1383 P9_0_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:0 */ 1384 1385 /* P9.1 */ 1386 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1387 P9_1_AMUXA = 4, /* Analog mux bus A */ 1388 P9_1_AMUXB = 5, /* Analog mux bus B */ 1389 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1390 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1391 P9_1_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:0 */ 1392 P9_1_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:0 */ 1393 P9_1_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:0 */ 1394 P9_1_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:0 */ 1395 1396 /* P10.0 */ 1397 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1398 P10_0_AMUXA = 4, /* Analog mux bus A */ 1399 P10_0_AMUXB = 5, /* Analog mux bus B */ 1400 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1401 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1402 P10_0_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:0 */ 1403 P10_0_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:0 */ 1404 P10_0_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:0 */ 1405 P10_0_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:0 */ 1406 P10_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:1 */ 1407 P10_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:1 */ 1408 P10_0_PERI_TR_IO_INPUT18 = 26, /* Digital Active - peri.tr_io_input[18]:0 */ 1409 1410 /* P10.1 */ 1411 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1412 P10_1_AMUXA = 4, /* Analog mux bus A */ 1413 P10_1_AMUXB = 5, /* Analog mux bus B */ 1414 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1415 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1416 P10_1_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:0 */ 1417 P10_1_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:0 */ 1418 P10_1_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:0 */ 1419 P10_1_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:0 */ 1420 P10_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:1 */ 1421 P10_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:1 */ 1422 P10_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:1 */ 1423 P10_1_PERI_TR_IO_INPUT19 = 26, /* Digital Active - peri.tr_io_input[19]:0 */ 1424 1425 /* P10.2 */ 1426 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1427 P10_2_AMUXA = 4, /* Analog mux bus A */ 1428 P10_2_AMUXB = 5, /* Analog mux bus B */ 1429 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1430 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1431 P10_2_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:0 */ 1432 P10_2_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:0 */ 1433 P10_2_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:0 */ 1434 P10_2_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:0 */ 1435 P10_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:1 */ 1436 P10_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:1 */ 1437 P10_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:1 */ 1438 1439 /* P10.3 */ 1440 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1441 P10_3_AMUXA = 4, /* Analog mux bus A */ 1442 P10_3_AMUXB = 5, /* Analog mux bus B */ 1443 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1444 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1445 P10_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:0 */ 1446 P10_3_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:0 */ 1447 P10_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:0 */ 1448 P10_3_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:0 */ 1449 P10_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:1 */ 1450 P10_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:1 */ 1451 1452 /* P10.4 */ 1453 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1454 P10_4_AMUXA = 4, /* Analog mux bus A */ 1455 P10_4_AMUXB = 5, /* Analog mux bus B */ 1456 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1457 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1458 P10_4_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:0 */ 1459 P10_4_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:0 */ 1460 P10_4_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:0 */ 1461 P10_4_TCPWM0_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[94]:0 */ 1462 P10_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:1 */ 1463 1464 /* P11.0 */ 1465 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1466 P11_0_AMUXA = 4, /* Analog mux bus A */ 1467 P11_0_AMUXB = 5, /* Analog mux bus B */ 1468 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1469 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1470 1471 /* P11.1 */ 1472 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1473 P11_1_AMUXA = 4, /* Analog mux bus A */ 1474 P11_1_AMUXB = 5, /* Analog mux bus B */ 1475 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1476 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1477 1478 /* P11.2 */ 1479 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1480 P11_2_AMUXA = 4, /* Analog mux bus A */ 1481 P11_2_AMUXB = 5, /* Analog mux bus B */ 1482 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1483 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1484 1485 /* P12.0 */ 1486 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1487 P12_0_AMUXA = 4, /* Analog mux bus A */ 1488 P12_0_AMUXB = 5, /* Analog mux bus B */ 1489 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1490 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1491 P12_0_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ 1492 P12_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:0 */ 1493 P12_0_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:0 */ 1494 P12_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:0 */ 1495 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 1496 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 1497 1498 /* P12.1 */ 1499 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1500 P12_1_AMUXA = 4, /* Analog mux bus A */ 1501 P12_1_AMUXB = 5, /* Analog mux bus B */ 1502 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1503 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1504 P12_1_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ 1505 P12_1_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ 1506 P12_1_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:0 */ 1507 P12_1_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:0 */ 1508 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 1509 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 1510 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 1511 1512 /* P12.2 */ 1513 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1514 P12_2_AMUXA = 4, /* Analog mux bus A */ 1515 P12_2_AMUXB = 5, /* Analog mux bus B */ 1516 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1517 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1518 P12_2_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:0 */ 1519 P12_2_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:0 */ 1520 P12_2_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:0 */ 1521 P12_2_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:0 */ 1522 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 1523 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 1524 1525 /* P12.3 */ 1526 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1527 P12_3_AMUXA = 4, /* Analog mux bus A */ 1528 P12_3_AMUXB = 5, /* Analog mux bus B */ 1529 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1530 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1531 P12_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:0 */ 1532 P12_3_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:0 */ 1533 P12_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:0 */ 1534 P12_3_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:0 */ 1535 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 1536 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 1537 1538 /* P12.4 */ 1539 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1540 P12_4_AMUXA = 4, /* Analog mux bus A */ 1541 P12_4_AMUXB = 5, /* Analog mux bus B */ 1542 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1543 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1544 P12_4_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:0 */ 1545 P12_4_TCPWM0_LINE_COMPL39 = 9, /* Digital Active - tcpwm[0].line_compl[39]:0 */ 1546 P12_4_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:0 */ 1547 P12_4_TCPWM0_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[118]:0 */ 1548 P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 1549 1550 /* P12.5 */ 1551 P12_5_GPIO = 0, /* GPIO controls 'out' */ 1552 P12_5_AMUXA = 4, /* Analog mux bus A */ 1553 P12_5_AMUXB = 5, /* Analog mux bus B */ 1554 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1555 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1556 P12_5_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:0 */ 1557 P12_5_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:0 */ 1558 P12_5_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:0 */ 1559 P12_5_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:0 */ 1560 P12_5_PASS0_SAR_EXT_MUX_SEL5 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[5] */ 1561 1562 /* P13.0 */ 1563 P13_0_GPIO = 0, /* GPIO controls 'out' */ 1564 P13_0_AMUXA = 4, /* Analog mux bus A */ 1565 P13_0_AMUXB = 5, /* Analog mux bus B */ 1566 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1567 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1568 P13_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ 1569 P13_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:0 */ 1570 P13_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:0 */ 1571 P13_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:0 */ 1572 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 1573 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 1574 P13_0_SCB3_SPI_MISO = 19, /* Digital Active - scb[3].spi_miso:0 */ 1575 1576 /* P13.1 */ 1577 P13_1_GPIO = 0, /* GPIO controls 'out' */ 1578 P13_1_AMUXA = 4, /* Analog mux bus A */ 1579 P13_1_AMUXB = 5, /* Analog mux bus B */ 1580 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1581 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1582 P13_1_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:0 */ 1583 P13_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ 1584 P13_1_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:0 */ 1585 P13_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:0 */ 1586 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 1587 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 1588 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 1589 P13_1_SCB3_SPI_MOSI = 19, /* Digital Active - scb[3].spi_mosi:0 */ 1590 1591 /* P13.2 */ 1592 P13_2_GPIO = 0, /* GPIO controls 'out' */ 1593 P13_2_AMUXA = 4, /* Analog mux bus A */ 1594 P13_2_AMUXB = 5, /* Analog mux bus B */ 1595 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1596 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1597 P13_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ 1598 P13_2_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:0 */ 1599 P13_2_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:0 */ 1600 P13_2_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:0 */ 1601 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 1602 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 1603 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 1604 P13_2_SCB3_SPI_CLK = 19, /* Digital Active - scb[3].spi_clk:0 */ 1605 1606 /* P13.3 */ 1607 P13_3_GPIO = 0, /* GPIO controls 'out' */ 1608 P13_3_AMUXA = 4, /* Analog mux bus A */ 1609 P13_3_AMUXB = 5, /* Analog mux bus B */ 1610 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1611 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1612 P13_3_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:0 */ 1613 P13_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ 1614 P13_3_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:0 */ 1615 P13_3_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:0 */ 1616 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 1617 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 1618 P13_3_SCB3_SPI_SELECT0 = 19, /* Digital Active - scb[3].spi_select0:0 */ 1619 1620 /* P13.4 */ 1621 P13_4_GPIO = 0, /* GPIO controls 'out' */ 1622 P13_4_AMUXA = 4, /* Analog mux bus A */ 1623 P13_4_AMUXB = 5, /* Analog mux bus B */ 1624 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1625 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1626 P13_4_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:0 */ 1627 P13_4_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:0 */ 1628 P13_4_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:0 */ 1629 P13_4_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:0 */ 1630 P13_4_SCB3_SPI_SELECT1 = 19, /* Digital Active - scb[3].spi_select1:0 */ 1631 1632 /* P13.5 */ 1633 P13_5_GPIO = 0, /* GPIO controls 'out' */ 1634 P13_5_AMUXA = 4, /* Analog mux bus A */ 1635 P13_5_AMUXB = 5, /* Analog mux bus B */ 1636 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1637 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1638 P13_5_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:0 */ 1639 P13_5_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:0 */ 1640 P13_5_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:0 */ 1641 P13_5_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:0 */ 1642 P13_5_SCB3_SPI_SELECT2 = 19, /* Digital Active - scb[3].spi_select2:0 */ 1643 1644 /* P13.6 */ 1645 P13_6_GPIO = 0, /* GPIO controls 'out' */ 1646 P13_6_AMUXA = 4, /* Analog mux bus A */ 1647 P13_6_AMUXB = 5, /* Analog mux bus B */ 1648 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1649 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1650 P13_6_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:0 */ 1651 P13_6_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:0 */ 1652 P13_6_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:0 */ 1653 P13_6_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:0 */ 1654 P13_6_SCB3_SPI_SELECT3 = 19, /* Digital Active - scb[3].spi_select3:0 */ 1655 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 1656 1657 /* P13.7 */ 1658 P13_7_GPIO = 0, /* GPIO controls 'out' */ 1659 P13_7_AMUXA = 4, /* Analog mux bus A */ 1660 P13_7_AMUXB = 5, /* Analog mux bus B */ 1661 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1662 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1663 P13_7_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:0 */ 1664 P13_7_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:0 */ 1665 P13_7_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:0 */ 1666 P13_7_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:0 */ 1667 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 1668 1669 /* P14.0 */ 1670 P14_0_GPIO = 0, /* GPIO controls 'out' */ 1671 P14_0_AMUXA = 4, /* Analog mux bus A */ 1672 P14_0_AMUXB = 5, /* Analog mux bus B */ 1673 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1674 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1675 P14_0_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:0 */ 1676 P14_0_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:0 */ 1677 P14_0_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:0 */ 1678 P14_0_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:0 */ 1679 P14_0_SCB2_UART_RX = 17, /* Digital Active - scb[2].uart_rx:0 */ 1680 P14_0_SCB2_SPI_MISO = 19, /* Digital Active - scb[2].spi_miso:0 */ 1681 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 1682 1683 /* P14.1 */ 1684 P14_1_GPIO = 0, /* GPIO controls 'out' */ 1685 P14_1_AMUXA = 4, /* Analog mux bus A */ 1686 P14_1_AMUXB = 5, /* Analog mux bus B */ 1687 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1688 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1689 P14_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:0 */ 1690 P14_1_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:0 */ 1691 P14_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:0 */ 1692 P14_1_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:0 */ 1693 P14_1_SCB2_UART_TX = 17, /* Digital Active - scb[2].uart_tx:0 */ 1694 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 1695 P14_1_SCB2_SPI_MOSI = 19, /* Digital Active - scb[2].spi_mosi:0 */ 1696 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 1697 1698 /* P14.2 */ 1699 P14_2_GPIO = 0, /* GPIO controls 'out' */ 1700 P14_2_AMUXA = 4, /* Analog mux bus A */ 1701 P14_2_AMUXB = 5, /* Analog mux bus B */ 1702 P14_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1703 P14_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1704 P14_2_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:0 */ 1705 P14_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:0 */ 1706 P14_2_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:0 */ 1707 P14_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:0 */ 1708 P14_2_SCB2_UART_RTS = 17, /* Digital Active - scb[2].uart_rts:0 */ 1709 P14_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:0 */ 1710 P14_2_SCB2_SPI_CLK = 19, /* Digital Active - scb[2].spi_clk:0 */ 1711 P14_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:1 */ 1712 1713 /* P14.3 */ 1714 P14_3_GPIO = 0, /* GPIO controls 'out' */ 1715 P14_3_AMUXA = 4, /* Analog mux bus A */ 1716 P14_3_AMUXB = 5, /* Analog mux bus B */ 1717 P14_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1718 P14_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1719 P14_3_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:0 */ 1720 P14_3_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:0 */ 1721 P14_3_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:0 */ 1722 P14_3_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:0 */ 1723 P14_3_SCB2_UART_CTS = 17, /* Digital Active - scb[2].uart_cts:0 */ 1724 P14_3_SCB2_SPI_SELECT0 = 19, /* Digital Active - scb[2].spi_select0:0 */ 1725 P14_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:1 */ 1726 1727 /* P14.4 */ 1728 P14_4_GPIO = 0, /* GPIO controls 'out' */ 1729 P14_4_AMUXA = 4, /* Analog mux bus A */ 1730 P14_4_AMUXB = 5, /* Analog mux bus B */ 1731 P14_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1732 P14_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1733 P14_4_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:0 */ 1734 P14_4_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:0 */ 1735 P14_4_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:0 */ 1736 P14_4_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:0 */ 1737 P14_4_SCB2_SPI_SELECT1 = 19, /* Digital Active - scb[2].spi_select1:0 */ 1738 P14_4_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:1 */ 1739 1740 /* P14.5 */ 1741 P14_5_GPIO = 0, /* GPIO controls 'out' */ 1742 P14_5_AMUXA = 4, /* Analog mux bus A */ 1743 P14_5_AMUXB = 5, /* Analog mux bus B */ 1744 P14_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1745 P14_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1746 P14_5_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:0 */ 1747 P14_5_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:0 */ 1748 P14_5_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:0 */ 1749 P14_5_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:0 */ 1750 P14_5_SCB2_SPI_SELECT2 = 19, /* Digital Active - scb[2].spi_select2:0 */ 1751 1752 /* P15.0 */ 1753 P15_0_GPIO = 0, /* GPIO controls 'out' */ 1754 P15_0_AMUXA = 4, /* Analog mux bus A */ 1755 P15_0_AMUXB = 5, /* Analog mux bus B */ 1756 P15_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1757 P15_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1758 P15_0_TCPWM0_LINE56 = 8, /* Digital Active - tcpwm[0].line[56]:0 */ 1759 P15_0_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:0 */ 1760 P15_0_TCPWM0_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[168]:0 */ 1761 P15_0_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:0 */ 1762 1763 /* P15.1 */ 1764 P15_1_GPIO = 0, /* GPIO controls 'out' */ 1765 P15_1_AMUXA = 4, /* Analog mux bus A */ 1766 P15_1_AMUXB = 5, /* Analog mux bus B */ 1767 P15_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1768 P15_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1769 P15_1_TCPWM0_LINE57 = 8, /* Digital Active - tcpwm[0].line[57]:0 */ 1770 P15_1_TCPWM0_LINE_COMPL56 = 9, /* Digital Active - tcpwm[0].line_compl[56]:0 */ 1771 P15_1_TCPWM0_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[171]:0 */ 1772 P15_1_TCPWM0_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[169]:0 */ 1773 1774 /* P15.2 */ 1775 P15_2_GPIO = 0, /* GPIO controls 'out' */ 1776 P15_2_AMUXA = 4, /* Analog mux bus A */ 1777 P15_2_AMUXB = 5, /* Analog mux bus B */ 1778 P15_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1779 P15_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1780 P15_2_TCPWM0_LINE58 = 8, /* Digital Active - tcpwm[0].line[58]:0 */ 1781 P15_2_TCPWM0_LINE_COMPL57 = 9, /* Digital Active - tcpwm[0].line_compl[57]:0 */ 1782 P15_2_TCPWM0_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[174]:0 */ 1783 P15_2_TCPWM0_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[172]:0 */ 1784 1785 /* P15.3 */ 1786 P15_3_GPIO = 0, /* GPIO controls 'out' */ 1787 P15_3_AMUXA = 4, /* Analog mux bus A */ 1788 P15_3_AMUXB = 5, /* Analog mux bus B */ 1789 P15_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1790 P15_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1791 P15_3_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:0 */ 1792 P15_3_TCPWM0_LINE_COMPL58 = 9, /* Digital Active - tcpwm[0].line_compl[58]:0 */ 1793 P15_3_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:0 */ 1794 P15_3_TCPWM0_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[175]:0 */ 1795 1796 /* P16.0 */ 1797 P16_0_GPIO = 0, /* GPIO controls 'out' */ 1798 P16_0_AMUXA = 4, /* Analog mux bus A */ 1799 P16_0_AMUXB = 5, /* Analog mux bus B */ 1800 P16_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1801 P16_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1802 P16_0_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:0 */ 1803 P16_0_TCPWM0_LINE_COMPL59 = 9, /* Digital Active - tcpwm[0].line_compl[59]:0 */ 1804 P16_0_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:0 */ 1805 P16_0_TCPWM0_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[178]:0 */ 1806 P16_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:1 */ 1807 1808 /* P16.1 */ 1809 P16_1_GPIO = 0, /* GPIO controls 'out' */ 1810 P16_1_AMUXA = 4, /* Analog mux bus A */ 1811 P16_1_AMUXB = 5, /* Analog mux bus B */ 1812 P16_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1813 P16_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1814 P16_1_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:0 */ 1815 P16_1_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:0 */ 1816 P16_1_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:0 */ 1817 P16_1_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:0 */ 1818 P16_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:1 */ 1819 1820 /* P16.2 */ 1821 P16_2_GPIO = 0, /* GPIO controls 'out' */ 1822 P16_2_AMUXA = 4, /* Analog mux bus A */ 1823 P16_2_AMUXB = 5, /* Analog mux bus B */ 1824 P16_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1825 P16_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1826 P16_2_TCPWM0_LINE62 = 8, /* Digital Active - tcpwm[0].line[62]:0 */ 1827 P16_2_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:0 */ 1828 P16_2_TCPWM0_TR_ONE_CNT_IN186 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[186]:0 */ 1829 P16_2_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:0 */ 1830 P16_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:1 */ 1831 1832 /* P17.0 */ 1833 P17_0_GPIO = 0, /* GPIO controls 'out' */ 1834 P17_0_AMUXA = 4, /* Analog mux bus A */ 1835 P17_0_AMUXB = 5, /* Analog mux bus B */ 1836 P17_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1837 P17_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1838 P17_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:1 */ 1839 P17_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:1 */ 1840 P17_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:1 */ 1841 P17_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:1 */ 1842 P17_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:0 */ 1843 1844 /* P17.1 */ 1845 P17_1_GPIO = 0, /* GPIO controls 'out' */ 1846 P17_1_AMUXA = 4, /* Analog mux bus A */ 1847 P17_1_AMUXB = 5, /* Analog mux bus B */ 1848 P17_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1849 P17_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1850 P17_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:1 */ 1851 P17_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:1 */ 1852 P17_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:1 */ 1853 P17_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:1 */ 1854 P17_1_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:1 */ 1855 P17_1_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:1 */ 1856 P17_1_SCB3_SPI_MISO = 19, /* Digital Active - scb[3].spi_miso:1 */ 1857 P17_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:0 */ 1858 1859 /* P17.2 */ 1860 P17_2_GPIO = 0, /* GPIO controls 'out' */ 1861 P17_2_AMUXA = 4, /* Analog mux bus A */ 1862 P17_2_AMUXB = 5, /* Analog mux bus B */ 1863 P17_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1864 P17_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1865 P17_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:1 */ 1866 P17_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:1 */ 1867 P17_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:1 */ 1868 P17_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:1 */ 1869 P17_2_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:1 */ 1870 P17_2_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:1 */ 1871 P17_2_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:1 */ 1872 P17_2_SCB3_SPI_MOSI = 19, /* Digital Active - scb[3].spi_mosi:1 */ 1873 1874 /* P17.3 */ 1875 P17_3_GPIO = 0, /* GPIO controls 'out' */ 1876 P17_3_AMUXA = 4, /* Analog mux bus A */ 1877 P17_3_AMUXB = 5, /* Analog mux bus B */ 1878 P17_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1879 P17_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1880 P17_3_TCPWM0_LINE58 = 8, /* Digital Active - tcpwm[0].line[58]:1 */ 1881 P17_3_TCPWM0_LINE_COMPL59 = 9, /* Digital Active - tcpwm[0].line_compl[59]:1 */ 1882 P17_3_TCPWM0_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[174]:1 */ 1883 P17_3_TCPWM0_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[178]:1 */ 1884 P17_3_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:1 */ 1885 P17_3_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:1 */ 1886 P17_3_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:1 */ 1887 P17_3_SCB3_SPI_CLK = 19, /* Digital Active - scb[3].spi_clk:1 */ 1888 P17_3_PERI_TR_IO_INPUT26 = 26, /* Digital Active - peri.tr_io_input[26]:0 */ 1889 1890 /* P17.4 */ 1891 P17_4_GPIO = 0, /* GPIO controls 'out' */ 1892 P17_4_AMUXA = 4, /* Analog mux bus A */ 1893 P17_4_AMUXB = 5, /* Analog mux bus B */ 1894 P17_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1895 P17_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1896 P17_4_TCPWM0_LINE57 = 8, /* Digital Active - tcpwm[0].line[57]:1 */ 1897 P17_4_TCPWM0_LINE_COMPL58 = 9, /* Digital Active - tcpwm[0].line_compl[58]:1 */ 1898 P17_4_TCPWM0_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[171]:1 */ 1899 P17_4_TCPWM0_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[175]:1 */ 1900 P17_4_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:1 */ 1901 P17_4_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:1 */ 1902 P17_4_SCB3_SPI_SELECT0 = 19, /* Digital Active - scb[3].spi_select0:1 */ 1903 P17_4_PERI_TR_IO_INPUT27 = 26, /* Digital Active - peri.tr_io_input[27]:0 */ 1904 1905 /* P18.0 */ 1906 P18_0_GPIO = 0, /* GPIO controls 'out' */ 1907 P18_0_AMUXA = 4, /* Analog mux bus A */ 1908 P18_0_AMUXB = 5, /* Analog mux bus B */ 1909 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1910 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1911 P18_0_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:1 */ 1912 P18_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 1913 P18_0_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:1 */ 1914 P18_0_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:1 */ 1915 P18_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:0 */ 1916 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 1917 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 1918 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 1919 1920 /* P18.1 */ 1921 P18_1_GPIO = 0, /* GPIO controls 'out' */ 1922 P18_1_AMUXA = 4, /* Analog mux bus A */ 1923 P18_1_AMUXB = 5, /* Analog mux bus B */ 1924 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1925 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1926 P18_1_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:1 */ 1927 P18_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 1928 P18_1_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:1 */ 1929 P18_1_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:1 */ 1930 P18_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:0 */ 1931 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 1932 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 1933 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 1934 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 1935 1936 /* P18.2 */ 1937 P18_2_GPIO = 0, /* GPIO controls 'out' */ 1938 P18_2_AMUXA = 4, /* Analog mux bus A */ 1939 P18_2_AMUXB = 5, /* Analog mux bus B */ 1940 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1941 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1942 P18_2_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:1 */ 1943 P18_2_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ 1944 P18_2_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:1 */ 1945 P18_2_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:1 */ 1946 P18_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:0 */ 1947 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 1948 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 1949 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 1950 1951 /* P18.3 */ 1952 P18_3_GPIO = 0, /* GPIO controls 'out' */ 1953 P18_3_AMUXA = 4, /* Analog mux bus A */ 1954 P18_3_AMUXB = 5, /* Analog mux bus B */ 1955 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1956 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1957 P18_3_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:1 */ 1958 P18_3_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:1 */ 1959 P18_3_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:1 */ 1960 P18_3_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:1 */ 1961 P18_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:0 */ 1962 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 1963 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 1964 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 1965 1966 /* P18.4 */ 1967 P18_4_GPIO = 0, /* GPIO controls 'out' */ 1968 P18_4_AMUXA = 4, /* Analog mux bus A */ 1969 P18_4_AMUXB = 5, /* Analog mux bus B */ 1970 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1971 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1972 P18_4_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:1 */ 1973 P18_4_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:1 */ 1974 P18_4_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:1 */ 1975 P18_4_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:1 */ 1976 P18_4_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:0 */ 1977 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 1978 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1979 1980 /* P18.5 */ 1981 P18_5_GPIO = 0, /* GPIO controls 'out' */ 1982 P18_5_AMUXA = 4, /* Analog mux bus A */ 1983 P18_5_AMUXB = 5, /* Analog mux bus B */ 1984 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1985 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1986 P18_5_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:1 */ 1987 P18_5_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:1 */ 1988 P18_5_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:1 */ 1989 P18_5_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:1 */ 1990 P18_5_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:0 */ 1991 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 1992 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1993 1994 /* P18.6 */ 1995 P18_6_GPIO = 0, /* GPIO controls 'out' */ 1996 P18_6_AMUXA = 4, /* Analog mux bus A */ 1997 P18_6_AMUXB = 5, /* Analog mux bus B */ 1998 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1999 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2000 P18_6_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:1 */ 2001 P18_6_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:1 */ 2002 P18_6_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:1 */ 2003 P18_6_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:1 */ 2004 P18_6_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:0 */ 2005 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 2006 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 2007 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 2008 2009 /* P18.7 */ 2010 P18_7_GPIO = 0, /* GPIO controls 'out' */ 2011 P18_7_AMUXA = 4, /* Analog mux bus A */ 2012 P18_7_AMUXB = 5, /* Analog mux bus B */ 2013 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2014 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2015 P18_7_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:1 */ 2016 P18_7_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:1 */ 2017 P18_7_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:1 */ 2018 P18_7_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:1 */ 2019 P18_7_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:0 */ 2020 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 2021 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 2022 2023 /* P19.0 */ 2024 P19_0_GPIO = 0, /* GPIO controls 'out' */ 2025 P19_0_AMUXA = 4, /* Analog mux bus A */ 2026 P19_0_AMUXB = 5, /* Analog mux bus B */ 2027 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2028 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2029 P19_0_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:2 */ 2030 P19_0_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:1 */ 2031 P19_0_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:2 */ 2032 P19_0_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:1 */ 2033 P19_0_TCPWM0_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536]:0 */ 2034 P19_0_SCB2_UART_RX = 17, /* Digital Active - scb[2].uart_rx:1 */ 2035 P19_0_SCB2_SPI_MISO = 19, /* Digital Active - scb[2].spi_miso:1 */ 2036 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 2037 2038 /* P19.1 */ 2039 P19_1_GPIO = 0, /* GPIO controls 'out' */ 2040 P19_1_AMUXA = 4, /* Analog mux bus A */ 2041 P19_1_AMUXB = 5, /* Analog mux bus B */ 2042 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2043 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2044 P19_1_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:1 */ 2045 P19_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ 2046 P19_1_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:1 */ 2047 P19_1_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:2 */ 2048 P19_1_TCPWM0_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537]:0 */ 2049 P19_1_SCB2_UART_TX = 17, /* Digital Active - scb[2].uart_tx:1 */ 2050 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 2051 P19_1_SCB2_SPI_MOSI = 19, /* Digital Active - scb[2].spi_mosi:1 */ 2052 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 2053 2054 /* P19.2 */ 2055 P19_2_GPIO = 0, /* GPIO controls 'out' */ 2056 P19_2_AMUXA = 4, /* Analog mux bus A */ 2057 P19_2_AMUXB = 5, /* Analog mux bus B */ 2058 P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2059 P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2060 P19_2_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:2 */ 2061 P19_2_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:1 */ 2062 P19_2_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:2 */ 2063 P19_2_TCPWM0_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[79]:1 */ 2064 P19_2_TCPWM0_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539]:0 */ 2065 P19_2_SCB2_UART_RTS = 17, /* Digital Active - scb[2].uart_rts:1 */ 2066 P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ 2067 P19_2_SCB2_SPI_CLK = 19, /* Digital Active - scb[2].spi_clk:1 */ 2068 P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ 2069 2070 /* P19.3 */ 2071 P19_3_GPIO = 0, /* GPIO controls 'out' */ 2072 P19_3_AMUXA = 4, /* Analog mux bus A */ 2073 P19_3_AMUXB = 5, /* Analog mux bus B */ 2074 P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2075 P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2076 P19_3_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:2 */ 2077 P19_3_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:2 */ 2078 P19_3_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:2 */ 2079 P19_3_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:2 */ 2080 P19_3_TCPWM0_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540]:0 */ 2081 P19_3_SCB2_UART_CTS = 17, /* Digital Active - scb[2].uart_cts:1 */ 2082 P19_3_SCB2_SPI_SELECT0 = 19, /* Digital Active - scb[2].spi_select0:1 */ 2083 P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ 2084 2085 /* P19.4 */ 2086 P19_4_GPIO = 0, /* GPIO controls 'out' */ 2087 P19_4_AMUXA = 4, /* Analog mux bus A */ 2088 P19_4_AMUXB = 5, /* Analog mux bus B */ 2089 P19_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2090 P19_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2091 P19_4_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:2 */ 2092 P19_4_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:2 */ 2093 P19_4_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:2 */ 2094 P19_4_TCPWM0_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[85]:2 */ 2095 P19_4_TCPWM0_TR_ONE_CNT_IN1542 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1542]:0 */ 2096 P19_4_SCB2_SPI_SELECT1 = 19, /* Digital Active - scb[2].spi_select1:1 */ 2097 2098 /* P20.0 */ 2099 P20_0_GPIO = 0, /* GPIO controls 'out' */ 2100 P20_0_AMUXA = 4, /* Analog mux bus A */ 2101 P20_0_AMUXB = 5, /* Analog mux bus B */ 2102 P20_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2103 P20_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2104 P20_0_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:2 */ 2105 P20_0_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:2 */ 2106 P20_0_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:2 */ 2107 P20_0_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:2 */ 2108 P20_0_TCPWM0_TR_ONE_CNT_IN1543 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1543]:0 */ 2109 P20_0_SCB2_SPI_SELECT2 = 19, /* Digital Active - scb[2].spi_select2:1 */ 2110 P20_0_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:0 */ 2111 2112 /* P20.1 */ 2113 P20_1_GPIO = 0, /* GPIO controls 'out' */ 2114 P20_1_AMUXA = 4, /* Analog mux bus A */ 2115 P20_1_AMUXB = 5, /* Analog mux bus B */ 2116 P20_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2117 P20_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2118 P20_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:1 */ 2119 P20_1_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:2 */ 2120 P20_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:1 */ 2121 P20_1_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:2 */ 2122 P20_1_TCPWM0_TR_ONE_CNT_IN1545 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1545]:0 */ 2123 P20_1_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:0 */ 2124 2125 /* P20.2 */ 2126 P20_2_GPIO = 0, /* GPIO controls 'out' */ 2127 P20_2_AMUXA = 4, /* Analog mux bus A */ 2128 P20_2_AMUXB = 5, /* Analog mux bus B */ 2129 P20_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2130 P20_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2131 P20_2_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:1 */ 2132 P20_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:1 */ 2133 P20_2_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:1 */ 2134 P20_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:1 */ 2135 P20_2_TCPWM0_TR_ONE_CNT_IN1546 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1546]:0 */ 2136 P20_2_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:0 */ 2137 2138 /* P20.3 */ 2139 P20_3_GPIO = 0, /* GPIO controls 'out' */ 2140 P20_3_AMUXA = 4, /* Analog mux bus A */ 2141 P20_3_AMUXB = 5, /* Analog mux bus B */ 2142 P20_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2143 P20_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2144 P20_3_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:1 */ 2145 P20_3_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:1 */ 2146 P20_3_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:1 */ 2147 P20_3_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:1 */ 2148 P20_3_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:1 */ 2149 P20_3_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:1 */ 2150 P20_3_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:1 */ 2151 2152 /* P21.0 */ 2153 P21_0_GPIO = 0, /* GPIO controls 'out' */ 2154 P21_0_AMUXA = 4, /* Analog mux bus A */ 2155 P21_0_AMUXB = 5, /* Analog mux bus B */ 2156 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2157 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2158 P21_0_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:1 */ 2159 P21_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:1 */ 2160 P21_0_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:1 */ 2161 P21_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:1 */ 2162 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 2163 2164 /* P21.1 */ 2165 P21_1_GPIO = 0, /* GPIO controls 'out' */ 2166 P21_1_AMUXA = 4, /* Analog mux bus A */ 2167 P21_1_AMUXB = 5, /* Analog mux bus B */ 2168 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2169 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2170 P21_1_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:1 */ 2171 P21_1_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:1 */ 2172 P21_1_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:1 */ 2173 P21_1_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:1 */ 2174 2175 /* P21.2 */ 2176 P21_2_GPIO = 0, /* GPIO controls 'out' */ 2177 P21_2_AMUXA = 4, /* Analog mux bus A */ 2178 P21_2_AMUXB = 5, /* Analog mux bus B */ 2179 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2180 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2181 P21_2_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:1 */ 2182 P21_2_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:1 */ 2183 P21_2_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:1 */ 2184 P21_2_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:1 */ 2185 P21_2_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:0 */ 2186 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 2187 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 2188 2189 /* P21.3 */ 2190 P21_3_GPIO = 0, /* GPIO controls 'out' */ 2191 P21_3_AMUXA = 4, /* Analog mux bus A */ 2192 P21_3_AMUXB = 5, /* Analog mux bus B */ 2193 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2194 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2195 P21_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:1 */ 2196 P21_3_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:1 */ 2197 P21_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:1 */ 2198 P21_3_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:1 */ 2199 2200 /* P21.5 */ 2201 P21_5_GPIO = 0, /* GPIO controls 'out' */ 2202 P21_5_AMUXA = 4, /* Analog mux bus A */ 2203 P21_5_AMUXB = 5, /* Analog mux bus B */ 2204 P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2205 P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2206 P21_5_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:1 */ 2207 P21_5_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:1 */ 2208 P21_5_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:1 */ 2209 P21_5_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:1 */ 2210 P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ 2211 2212 /* P21.6 */ 2213 P21_6_GPIO = 0, /* GPIO controls 'out' */ 2214 P21_6_AMUXA = 4, /* Analog mux bus A */ 2215 P21_6_AMUXB = 5, /* Analog mux bus B */ 2216 P21_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2217 P21_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2218 P21_6_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:1 */ 2219 P21_6_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:1 */ 2220 P21_6_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:1 */ 2221 P21_6_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:1 */ 2222 P21_6_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:1 */ 2223 P21_6_CPUSS_CLK_FM_PUMP = 26, /* Digital Active - cpuss.clk_fm_pump */ 2224 2225 /* P22.0 */ 2226 P22_0_GPIO = 0, /* GPIO controls 'out' */ 2227 P22_0_AMUXA = 4, /* Analog mux bus A */ 2228 P22_0_AMUXB = 5, /* Analog mux bus B */ 2229 P22_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2230 P22_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2231 P22_0_TCPWM0_LINE34 = 8, /* Digital Active - tcpwm[0].line[34]:1 */ 2232 P22_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:1 */ 2233 P22_0_TCPWM0_TR_ONE_CNT_IN102 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:1 */ 2234 P22_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:1 */ 2235 P22_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ 2236 P22_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ 2237 P22_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 2238 P22_0_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 2239 2240 /* P22.1 */ 2241 P22_1_GPIO = 0, /* GPIO controls 'out' */ 2242 P22_1_AMUXA = 4, /* Analog mux bus A */ 2243 P22_1_AMUXB = 5, /* Analog mux bus B */ 2244 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2245 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2246 P22_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:1 */ 2247 P22_1_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:1 */ 2248 P22_1_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:1 */ 2249 P22_1_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:1 */ 2250 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 2251 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 2252 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 2253 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 2254 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 2255 2256 /* P22.2 */ 2257 P22_2_GPIO = 0, /* GPIO controls 'out' */ 2258 P22_2_AMUXA = 4, /* Analog mux bus A */ 2259 P22_2_AMUXB = 5, /* Analog mux bus B */ 2260 P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2261 P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2262 P22_2_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:1 */ 2263 P22_2_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:1 */ 2264 P22_2_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:1 */ 2265 P22_2_TCPWM0_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[100]:1 */ 2266 P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ 2267 P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ 2268 P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ 2269 P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 2270 2271 /* P22.3 */ 2272 P22_3_GPIO = 0, /* GPIO controls 'out' */ 2273 P22_3_AMUXA = 4, /* Analog mux bus A */ 2274 P22_3_AMUXB = 5, /* Analog mux bus B */ 2275 P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2276 P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2277 P22_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:1 */ 2278 P22_3_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:1 */ 2279 P22_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:1 */ 2280 P22_3_TCPWM0_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[97]:1 */ 2281 P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ 2282 P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ 2283 P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 2284 2285 /* P22.4 */ 2286 P22_4_GPIO = 0, /* GPIO controls 'out' */ 2287 P22_4_AMUXA = 4, /* Analog mux bus A */ 2288 P22_4_AMUXB = 5, /* Analog mux bus B */ 2289 P22_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2290 P22_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2291 P22_4_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:1 */ 2292 P22_4_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:1 */ 2293 P22_4_TCPWM0_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[90]:1 */ 2294 P22_4_TCPWM0_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[94]:1 */ 2295 P22_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:1 */ 2296 P22_4_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:1 */ 2297 2298 /* P22.5 */ 2299 P22_5_GPIO = 0, /* GPIO controls 'out' */ 2300 P22_5_AMUXA = 4, /* Analog mux bus A */ 2301 P22_5_AMUXB = 5, /* Analog mux bus B */ 2302 P22_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2303 P22_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2304 P22_5_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:1 */ 2305 P22_5_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:1 */ 2306 P22_5_TCPWM0_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[87]:1 */ 2307 P22_5_TCPWM0_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[91]:1 */ 2308 P22_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:1 */ 2309 P22_5_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:1 */ 2310 2311 /* P22.6 */ 2312 P22_6_GPIO = 0, /* GPIO controls 'out' */ 2313 P22_6_AMUXA = 4, /* Analog mux bus A */ 2314 P22_6_AMUXB = 5, /* Analog mux bus B */ 2315 P22_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2316 P22_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2317 P22_6_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:1 */ 2318 P22_6_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:1 */ 2319 P22_6_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:1 */ 2320 P22_6_TCPWM0_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[88]:1 */ 2321 P22_6_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:1 */ 2322 2323 /* P23.0 */ 2324 P23_0_GPIO = 0, /* GPIO controls 'out' */ 2325 P23_0_AMUXA = 4, /* Analog mux bus A */ 2326 P23_0_AMUXB = 5, /* Analog mux bus B */ 2327 P23_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2328 P23_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2329 P23_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:1 */ 2330 P23_0_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:1 */ 2331 P23_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:1 */ 2332 P23_0_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:1 */ 2333 P23_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:1 */ 2334 P23_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:1 */ 2335 P23_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:1 */ 2336 P23_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:1 */ 2337 2338 /* P23.1 */ 2339 P23_1_GPIO = 0, /* GPIO controls 'out' */ 2340 P23_1_AMUXA = 4, /* Analog mux bus A */ 2341 P23_1_AMUXB = 5, /* Analog mux bus B */ 2342 P23_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2343 P23_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2344 P23_1_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:1 */ 2345 P23_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:1 */ 2346 P23_1_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:1 */ 2347 P23_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:1 */ 2348 P23_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:1 */ 2349 P23_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:1 */ 2350 P23_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:1 */ 2351 P23_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:1 */ 2352 P23_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:1 */ 2353 2354 /* P23.3 */ 2355 P23_3_GPIO = 0, /* GPIO controls 'out' */ 2356 P23_3_AMUXA = 4, /* Analog mux bus A */ 2357 P23_3_AMUXB = 5, /* Analog mux bus B */ 2358 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2359 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2360 P23_3_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:1 */ 2361 P23_3_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:1 */ 2362 P23_3_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:1 */ 2363 P23_3_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:1 */ 2364 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 2365 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 2366 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 2367 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 2368 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 2369 2370 /* P23.4 */ 2371 P23_4_GPIO = 0, /* GPIO controls 'out' */ 2372 P23_4_AMUXA = 4, /* Analog mux bus A */ 2373 P23_4_AMUXB = 5, /* Analog mux bus B */ 2374 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2375 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2376 P23_4_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ 2377 P23_4_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:1 */ 2378 P23_4_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:1 */ 2379 P23_4_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:1 */ 2380 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 2381 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 2382 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 2383 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 2384 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 2385 2386 /* P23.5 */ 2387 P23_5_GPIO = 0, /* GPIO controls 'out' */ 2388 P23_5_AMUXA = 4, /* Analog mux bus A */ 2389 P23_5_AMUXB = 5, /* Analog mux bus B */ 2390 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2391 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2392 P23_5_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ 2393 P23_5_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ 2394 P23_5_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:1 */ 2395 P23_5_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:1 */ 2396 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 2397 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 2398 2399 /* P23.6 */ 2400 P23_6_GPIO = 0, /* GPIO controls 'out' */ 2401 P23_6_AMUXA = 4, /* Analog mux bus A */ 2402 P23_6_AMUXB = 5, /* Analog mux bus B */ 2403 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2404 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2405 P23_6_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ 2406 P23_6_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ 2407 P23_6_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:1 */ 2408 P23_6_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:1 */ 2409 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 2410 2411 /* P23.7 */ 2412 P23_7_GPIO = 0, /* GPIO controls 'out' */ 2413 P23_7_AMUXA = 4, /* Analog mux bus A */ 2414 P23_7_AMUXB = 5, /* Analog mux bus B */ 2415 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2416 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2417 P23_7_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ 2418 P23_7_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ 2419 P23_7_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:1 */ 2420 P23_7_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:1 */ 2421 P23_7_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:1 */ 2422 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 2423 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 2424 P23_7_SRSS_DDFT_PIN_IN0 = 31 /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 2425 } en_hsiom_sel_t; 2426 2427 #endif /* _GPIO_TVIIBE1M_144_LQFP_H_ */ 2428 2429 2430 /* [] END OF FILE */ 2431
