1 /***************************************************************************//** 2 * \file gpio_psoc6_04_80_tqfp.h 3 * 4 * \brief 5 * PSoC6_04 device GPIO header for 80-TQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_04_80_TQFP_H_ 28 #define _GPIO_PSOC6_04_80_TQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_TQFP 44 #define CY_GPIO_PIN_COUNT 80u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ANALOG_VDDD, 50 AMUXBUS_CSD0, 51 AMUXBUS_CSD1, 52 AMUXBUS_MAIN, 53 AMUXBUS_SAR, 54 AMUXBUS_VDDIO_1, 55 AMUXBUS_VSSA, 56 AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, 57 AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, 58 }; 59 60 /* AMUX Splitter Controls */ 61 typedef enum 62 { 63 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_MAIN */ 64 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 65 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 66 AMUX_SPLIT_CTL_5 = 0x0005u /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 67 } cy_en_amux_split_t; 68 69 /* Port List */ 70 /* PORT 0 (GPIO) */ 71 #define P0_0_PORT GPIO_PRT0 72 #define P0_0_PIN 0u 73 #define P0_0_NUM 0u 74 #define P0_1_PORT GPIO_PRT0 75 #define P0_1_PIN 1u 76 #define P0_1_NUM 1u 77 #define P0_2_PORT GPIO_PRT0 78 #define P0_2_PIN 2u 79 #define P0_2_NUM 2u 80 #define P0_3_PORT GPIO_PRT0 81 #define P0_3_PIN 3u 82 #define P0_3_NUM 3u 83 #define P0_4_PORT GPIO_PRT0 84 #define P0_4_PIN 4u 85 #define P0_4_NUM 4u 86 #define P0_5_PORT GPIO_PRT0 87 #define P0_5_PIN 5u 88 #define P0_5_NUM 5u 89 90 /* PORT 1 (GPIO) */ 91 #define P1_0_PORT GPIO_PRT1 92 #define P1_0_PIN 0u 93 #define P1_0_NUM 0u 94 #define P1_1_PORT GPIO_PRT1 95 #define P1_1_PIN 1u 96 #define P1_1_NUM 1u 97 #define P1_2_PORT GPIO_PRT1 98 #define P1_2_PIN 2u 99 #define P1_2_NUM 2u 100 101 /* PORT 2 (GPIO) */ 102 #define P2_0_PORT GPIO_PRT2 103 #define P2_0_PIN 0u 104 #define P2_0_NUM 0u 105 #define P2_1_PORT GPIO_PRT2 106 #define P2_1_PIN 1u 107 #define P2_1_NUM 1u 108 #define P2_2_PORT GPIO_PRT2 109 #define P2_2_PIN 2u 110 #define P2_2_NUM 2u 111 #define P2_3_PORT GPIO_PRT2 112 #define P2_3_PIN 3u 113 #define P2_3_NUM 3u 114 #define P2_4_PORT GPIO_PRT2 115 #define P2_4_PIN 4u 116 #define P2_4_NUM 4u 117 #define P2_5_PORT GPIO_PRT2 118 #define P2_5_PIN 5u 119 #define P2_5_NUM 5u 120 #define P2_6_PORT GPIO_PRT2 121 #define P2_6_PIN 6u 122 #define P2_6_NUM 6u 123 #define P2_7_PORT GPIO_PRT2 124 #define P2_7_PIN 7u 125 #define P2_7_NUM 7u 126 127 /* PORT 3 (GPIO_OVT) */ 128 #define P3_0_PORT GPIO_PRT3 129 #define P3_0_PIN 0u 130 #define P3_0_NUM 0u 131 #define P3_0_AMUXSEGMENT AMUXBUS_VSSA 132 #define P3_1_PORT GPIO_PRT3 133 #define P3_1_PIN 1u 134 #define P3_1_NUM 1u 135 #define P3_1_AMUXSEGMENT AMUXBUS_VSSA 136 137 /* PORT 5 (GPIO) */ 138 #define P5_0_PORT GPIO_PRT5 139 #define P5_0_PIN 0u 140 #define P5_0_NUM 0u 141 #define P5_1_PORT GPIO_PRT5 142 #define P5_1_PIN 1u 143 #define P5_1_NUM 1u 144 #define P5_2_PORT GPIO_PRT5 145 #define P5_2_PIN 2u 146 #define P5_2_NUM 2u 147 #define P5_6_PORT GPIO_PRT5 148 #define P5_6_PIN 6u 149 #define P5_6_NUM 6u 150 #define P5_7_PORT GPIO_PRT5 151 #define P5_7_PIN 7u 152 #define P5_7_NUM 7u 153 154 /* PORT 6 (GPIO) */ 155 #define P6_2_PORT GPIO_PRT6 156 #define P6_2_PIN 2u 157 #define P6_2_NUM 2u 158 #define P6_3_PORT GPIO_PRT6 159 #define P6_3_PIN 3u 160 #define P6_3_NUM 3u 161 #define P6_4_PORT GPIO_PRT6 162 #define P6_4_PIN 4u 163 #define P6_4_NUM 4u 164 #define P6_5_PORT GPIO_PRT6 165 #define P6_5_PIN 5u 166 #define P6_5_NUM 5u 167 #define P6_6_PORT GPIO_PRT6 168 #define P6_6_PIN 6u 169 #define P6_6_NUM 6u 170 #define P6_7_PORT GPIO_PRT6 171 #define P6_7_PIN 7u 172 #define P6_7_NUM 7u 173 174 /* PORT 7 (GPIO) */ 175 #define P7_0_PORT GPIO_PRT7 176 #define P7_0_PIN 0u 177 #define P7_0_NUM 0u 178 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 179 #define P7_1_PORT GPIO_PRT7 180 #define P7_1_PIN 1u 181 #define P7_1_NUM 1u 182 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 183 #define P7_2_PORT GPIO_PRT7 184 #define P7_2_PIN 2u 185 #define P7_2_NUM 2u 186 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 187 #define P7_3_PORT GPIO_PRT7 188 #define P7_3_PIN 3u 189 #define P7_3_NUM 3u 190 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 191 #define P7_4_PORT GPIO_PRT7 192 #define P7_4_PIN 4u 193 #define P7_4_NUM 4u 194 #define P7_4_AMUXSEGMENT AMUXBUS_CSD0 195 #define P7_5_PORT GPIO_PRT7 196 #define P7_5_PIN 5u 197 #define P7_5_NUM 5u 198 #define P7_5_AMUXSEGMENT AMUXBUS_CSD0 199 #define P7_7_PORT GPIO_PRT7 200 #define P7_7_PIN 7u 201 #define P7_7_NUM 7u 202 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 203 204 /* PORT 8 (GPIO) */ 205 #define P8_0_PORT GPIO_PRT8 206 #define P8_0_PIN 0u 207 #define P8_0_NUM 0u 208 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 209 #define P8_1_PORT GPIO_PRT8 210 #define P8_1_PIN 1u 211 #define P8_1_NUM 1u 212 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 213 214 /* PORT 9 (GPIO) */ 215 #define P9_0_PORT GPIO_PRT9 216 #define P9_0_PIN 0u 217 #define P9_0_NUM 0u 218 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 219 #define P9_1_PORT GPIO_PRT9 220 #define P9_1_PIN 1u 221 #define P9_1_NUM 1u 222 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 223 #define P9_2_PORT GPIO_PRT9 224 #define P9_2_PIN 2u 225 #define P9_2_NUM 2u 226 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 227 #define P9_3_PORT GPIO_PRT9 228 #define P9_3_PIN 3u 229 #define P9_3_NUM 3u 230 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 231 #define P9_4_PORT GPIO_PRT9 232 #define P9_4_PIN 4u 233 #define P9_4_NUM 4u 234 #define P9_4_AMUXSEGMENT AMUXBUS_SAR 235 #define P9_5_PORT GPIO_PRT9 236 #define P9_5_PIN 5u 237 #define P9_5_NUM 5u 238 #define P9_5_AMUXSEGMENT AMUXBUS_SAR 239 240 /* PORT 10 (GPIO) */ 241 #define P10_0_PORT GPIO_PRT10 242 #define P10_0_PIN 0u 243 #define P10_0_NUM 0u 244 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 245 #define P10_1_PORT GPIO_PRT10 246 #define P10_1_PIN 1u 247 #define P10_1_NUM 1u 248 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 249 #define P10_2_PORT GPIO_PRT10 250 #define P10_2_PIN 2u 251 #define P10_2_NUM 2u 252 #define P10_2_AMUXSEGMENT AMUXBUS_SAR 253 #define P10_3_PORT GPIO_PRT10 254 #define P10_3_PIN 3u 255 #define P10_3_NUM 3u 256 #define P10_3_AMUXSEGMENT AMUXBUS_SAR 257 #define P10_4_PORT GPIO_PRT10 258 #define P10_4_PIN 4u 259 #define P10_4_NUM 4u 260 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 261 #define P10_5_PORT GPIO_PRT10 262 #define P10_5_PIN 5u 263 #define P10_5_NUM 5u 264 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 265 #define P10_6_PORT GPIO_PRT10 266 #define P10_6_PIN 6u 267 #define P10_6_NUM 6u 268 #define P10_6_AMUXSEGMENT AMUXBUS_SAR 269 #define P10_7_PORT GPIO_PRT10 270 #define P10_7_PIN 7u 271 #define P10_7_NUM 7u 272 #define P10_7_AMUXSEGMENT AMUXBUS_SAR 273 274 /* PORT 11 (GPIO) */ 275 #define P11_1_PORT GPIO_PRT11 276 #define P11_1_PIN 1u 277 #define P11_1_NUM 1u 278 #define P11_2_PORT GPIO_PRT11 279 #define P11_2_PIN 2u 280 #define P11_2_NUM 2u 281 #define P11_3_PORT GPIO_PRT11 282 #define P11_3_PIN 3u 283 #define P11_3_NUM 3u 284 #define P11_4_PORT GPIO_PRT11 285 #define P11_4_PIN 4u 286 #define P11_4_NUM 4u 287 #define P11_5_PORT GPIO_PRT11 288 #define P11_5_PIN 5u 289 #define P11_5_NUM 5u 290 #define P11_6_PORT GPIO_PRT11 291 #define P11_6_PIN 6u 292 #define P11_6_NUM 6u 293 #define P11_7_PORT GPIO_PRT11 294 #define P11_7_PIN 7u 295 #define P11_7_NUM 7u 296 297 /* PORT 12 (GPIO) */ 298 #define P12_6_PORT GPIO_PRT12 299 #define P12_6_PIN 6u 300 #define P12_6_NUM 6u 301 #define P12_7_PORT GPIO_PRT12 302 #define P12_7_PIN 7u 303 #define P12_7_NUM 7u 304 305 /* Analog Connections */ 306 #define CSD_CMODPADD_PORT 7u 307 #define CSD_CMODPADD_PIN 1u 308 #define CSD_CMODPADS_PORT 7u 309 #define CSD_CMODPADS_PIN 1u 310 #define CSD_CSH_TANKPADD_PORT 7u 311 #define CSD_CSH_TANKPADD_PIN 2u 312 #define CSD_CSH_TANKPADS_PORT 7u 313 #define CSD_CSH_TANKPADS_PIN 2u 314 #define CSD_CSHIELDPADS_PORT 7u 315 #define CSD_CSHIELDPADS_PIN 7u 316 #define CSD_VREF_EXT_PORT 7u 317 #define CSD_VREF_EXT_PIN 3u 318 #define IOSS_ADFT0_NET_PORT 10u 319 #define IOSS_ADFT0_NET_PIN 0u 320 #define IOSS_ADFT1_NET_PORT 10u 321 #define IOSS_ADFT1_NET_PIN 1u 322 #define LPCOMP_INN_COMP0_PORT 5u 323 #define LPCOMP_INN_COMP0_PIN 7u 324 #define LPCOMP_INN_COMP1_PORT 6u 325 #define LPCOMP_INN_COMP1_PIN 3u 326 #define LPCOMP_INP_COMP0_PORT 5u 327 #define LPCOMP_INP_COMP0_PIN 6u 328 #define LPCOMP_INP_COMP1_PORT 6u 329 #define LPCOMP_INP_COMP1_PIN 2u 330 #define PASS_AREF_EXT_VREF_PORT 9u 331 #define PASS_AREF_EXT_VREF_PIN 5u 332 #define PASS_CTB_OA0_OUT_10X_PORT 9u 333 #define PASS_CTB_OA0_OUT_10X_PIN 2u 334 #define PASS_CTB_OA1_OUT_10X_PORT 9u 335 #define PASS_CTB_OA1_OUT_10X_PIN 3u 336 #define PASS_CTB_PADS0_PORT 9u 337 #define PASS_CTB_PADS0_PIN 0u 338 #define PASS_CTB_PADS1_PORT 9u 339 #define PASS_CTB_PADS1_PIN 1u 340 #define PASS_CTB_PADS2_PORT 9u 341 #define PASS_CTB_PADS2_PIN 2u 342 #define PASS_CTB_PADS3_PORT 9u 343 #define PASS_CTB_PADS3_PIN 3u 344 #define PASS_CTB_PADS4_PORT 9u 345 #define PASS_CTB_PADS4_PIN 4u 346 #define PASS_CTB_PADS5_PORT 9u 347 #define PASS_CTB_PADS5_PIN 5u 348 #define PASS_SARMUX_PADS0_PORT 10u 349 #define PASS_SARMUX_PADS0_PIN 0u 350 #define PASS_SARMUX_PADS1_PORT 10u 351 #define PASS_SARMUX_PADS1_PIN 1u 352 #define PASS_SARMUX_PADS10_PORT 10u 353 #define PASS_SARMUX_PADS10_PIN 2u 354 #define PASS_SARMUX_PADS11_PORT 10u 355 #define PASS_SARMUX_PADS11_PIN 3u 356 #define PASS_SARMUX_PADS12_PORT 10u 357 #define PASS_SARMUX_PADS12_PIN 4u 358 #define PASS_SARMUX_PADS13_PORT 10u 359 #define PASS_SARMUX_PADS13_PIN 5u 360 #define PASS_SARMUX_PADS14_PORT 10u 361 #define PASS_SARMUX_PADS14_PIN 6u 362 #define PASS_SARMUX_PADS15_PORT 10u 363 #define PASS_SARMUX_PADS15_PIN 7u 364 #define PASS_SARMUX_PADS2_PORT 10u 365 #define PASS_SARMUX_PADS2_PIN 2u 366 #define PASS_SARMUX_PADS3_PORT 10u 367 #define PASS_SARMUX_PADS3_PIN 3u 368 #define PASS_SARMUX_PADS4_PORT 10u 369 #define PASS_SARMUX_PADS4_PIN 4u 370 #define PASS_SARMUX_PADS5_PORT 10u 371 #define PASS_SARMUX_PADS5_PIN 5u 372 #define PASS_SARMUX_PADS6_PORT 10u 373 #define PASS_SARMUX_PADS6_PIN 6u 374 #define PASS_SARMUX_PADS7_PORT 10u 375 #define PASS_SARMUX_PADS7_PIN 7u 376 #define PASS_SARMUX_PADS8_PORT 10u 377 #define PASS_SARMUX_PADS8_PIN 0u 378 #define PASS_SARMUX_PADS9_PORT 10u 379 #define PASS_SARMUX_PADS9_PIN 1u 380 #define SRSS_ADFT_PIN0_PORT 10u 381 #define SRSS_ADFT_PIN0_PIN 0u 382 #define SRSS_ADFT_PIN1_PORT 10u 383 #define SRSS_ADFT_PIN1_PIN 1u 384 #define SRSS_ECO_IN_PORT 12u 385 #define SRSS_ECO_IN_PIN 6u 386 #define SRSS_ECO_OUT_PORT 12u 387 #define SRSS_ECO_OUT_PIN 7u 388 #define SRSS_WCO_IN_PORT 0u 389 #define SRSS_WCO_IN_PIN 0u 390 #define SRSS_WCO_OUT_PORT 0u 391 #define SRSS_WCO_OUT_PIN 1u 392 393 /* HSIOM Connections */ 394 typedef enum 395 { 396 /* Generic HSIOM connections */ 397 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 398 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 399 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 400 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 401 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 402 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 403 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 404 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 405 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 406 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 407 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 408 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 409 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 410 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 411 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 412 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 413 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 414 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 415 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 416 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 417 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 418 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 419 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 420 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 421 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 422 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 423 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 424 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 425 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 426 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 427 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 428 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 429 430 /* P0.0 */ 431 P0_0_GPIO = 0, /* GPIO controls 'out' */ 432 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 433 P0_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ 434 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 435 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 436 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 437 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 438 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 439 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 440 P0_0_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 441 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 442 443 /* P0.1 */ 444 P0_1_GPIO = 0, /* GPIO controls 'out' */ 445 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 446 P0_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 447 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 448 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 449 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 450 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 451 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 452 P0_1_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 453 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 454 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 455 456 /* P0.2 */ 457 P0_2_GPIO = 0, /* GPIO controls 'out' */ 458 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 459 P0_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ 460 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 461 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 462 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 463 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 464 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 465 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 466 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 467 P0_2_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:0 */ 468 469 /* P0.3 */ 470 P0_3_GPIO = 0, /* GPIO controls 'out' */ 471 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 472 P0_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 473 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 474 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 475 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 476 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 477 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 478 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 479 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 480 P0_3_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 481 482 /* P0.4 */ 483 P0_4_GPIO = 0, /* GPIO controls 'out' */ 484 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 485 P0_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ 486 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 487 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 488 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 489 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 490 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 491 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 492 P0_4_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:0 */ 493 P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 494 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 495 496 /* P0.5 */ 497 P0_5_GPIO = 0, /* GPIO controls 'out' */ 498 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 499 P0_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 500 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 501 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 502 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 503 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 504 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 505 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 506 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 507 P0_5_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:0 */ 508 P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 509 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 510 511 /* P1.0 */ 512 P1_0_GPIO = 0, /* GPIO controls 'out' */ 513 P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 514 P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 515 P1_0_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:0 */ 516 517 /* P1.1 */ 518 P1_1_GPIO = 0, /* GPIO controls 'out' */ 519 P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 520 P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 521 P1_1_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:0 */ 522 523 /* P1.2 */ 524 P1_2_GPIO = 0, /* GPIO controls 'out' */ 525 P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ 526 P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ 527 P1_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:0 */ 528 529 /* P2.0 */ 530 P2_0_GPIO = 0, /* GPIO controls 'out' */ 531 P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 532 P2_0_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ 533 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 534 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 535 P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 536 P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 537 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 538 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 539 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 540 P2_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:0 */ 541 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 542 543 /* P2.1 */ 544 P2_1_GPIO = 0, /* GPIO controls 'out' */ 545 P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 546 P2_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ 547 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 548 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 549 P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 550 P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 551 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 552 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 553 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 554 P2_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:0 */ 555 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 556 557 /* P2.2 */ 558 P2_2_GPIO = 0, /* GPIO controls 'out' */ 559 P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 560 P2_2_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ 561 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 562 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 563 P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 564 P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 565 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 566 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 567 P2_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:0 */ 568 569 /* P2.3 */ 570 P2_3_GPIO = 0, /* GPIO controls 'out' */ 571 P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 572 P2_3_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 573 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 574 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 575 P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 576 P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 577 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 578 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 579 P2_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ 580 581 /* P2.4 */ 582 P2_4_GPIO = 0, /* GPIO controls 'out' */ 583 P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 584 P2_4_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ 585 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 586 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 587 P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 588 P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 589 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 590 P2_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ 591 592 /* P2.5 */ 593 P2_5_GPIO = 0, /* GPIO controls 'out' */ 594 P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 595 P2_5_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 596 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 597 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 598 P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 599 P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 600 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 601 P2_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:1 */ 602 603 /* P2.6 */ 604 P2_6_GPIO = 0, /* GPIO controls 'out' */ 605 P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 606 P2_6_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ 607 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 608 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 609 P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 610 P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 611 P2_6_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 612 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 613 P2_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ 614 P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 615 616 /* P2.7 */ 617 P2_7_GPIO = 0, /* GPIO controls 'out' */ 618 P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 619 P2_7_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 620 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 621 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 622 P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 623 P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 624 P2_7_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 625 P2_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:1 */ 626 P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 627 628 /* P3.0 */ 629 P3_0_GPIO = 0, /* GPIO controls 'out' */ 630 P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 631 P3_0_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:0 */ 632 P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 633 P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 634 P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 635 P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 636 P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 637 P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 638 P3_0_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:1 */ 639 P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 640 641 /* P3.1 */ 642 P3_1_GPIO = 0, /* GPIO controls 'out' */ 643 P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 644 P3_1_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ 645 P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 646 P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 647 P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 648 P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 649 P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 650 P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 651 P3_1_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:1 */ 652 P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 653 654 /* P5.0 */ 655 P5_0_GPIO = 0, /* GPIO controls 'out' */ 656 P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 657 P5_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ 658 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 659 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 660 P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 661 P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 662 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 663 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 664 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 665 P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ 666 P5_0_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:1 */ 667 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 668 669 /* P5.1 */ 670 P5_1_GPIO = 0, /* GPIO controls 'out' */ 671 P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 672 P5_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ 673 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ 674 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ 675 P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 676 P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 677 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 678 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 679 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 680 P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ 681 P5_1_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:1 */ 682 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 683 684 /* P5.2 */ 685 P5_2_GPIO = 0, /* GPIO controls 'out' */ 686 P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */ 687 P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */ 688 P5_2_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:1 */ 689 690 /* P5.6 */ 691 P5_6_GPIO = 0, /* GPIO controls 'out' */ 692 P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 693 P5_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ 694 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ 695 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ 696 P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 697 P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 698 P5_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:1 */ 699 700 /* P5.7 */ 701 P5_7_GPIO = 0, /* GPIO controls 'out' */ 702 P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 703 P5_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ 704 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ 705 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ 706 P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 707 P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 708 P5_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:1 */ 709 710 /* P6.2 */ 711 P6_2_GPIO = 0, /* GPIO controls 'out' */ 712 P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 713 P6_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ 714 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ 715 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ 716 P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ 717 P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ 718 P6_2_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:2 */ 719 P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 720 721 /* P6.3 */ 722 P6_3_GPIO = 0, /* GPIO controls 'out' */ 723 P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 724 P6_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ 725 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ 726 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ 727 P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ 728 P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ 729 P6_3_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:2 */ 730 P6_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 731 732 /* P6.4 */ 733 P6_4_GPIO = 0, /* GPIO controls 'out' */ 734 P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 735 P6_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ 736 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ 737 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ 738 P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ 739 P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ 740 P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ 741 P6_4_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:2 */ 742 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 743 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 744 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 745 P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ 746 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 747 748 /* P6.5 */ 749 P6_5_GPIO = 0, /* GPIO controls 'out' */ 750 P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 751 P6_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ 752 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ 753 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ 754 P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ 755 P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ 756 P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ 757 P6_5_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:2 */ 758 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 759 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 760 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 761 P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ 762 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 763 764 /* P6.6 */ 765 P6_6_GPIO = 0, /* GPIO controls 'out' */ 766 P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 767 P6_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ 768 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ 769 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ 770 P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ 771 P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ 772 P6_6_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:2 */ 773 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 774 P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ 775 776 /* P6.7 */ 777 P6_7_GPIO = 0, /* GPIO controls 'out' */ 778 P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 779 P6_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 780 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ 781 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ 782 P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ 783 P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ 784 P6_7_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:2 */ 785 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 786 P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ 787 788 /* P7.0 */ 789 P7_0_GPIO = 0, /* GPIO controls 'out' */ 790 P7_0_AMUXA = 4, /* Analog mux bus A */ 791 P7_0_AMUXB = 5, /* Analog mux bus B */ 792 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 793 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 794 P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 795 P7_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:1 */ 796 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 797 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 798 P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ 799 P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ 800 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 801 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 802 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 803 P7_0_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:2 */ 804 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 805 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 806 807 /* P7.1 */ 808 P7_1_GPIO = 0, /* GPIO controls 'out' */ 809 P7_1_AMUXA = 4, /* Analog mux bus A */ 810 P7_1_AMUXB = 5, /* Analog mux bus B */ 811 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 812 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 813 P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ 814 P7_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 815 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 816 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 817 P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ 818 P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ 819 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 820 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 821 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 822 P7_1_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:2 */ 823 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 824 825 /* P7.2 */ 826 P7_2_GPIO = 0, /* GPIO controls 'out' */ 827 P7_2_AMUXA = 4, /* Analog mux bus A */ 828 P7_2_AMUXB = 5, /* Analog mux bus B */ 829 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 830 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 831 P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 832 P7_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:1 */ 833 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 834 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 835 P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 836 P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 837 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 838 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 839 P7_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:2 */ 840 841 /* P7.3 */ 842 P7_3_GPIO = 0, /* GPIO controls 'out' */ 843 P7_3_AMUXA = 4, /* Analog mux bus A */ 844 P7_3_AMUXB = 5, /* Analog mux bus B */ 845 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 846 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 847 P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 848 P7_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ 849 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 850 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 851 P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 852 P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 853 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 854 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 855 P7_3_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:2 */ 856 857 /* P7.4 */ 858 P7_4_GPIO = 0, /* GPIO controls 'out' */ 859 P7_4_AMUXA = 4, /* Analog mux bus A */ 860 P7_4_AMUXB = 5, /* Analog mux bus B */ 861 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 862 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 863 P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ 864 P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ 865 P7_4_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 866 P7_4_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 867 P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ 868 P7_4_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:2 */ 869 870 /* P7.5 */ 871 P7_5_GPIO = 0, /* GPIO controls 'out' */ 872 P7_5_AMUXA = 4, /* Analog mux bus A */ 873 P7_5_AMUXB = 5, /* Analog mux bus B */ 874 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 875 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 876 P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 877 P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 878 P7_5_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ 879 P7_5_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ 880 P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */ 881 P7_5_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:2 */ 882 883 /* P7.7 */ 884 P7_7_GPIO = 0, /* GPIO controls 'out' */ 885 P7_7_AMUXA = 4, /* Analog mux bus A */ 886 P7_7_AMUXB = 5, /* Analog mux bus B */ 887 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 888 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 889 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 890 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 891 P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 892 P7_7_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 893 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 894 P7_7_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:3 */ 895 896 /* P8.0 */ 897 P8_0_GPIO = 0, /* GPIO controls 'out' */ 898 P8_0_AMUXA = 4, /* Analog mux bus A */ 899 P8_0_AMUXB = 5, /* Analog mux bus B */ 900 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 901 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 902 P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 903 P8_0_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ 904 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 905 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 906 P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 907 P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 908 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 909 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 910 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 911 P8_0_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:3 */ 912 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 913 914 /* P8.1 */ 915 P8_1_GPIO = 0, /* GPIO controls 'out' */ 916 P8_1_AMUXA = 4, /* Analog mux bus A */ 917 P8_1_AMUXB = 5, /* Analog mux bus B */ 918 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 919 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 920 P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 921 P8_1_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ 922 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 923 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 924 P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 925 P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 926 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 927 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 928 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 929 P8_1_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:3 */ 930 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 931 932 /* P9.0 */ 933 P9_0_GPIO = 0, /* GPIO controls 'out' */ 934 P9_0_AMUXA = 4, /* Analog mux bus A */ 935 P9_0_AMUXB = 5, /* Analog mux bus B */ 936 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 937 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 938 P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 939 P9_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:2 */ 940 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 941 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 942 P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 943 P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 944 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 945 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 946 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 947 P9_0_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:3 */ 948 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 949 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 950 951 /* P9.1 */ 952 P9_1_GPIO = 0, /* GPIO controls 'out' */ 953 P9_1_AMUXA = 4, /* Analog mux bus A */ 954 P9_1_AMUXB = 5, /* Analog mux bus B */ 955 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 956 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 957 P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 958 P9_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:2 */ 959 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 960 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 961 P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 962 P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 963 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 964 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 965 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 966 P9_1_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:3 */ 967 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 968 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 969 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 970 971 /* P9.2 */ 972 P9_2_GPIO = 0, /* GPIO controls 'out' */ 973 P9_2_AMUXA = 4, /* Analog mux bus A */ 974 P9_2_AMUXB = 5, /* Analog mux bus B */ 975 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 976 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 977 P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 978 P9_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:2 */ 979 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 980 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 981 P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 982 P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 983 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 984 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 985 P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ 986 P9_2_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:3 */ 987 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 988 989 /* P9.3 */ 990 P9_3_GPIO = 0, /* GPIO controls 'out' */ 991 P9_3_AMUXA = 4, /* Analog mux bus A */ 992 P9_3_AMUXB = 5, /* Analog mux bus B */ 993 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 994 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 995 P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 996 P9_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:3 */ 997 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 998 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 999 P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 1000 P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 1001 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1002 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1003 P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ 1004 P9_3_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:3 */ 1005 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1006 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1007 1008 /* P9.4 */ 1009 P9_4_GPIO = 0, /* GPIO controls 'out' */ 1010 P9_4_AMUXA = 4, /* Analog mux bus A */ 1011 P9_4_AMUXB = 5, /* Analog mux bus B */ 1012 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1013 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1014 P9_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:3 */ 1015 P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 1016 P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 1017 P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ 1018 P9_4_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:3 */ 1019 1020 /* P9.5 */ 1021 P9_5_GPIO = 0, /* GPIO controls 'out' */ 1022 P9_5_AMUXA = 4, /* Analog mux bus A */ 1023 P9_5_AMUXB = 5, /* Analog mux bus B */ 1024 P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1025 P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1026 P9_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:3 */ 1027 P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 1028 P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 1029 P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */ 1030 P9_5_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:3 */ 1031 1032 /* P10.0 */ 1033 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1034 P10_0_AMUXA = 4, /* Analog mux bus A */ 1035 P10_0_AMUXB = 5, /* Analog mux bus B */ 1036 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1037 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1038 P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ 1039 P10_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:2 */ 1040 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 1041 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 1042 P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 1043 P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 1044 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 1045 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 1046 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 1047 P10_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:3 */ 1048 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1049 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1050 1051 /* P10.1 */ 1052 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1053 P10_1_AMUXA = 4, /* Analog mux bus A */ 1054 P10_1_AMUXB = 5, /* Analog mux bus B */ 1055 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1056 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1057 P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ 1058 P10_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:2 */ 1059 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 1060 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 1061 P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 1062 P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 1063 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 1064 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 1065 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 1066 P10_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:3 */ 1067 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1068 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1069 1070 /* P10.2 */ 1071 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1072 P10_2_AMUXA = 4, /* Analog mux bus A */ 1073 P10_2_AMUXB = 5, /* Analog mux bus B */ 1074 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1075 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1076 P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ 1077 P10_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:2 */ 1078 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1079 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1080 P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 1081 P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 1082 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 1083 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 1084 P10_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:3 */ 1085 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1086 1087 /* P10.3 */ 1088 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1089 P10_3_AMUXA = 4, /* Analog mux bus A */ 1090 P10_3_AMUXB = 5, /* Analog mux bus B */ 1091 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1092 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1093 P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ 1094 P10_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:2 */ 1095 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1096 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1097 P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1098 P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1099 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 1100 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 1101 P10_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:4 */ 1102 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1103 1104 /* P10.4 */ 1105 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1106 P10_4_AMUXA = 4, /* Analog mux bus A */ 1107 P10_4_AMUXB = 5, /* Analog mux bus B */ 1108 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1109 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1110 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 1111 P10_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:2 */ 1112 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1113 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1114 P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1115 P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1116 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 1117 P10_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:4 */ 1118 1119 /* P10.5 */ 1120 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1121 P10_5_AMUXA = 4, /* Analog mux bus A */ 1122 P10_5_AMUXB = 5, /* Analog mux bus B */ 1123 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1124 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1125 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 1126 P10_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:2 */ 1127 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ 1128 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ 1129 P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1130 P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1131 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 1132 P10_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:4 */ 1133 1134 /* P10.6 */ 1135 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1136 P10_6_AMUXA = 4, /* Analog mux bus A */ 1137 P10_6_AMUXB = 5, /* Analog mux bus B */ 1138 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1139 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1140 P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 1141 P10_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:2 */ 1142 P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ 1143 P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ 1144 P10_6_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ 1145 P10_6_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ 1146 P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 1147 P10_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:4 */ 1148 P10_6_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1149 1150 /* P10.7 */ 1151 P10_7_GPIO = 0, /* GPIO controls 'out' */ 1152 P10_7_AMUXA = 4, /* Analog mux bus A */ 1153 P10_7_AMUXB = 5, /* Analog mux bus B */ 1154 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1155 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1156 P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 1157 P10_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:2 */ 1158 P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 1159 P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 1160 P10_7_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ 1161 P10_7_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ 1162 P10_7_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1163 P10_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:4 */ 1164 P10_7_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1165 1166 /* P11.1 */ 1167 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1168 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1169 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1170 P11_1_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1171 P11_1_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1172 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1173 P11_1_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:4 */ 1174 1175 /* P11.2 */ 1176 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1177 P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ 1178 P11_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:2 */ 1179 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1180 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1181 P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1182 P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1183 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1184 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 1185 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 1186 P11_2_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:4 */ 1187 1188 /* P11.3 */ 1189 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1190 P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ 1191 P11_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ 1192 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1193 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1194 P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1195 P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1196 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1197 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 1198 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 1199 P11_3_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:4 */ 1200 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1201 1202 /* P11.4 */ 1203 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1204 P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 1205 P11_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:3 */ 1206 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1207 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1208 P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1209 P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1210 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1211 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 1212 P11_4_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:4 */ 1213 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1214 1215 /* P11.5 */ 1216 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1217 P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1218 P11_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:3 */ 1219 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1220 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1221 P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1222 P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1223 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1224 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 1225 P11_5_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:4 */ 1226 1227 /* P11.6 */ 1228 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1229 P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ 1230 P11_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:3 */ 1231 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1232 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1233 P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1234 P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1235 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1236 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 1237 P11_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:4 */ 1238 1239 /* P11.7 */ 1240 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1241 P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ 1242 P11_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:2 */ 1243 P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1244 P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1245 P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1246 P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1247 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1248 P11_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:4 */ 1249 1250 /* P12.6 */ 1251 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1252 P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ 1253 P12_6_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:3 */ 1254 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ 1255 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ 1256 P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1257 P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1258 P12_6_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:5 */ 1259 1260 /* P12.7 */ 1261 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1262 P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ 1263 P12_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:3 */ 1264 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ 1265 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ 1266 P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1267 P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1268 P12_7_TCPWM0_TR_ONE_CNT_IN1 = 23 /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:5 */ 1269 } en_hsiom_sel_t; 1270 1271 #endif /* _GPIO_PSOC6_04_80_TQFP_H_ */ 1272 1273 1274 /* [] END OF FILE */ 1275
