1 /***************************************************************************//** 2 * \file gpio_psoc6_04_64_tqfp.h 3 * 4 * \brief 5 * PSoC6_04 device GPIO header for 64-TQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_04_64_TQFP_H_ 28 #define _GPIO_PSOC6_04_64_TQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_TQFP 44 #define CY_GPIO_PIN_COUNT 64u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ANALOG_VDDD, 50 AMUXBUS_CSD0, 51 AMUXBUS_CSD1, 52 AMUXBUS_MAIN, 53 AMUXBUS_SAR, 54 AMUXBUS_VDDIO_1, 55 AMUXBUS_VSSA, 56 AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, 57 AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, 58 }; 59 60 /* AMUX Splitter Controls */ 61 typedef enum 62 { 63 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_MAIN */ 64 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 65 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 66 AMUX_SPLIT_CTL_5 = 0x0005u /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 67 } cy_en_amux_split_t; 68 69 /* Port List */ 70 /* PORT 0 (GPIO) */ 71 #define P0_0_PORT GPIO_PRT0 72 #define P0_0_PIN 0u 73 #define P0_0_NUM 0u 74 #define P0_1_PORT GPIO_PRT0 75 #define P0_1_PIN 1u 76 #define P0_1_NUM 1u 77 #define P0_2_PORT GPIO_PRT0 78 #define P0_2_PIN 2u 79 #define P0_2_NUM 2u 80 #define P0_3_PORT GPIO_PRT0 81 #define P0_3_PIN 3u 82 #define P0_3_NUM 3u 83 #define P0_4_PORT GPIO_PRT0 84 #define P0_4_PIN 4u 85 #define P0_4_NUM 4u 86 #define P0_5_PORT GPIO_PRT0 87 #define P0_5_PIN 5u 88 #define P0_5_NUM 5u 89 90 /* PORT 2 (GPIO) */ 91 #define P2_0_PORT GPIO_PRT2 92 #define P2_0_PIN 0u 93 #define P2_0_NUM 0u 94 #define P2_1_PORT GPIO_PRT2 95 #define P2_1_PIN 1u 96 #define P2_1_NUM 1u 97 #define P2_2_PORT GPIO_PRT2 98 #define P2_2_PIN 2u 99 #define P2_2_NUM 2u 100 #define P2_3_PORT GPIO_PRT2 101 #define P2_3_PIN 3u 102 #define P2_3_NUM 3u 103 #define P2_4_PORT GPIO_PRT2 104 #define P2_4_PIN 4u 105 #define P2_4_NUM 4u 106 #define P2_5_PORT GPIO_PRT2 107 #define P2_5_PIN 5u 108 #define P2_5_NUM 5u 109 #define P2_6_PORT GPIO_PRT2 110 #define P2_6_PIN 6u 111 #define P2_6_NUM 6u 112 #define P2_7_PORT GPIO_PRT2 113 #define P2_7_PIN 7u 114 #define P2_7_NUM 7u 115 116 /* PORT 3 (GPIO_OVT) */ 117 #define P3_0_PORT GPIO_PRT3 118 #define P3_0_PIN 0u 119 #define P3_0_NUM 0u 120 #define P3_0_AMUXSEGMENT AMUXBUS_VSSA 121 #define P3_1_PORT GPIO_PRT3 122 #define P3_1_PIN 1u 123 #define P3_1_NUM 1u 124 #define P3_1_AMUXSEGMENT AMUXBUS_VSSA 125 126 /* PORT 5 (GPIO) */ 127 #define P5_0_PORT GPIO_PRT5 128 #define P5_0_PIN 0u 129 #define P5_0_NUM 0u 130 #define P5_1_PORT GPIO_PRT5 131 #define P5_1_PIN 1u 132 #define P5_1_NUM 1u 133 #define P5_6_PORT GPIO_PRT5 134 #define P5_6_PIN 6u 135 #define P5_6_NUM 6u 136 #define P5_7_PORT GPIO_PRT5 137 #define P5_7_PIN 7u 138 #define P5_7_NUM 7u 139 140 /* PORT 6 (GPIO) */ 141 #define P6_2_PORT GPIO_PRT6 142 #define P6_2_PIN 2u 143 #define P6_2_NUM 2u 144 #define P6_3_PORT GPIO_PRT6 145 #define P6_3_PIN 3u 146 #define P6_3_NUM 3u 147 #define P6_4_PORT GPIO_PRT6 148 #define P6_4_PIN 4u 149 #define P6_4_NUM 4u 150 #define P6_5_PORT GPIO_PRT6 151 #define P6_5_PIN 5u 152 #define P6_5_NUM 5u 153 #define P6_6_PORT GPIO_PRT6 154 #define P6_6_PIN 6u 155 #define P6_6_NUM 6u 156 #define P6_7_PORT GPIO_PRT6 157 #define P6_7_PIN 7u 158 #define P6_7_NUM 7u 159 160 /* PORT 7 (GPIO) */ 161 #define P7_0_PORT GPIO_PRT7 162 #define P7_0_PIN 0u 163 #define P7_0_NUM 0u 164 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 165 #define P7_1_PORT GPIO_PRT7 166 #define P7_1_PIN 1u 167 #define P7_1_NUM 1u 168 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 169 #define P7_2_PORT GPIO_PRT7 170 #define P7_2_PIN 2u 171 #define P7_2_NUM 2u 172 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 173 #define P7_3_PORT GPIO_PRT7 174 #define P7_3_PIN 3u 175 #define P7_3_NUM 3u 176 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 177 178 /* PORT 8 (GPIO) */ 179 #define P8_0_PORT GPIO_PRT8 180 #define P8_0_PIN 0u 181 #define P8_0_NUM 0u 182 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 183 #define P8_1_PORT GPIO_PRT8 184 #define P8_1_PIN 1u 185 #define P8_1_NUM 1u 186 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 187 188 /* PORT 9 (GPIO) */ 189 #define P9_0_PORT GPIO_PRT9 190 #define P9_0_PIN 0u 191 #define P9_0_NUM 0u 192 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 193 #define P9_1_PORT GPIO_PRT9 194 #define P9_1_PIN 1u 195 #define P9_1_NUM 1u 196 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 197 #define P9_2_PORT GPIO_PRT9 198 #define P9_2_PIN 2u 199 #define P9_2_NUM 2u 200 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 201 #define P9_3_PORT GPIO_PRT9 202 #define P9_3_PIN 3u 203 #define P9_3_NUM 3u 204 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 205 #define P9_4_PORT GPIO_PRT9 206 #define P9_4_PIN 4u 207 #define P9_4_NUM 4u 208 #define P9_4_AMUXSEGMENT AMUXBUS_SAR 209 #define P9_5_PORT GPIO_PRT9 210 #define P9_5_PIN 5u 211 #define P9_5_NUM 5u 212 #define P9_5_AMUXSEGMENT AMUXBUS_SAR 213 214 /* PORT 10 (GPIO) */ 215 #define P10_0_PORT GPIO_PRT10 216 #define P10_0_PIN 0u 217 #define P10_0_NUM 0u 218 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 219 #define P10_1_PORT GPIO_PRT10 220 #define P10_1_PIN 1u 221 #define P10_1_NUM 1u 222 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 223 #define P10_2_PORT GPIO_PRT10 224 #define P10_2_PIN 2u 225 #define P10_2_NUM 2u 226 #define P10_2_AMUXSEGMENT AMUXBUS_SAR 227 #define P10_3_PORT GPIO_PRT10 228 #define P10_3_PIN 3u 229 #define P10_3_NUM 3u 230 #define P10_3_AMUXSEGMENT AMUXBUS_SAR 231 #define P10_4_PORT GPIO_PRT10 232 #define P10_4_PIN 4u 233 #define P10_4_NUM 4u 234 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 235 #define P10_5_PORT GPIO_PRT10 236 #define P10_5_PIN 5u 237 #define P10_5_NUM 5u 238 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 239 #define P10_6_PORT GPIO_PRT10 240 #define P10_6_PIN 6u 241 #define P10_6_NUM 6u 242 #define P10_6_AMUXSEGMENT AMUXBUS_SAR 243 #define P10_7_PORT GPIO_PRT10 244 #define P10_7_PIN 7u 245 #define P10_7_NUM 7u 246 #define P10_7_AMUXSEGMENT AMUXBUS_SAR 247 248 /* PORT 11 (GPIO) */ 249 #define P11_2_PORT GPIO_PRT11 250 #define P11_2_PIN 2u 251 #define P11_2_NUM 2u 252 #define P11_3_PORT GPIO_PRT11 253 #define P11_3_PIN 3u 254 #define P11_3_NUM 3u 255 #define P11_4_PORT GPIO_PRT11 256 #define P11_4_PIN 4u 257 #define P11_4_NUM 4u 258 #define P11_5_PORT GPIO_PRT11 259 #define P11_5_PIN 5u 260 #define P11_5_NUM 5u 261 #define P11_6_PORT GPIO_PRT11 262 #define P11_6_PIN 6u 263 #define P11_6_NUM 6u 264 #define P11_7_PORT GPIO_PRT11 265 #define P11_7_PIN 7u 266 #define P11_7_NUM 7u 267 268 /* PORT 12 (GPIO) */ 269 #define P12_6_PORT GPIO_PRT12 270 #define P12_6_PIN 6u 271 #define P12_6_NUM 6u 272 #define P12_7_PORT GPIO_PRT12 273 #define P12_7_PIN 7u 274 #define P12_7_NUM 7u 275 276 /* Analog Connections */ 277 #define CSD_CMODPADD_PORT 7u 278 #define CSD_CMODPADD_PIN 1u 279 #define CSD_CMODPADS_PORT 7u 280 #define CSD_CMODPADS_PIN 1u 281 #define CSD_CSH_TANKPADD_PORT 7u 282 #define CSD_CSH_TANKPADD_PIN 2u 283 #define CSD_CSH_TANKPADS_PORT 7u 284 #define CSD_CSH_TANKPADS_PIN 2u 285 #define CSD_VREF_EXT_PORT 7u 286 #define CSD_VREF_EXT_PIN 3u 287 #define IOSS_ADFT0_NET_PORT 10u 288 #define IOSS_ADFT0_NET_PIN 0u 289 #define IOSS_ADFT1_NET_PORT 10u 290 #define IOSS_ADFT1_NET_PIN 1u 291 #define LPCOMP_INN_COMP0_PORT 5u 292 #define LPCOMP_INN_COMP0_PIN 7u 293 #define LPCOMP_INN_COMP1_PORT 6u 294 #define LPCOMP_INN_COMP1_PIN 3u 295 #define LPCOMP_INP_COMP0_PORT 5u 296 #define LPCOMP_INP_COMP0_PIN 6u 297 #define LPCOMP_INP_COMP1_PORT 6u 298 #define LPCOMP_INP_COMP1_PIN 2u 299 #define PASS_AREF_EXT_VREF_PORT 9u 300 #define PASS_AREF_EXT_VREF_PIN 5u 301 #define PASS_CTB_OA0_OUT_10X_PORT 9u 302 #define PASS_CTB_OA0_OUT_10X_PIN 2u 303 #define PASS_CTB_OA1_OUT_10X_PORT 9u 304 #define PASS_CTB_OA1_OUT_10X_PIN 3u 305 #define PASS_CTB_PADS0_PORT 9u 306 #define PASS_CTB_PADS0_PIN 0u 307 #define PASS_CTB_PADS1_PORT 9u 308 #define PASS_CTB_PADS1_PIN 1u 309 #define PASS_CTB_PADS2_PORT 9u 310 #define PASS_CTB_PADS2_PIN 2u 311 #define PASS_CTB_PADS3_PORT 9u 312 #define PASS_CTB_PADS3_PIN 3u 313 #define PASS_CTB_PADS4_PORT 9u 314 #define PASS_CTB_PADS4_PIN 4u 315 #define PASS_CTB_PADS5_PORT 9u 316 #define PASS_CTB_PADS5_PIN 5u 317 #define PASS_SARMUX_PADS0_PORT 10u 318 #define PASS_SARMUX_PADS0_PIN 0u 319 #define PASS_SARMUX_PADS1_PORT 10u 320 #define PASS_SARMUX_PADS1_PIN 1u 321 #define PASS_SARMUX_PADS10_PORT 10u 322 #define PASS_SARMUX_PADS10_PIN 2u 323 #define PASS_SARMUX_PADS11_PORT 10u 324 #define PASS_SARMUX_PADS11_PIN 3u 325 #define PASS_SARMUX_PADS12_PORT 10u 326 #define PASS_SARMUX_PADS12_PIN 4u 327 #define PASS_SARMUX_PADS13_PORT 10u 328 #define PASS_SARMUX_PADS13_PIN 5u 329 #define PASS_SARMUX_PADS14_PORT 10u 330 #define PASS_SARMUX_PADS14_PIN 6u 331 #define PASS_SARMUX_PADS15_PORT 10u 332 #define PASS_SARMUX_PADS15_PIN 7u 333 #define PASS_SARMUX_PADS2_PORT 10u 334 #define PASS_SARMUX_PADS2_PIN 2u 335 #define PASS_SARMUX_PADS3_PORT 10u 336 #define PASS_SARMUX_PADS3_PIN 3u 337 #define PASS_SARMUX_PADS4_PORT 10u 338 #define PASS_SARMUX_PADS4_PIN 4u 339 #define PASS_SARMUX_PADS5_PORT 10u 340 #define PASS_SARMUX_PADS5_PIN 5u 341 #define PASS_SARMUX_PADS6_PORT 10u 342 #define PASS_SARMUX_PADS6_PIN 6u 343 #define PASS_SARMUX_PADS7_PORT 10u 344 #define PASS_SARMUX_PADS7_PIN 7u 345 #define PASS_SARMUX_PADS8_PORT 10u 346 #define PASS_SARMUX_PADS8_PIN 0u 347 #define PASS_SARMUX_PADS9_PORT 10u 348 #define PASS_SARMUX_PADS9_PIN 1u 349 #define SRSS_ADFT_PIN0_PORT 10u 350 #define SRSS_ADFT_PIN0_PIN 0u 351 #define SRSS_ADFT_PIN1_PORT 10u 352 #define SRSS_ADFT_PIN1_PIN 1u 353 #define SRSS_ECO_IN_PORT 12u 354 #define SRSS_ECO_IN_PIN 6u 355 #define SRSS_ECO_OUT_PORT 12u 356 #define SRSS_ECO_OUT_PIN 7u 357 #define SRSS_WCO_IN_PORT 0u 358 #define SRSS_WCO_IN_PIN 0u 359 #define SRSS_WCO_OUT_PORT 0u 360 #define SRSS_WCO_OUT_PIN 1u 361 362 /* HSIOM Connections */ 363 typedef enum 364 { 365 /* Generic HSIOM connections */ 366 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 367 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 368 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 369 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 370 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 371 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 372 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 373 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 374 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 375 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 376 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 377 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 378 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 379 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 380 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 381 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 382 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 383 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 384 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 385 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 386 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 387 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 388 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 389 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 390 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 391 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 392 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 393 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 394 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 395 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 396 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 397 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 398 399 /* P0.0 */ 400 P0_0_GPIO = 0, /* GPIO controls 'out' */ 401 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 402 P0_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ 403 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 404 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 405 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 406 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 407 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 408 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 409 P0_0_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ 410 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 411 412 /* P0.1 */ 413 P0_1_GPIO = 0, /* GPIO controls 'out' */ 414 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 415 P0_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 416 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 417 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 418 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 419 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 420 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 421 P0_1_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ 422 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 423 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 424 425 /* P0.2 */ 426 P0_2_GPIO = 0, /* GPIO controls 'out' */ 427 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 428 P0_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ 429 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 430 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 431 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 432 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 433 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 434 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 435 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 436 P0_2_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:0 */ 437 438 /* P0.3 */ 439 P0_3_GPIO = 0, /* GPIO controls 'out' */ 440 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 441 P0_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 442 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 443 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 444 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 445 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 446 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 447 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 448 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 449 P0_3_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ 450 451 /* P0.4 */ 452 P0_4_GPIO = 0, /* GPIO controls 'out' */ 453 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 454 P0_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ 455 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 456 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 457 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 458 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 459 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 460 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 461 P0_4_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:0 */ 462 P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 463 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 464 465 /* P0.5 */ 466 P0_5_GPIO = 0, /* GPIO controls 'out' */ 467 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 468 P0_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 469 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 470 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 471 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 472 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 473 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 474 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 475 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 476 P0_5_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:0 */ 477 P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 478 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 479 480 /* P2.0 */ 481 P2_0_GPIO = 0, /* GPIO controls 'out' */ 482 P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 483 P2_0_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ 484 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 485 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 486 P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 487 P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 488 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 489 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 490 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 491 P2_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:0 */ 492 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 493 494 /* P2.1 */ 495 P2_1_GPIO = 0, /* GPIO controls 'out' */ 496 P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 497 P2_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ 498 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 499 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 500 P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 501 P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 502 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 503 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 504 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 505 P2_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:0 */ 506 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 507 508 /* P2.2 */ 509 P2_2_GPIO = 0, /* GPIO controls 'out' */ 510 P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 511 P2_2_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ 512 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 513 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 514 P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 515 P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 516 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 517 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 518 P2_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:0 */ 519 520 /* P2.3 */ 521 P2_3_GPIO = 0, /* GPIO controls 'out' */ 522 P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 523 P2_3_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 524 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 525 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 526 P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 527 P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 528 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 529 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 530 P2_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ 531 532 /* P2.4 */ 533 P2_4_GPIO = 0, /* GPIO controls 'out' */ 534 P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 535 P2_4_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ 536 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 537 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 538 P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 539 P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 540 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 541 P2_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ 542 543 /* P2.5 */ 544 P2_5_GPIO = 0, /* GPIO controls 'out' */ 545 P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 546 P2_5_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 547 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 548 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 549 P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 550 P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 551 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 552 P2_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:1 */ 553 554 /* P2.6 */ 555 P2_6_GPIO = 0, /* GPIO controls 'out' */ 556 P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 557 P2_6_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ 558 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 559 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 560 P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 561 P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 562 P2_6_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 563 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 564 P2_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ 565 P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 566 567 /* P2.7 */ 568 P2_7_GPIO = 0, /* GPIO controls 'out' */ 569 P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 570 P2_7_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 571 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 572 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 573 P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 574 P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 575 P2_7_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 576 P2_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:1 */ 577 P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 578 579 /* P3.0 */ 580 P3_0_GPIO = 0, /* GPIO controls 'out' */ 581 P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 582 P3_0_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:0 */ 583 P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 584 P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 585 P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 586 P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 587 P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 588 P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 589 P3_0_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:1 */ 590 P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 591 592 /* P3.1 */ 593 P3_1_GPIO = 0, /* GPIO controls 'out' */ 594 P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 595 P3_1_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ 596 P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 597 P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 598 P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 599 P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 600 P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 601 P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 602 P3_1_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:1 */ 603 P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 604 605 /* P5.0 */ 606 P5_0_GPIO = 0, /* GPIO controls 'out' */ 607 P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 608 P5_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ 609 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 610 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 611 P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 612 P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 613 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 614 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 615 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 616 P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ 617 P5_0_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:1 */ 618 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 619 620 /* P5.1 */ 621 P5_1_GPIO = 0, /* GPIO controls 'out' */ 622 P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 623 P5_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ 624 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ 625 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ 626 P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 627 P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 628 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 629 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 630 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 631 P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ 632 P5_1_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:1 */ 633 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 634 635 /* P5.6 */ 636 P5_6_GPIO = 0, /* GPIO controls 'out' */ 637 P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 638 P5_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ 639 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ 640 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ 641 P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 642 P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 643 P5_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:1 */ 644 645 /* P5.7 */ 646 P5_7_GPIO = 0, /* GPIO controls 'out' */ 647 P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 648 P5_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ 649 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ 650 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ 651 P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 652 P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 653 P5_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:1 */ 654 655 /* P6.2 */ 656 P6_2_GPIO = 0, /* GPIO controls 'out' */ 657 P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 658 P6_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ 659 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ 660 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ 661 P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ 662 P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ 663 P6_2_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:2 */ 664 P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 665 666 /* P6.3 */ 667 P6_3_GPIO = 0, /* GPIO controls 'out' */ 668 P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 669 P6_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ 670 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ 671 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ 672 P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ 673 P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ 674 P6_3_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:2 */ 675 P6_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 676 677 /* P6.4 */ 678 P6_4_GPIO = 0, /* GPIO controls 'out' */ 679 P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 680 P6_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ 681 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ 682 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ 683 P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ 684 P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ 685 P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ 686 P6_4_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:2 */ 687 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 688 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 689 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 690 P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ 691 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 692 693 /* P6.5 */ 694 P6_5_GPIO = 0, /* GPIO controls 'out' */ 695 P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 696 P6_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ 697 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ 698 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ 699 P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ 700 P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ 701 P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ 702 P6_5_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:2 */ 703 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 704 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 705 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 706 P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ 707 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 708 709 /* P6.6 */ 710 P6_6_GPIO = 0, /* GPIO controls 'out' */ 711 P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 712 P6_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ 713 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ 714 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ 715 P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ 716 P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ 717 P6_6_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:2 */ 718 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 719 P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ 720 721 /* P6.7 */ 722 P6_7_GPIO = 0, /* GPIO controls 'out' */ 723 P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 724 P6_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 725 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ 726 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ 727 P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ 728 P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ 729 P6_7_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:2 */ 730 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 731 P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ 732 733 /* P7.0 */ 734 P7_0_GPIO = 0, /* GPIO controls 'out' */ 735 P7_0_AMUXA = 4, /* Analog mux bus A */ 736 P7_0_AMUXB = 5, /* Analog mux bus B */ 737 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 738 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 739 P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 740 P7_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:1 */ 741 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 742 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 743 P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ 744 P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ 745 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 746 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 747 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 748 P7_0_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:2 */ 749 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 750 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 751 752 /* P7.1 */ 753 P7_1_GPIO = 0, /* GPIO controls 'out' */ 754 P7_1_AMUXA = 4, /* Analog mux bus A */ 755 P7_1_AMUXB = 5, /* Analog mux bus B */ 756 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 757 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 758 P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ 759 P7_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ 760 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 761 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 762 P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ 763 P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ 764 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 765 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 766 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 767 P7_1_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:2 */ 768 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 769 770 /* P7.2 */ 771 P7_2_GPIO = 0, /* GPIO controls 'out' */ 772 P7_2_AMUXA = 4, /* Analog mux bus A */ 773 P7_2_AMUXB = 5, /* Analog mux bus B */ 774 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 775 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 776 P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 777 P7_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:1 */ 778 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 779 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 780 P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 781 P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 782 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 783 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 784 P7_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:2 */ 785 786 /* P7.3 */ 787 P7_3_GPIO = 0, /* GPIO controls 'out' */ 788 P7_3_AMUXA = 4, /* Analog mux bus A */ 789 P7_3_AMUXB = 5, /* Analog mux bus B */ 790 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 791 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 792 P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 793 P7_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ 794 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 795 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 796 P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 797 P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 798 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 799 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 800 P7_3_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:2 */ 801 802 /* P8.0 */ 803 P8_0_GPIO = 0, /* GPIO controls 'out' */ 804 P8_0_AMUXA = 4, /* Analog mux bus A */ 805 P8_0_AMUXB = 5, /* Analog mux bus B */ 806 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 807 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 808 P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 809 P8_0_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ 810 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 811 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 812 P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 813 P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 814 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 815 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 816 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 817 P8_0_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:3 */ 818 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 819 820 /* P8.1 */ 821 P8_1_GPIO = 0, /* GPIO controls 'out' */ 822 P8_1_AMUXA = 4, /* Analog mux bus A */ 823 P8_1_AMUXB = 5, /* Analog mux bus B */ 824 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 825 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 826 P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 827 P8_1_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ 828 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 829 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 830 P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 831 P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 832 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 833 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 834 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 835 P8_1_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:3 */ 836 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 837 838 /* P9.0 */ 839 P9_0_GPIO = 0, /* GPIO controls 'out' */ 840 P9_0_AMUXA = 4, /* Analog mux bus A */ 841 P9_0_AMUXB = 5, /* Analog mux bus B */ 842 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 843 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 844 P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 845 P9_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:2 */ 846 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 847 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 848 P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 849 P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 850 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 851 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 852 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 853 P9_0_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:3 */ 854 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 855 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 856 857 /* P9.1 */ 858 P9_1_GPIO = 0, /* GPIO controls 'out' */ 859 P9_1_AMUXA = 4, /* Analog mux bus A */ 860 P9_1_AMUXB = 5, /* Analog mux bus B */ 861 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 862 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 863 P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 864 P9_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:2 */ 865 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 866 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 867 P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 868 P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 869 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 870 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 871 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 872 P9_1_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:3 */ 873 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 874 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 875 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 876 877 /* P9.2 */ 878 P9_2_GPIO = 0, /* GPIO controls 'out' */ 879 P9_2_AMUXA = 4, /* Analog mux bus A */ 880 P9_2_AMUXB = 5, /* Analog mux bus B */ 881 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 882 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 883 P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 884 P9_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:2 */ 885 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 886 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 887 P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 888 P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 889 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 890 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 891 P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ 892 P9_2_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:3 */ 893 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 894 895 /* P9.3 */ 896 P9_3_GPIO = 0, /* GPIO controls 'out' */ 897 P9_3_AMUXA = 4, /* Analog mux bus A */ 898 P9_3_AMUXB = 5, /* Analog mux bus B */ 899 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 900 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 901 P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 902 P9_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:3 */ 903 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 904 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 905 P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 906 P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 907 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 908 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 909 P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ 910 P9_3_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:3 */ 911 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 912 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 913 914 /* P9.4 */ 915 P9_4_GPIO = 0, /* GPIO controls 'out' */ 916 P9_4_AMUXA = 4, /* Analog mux bus A */ 917 P9_4_AMUXB = 5, /* Analog mux bus B */ 918 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 919 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 920 P9_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:3 */ 921 P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 922 P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 923 P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ 924 P9_4_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:3 */ 925 926 /* P9.5 */ 927 P9_5_GPIO = 0, /* GPIO controls 'out' */ 928 P9_5_AMUXA = 4, /* Analog mux bus A */ 929 P9_5_AMUXB = 5, /* Analog mux bus B */ 930 P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 931 P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 932 P9_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:3 */ 933 P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 934 P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 935 P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */ 936 P9_5_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:3 */ 937 938 /* P10.0 */ 939 P10_0_GPIO = 0, /* GPIO controls 'out' */ 940 P10_0_AMUXA = 4, /* Analog mux bus A */ 941 P10_0_AMUXB = 5, /* Analog mux bus B */ 942 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 943 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 944 P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ 945 P10_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:2 */ 946 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 947 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 948 P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 949 P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 950 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 951 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 952 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 953 P10_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:3 */ 954 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 955 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 956 957 /* P10.1 */ 958 P10_1_GPIO = 0, /* GPIO controls 'out' */ 959 P10_1_AMUXA = 4, /* Analog mux bus A */ 960 P10_1_AMUXB = 5, /* Analog mux bus B */ 961 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 962 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 963 P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ 964 P10_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:2 */ 965 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 966 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 967 P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 968 P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 969 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 970 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 971 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 972 P10_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:3 */ 973 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 974 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 975 976 /* P10.2 */ 977 P10_2_GPIO = 0, /* GPIO controls 'out' */ 978 P10_2_AMUXA = 4, /* Analog mux bus A */ 979 P10_2_AMUXB = 5, /* Analog mux bus B */ 980 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 981 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 982 P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ 983 P10_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:2 */ 984 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 985 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 986 P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 987 P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 988 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 989 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 990 P10_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:3 */ 991 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 992 993 /* P10.3 */ 994 P10_3_GPIO = 0, /* GPIO controls 'out' */ 995 P10_3_AMUXA = 4, /* Analog mux bus A */ 996 P10_3_AMUXB = 5, /* Analog mux bus B */ 997 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 998 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 999 P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ 1000 P10_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:2 */ 1001 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1002 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1003 P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1004 P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1005 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 1006 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 1007 P10_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:4 */ 1008 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1009 1010 /* P10.4 */ 1011 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1012 P10_4_AMUXA = 4, /* Analog mux bus A */ 1013 P10_4_AMUXB = 5, /* Analog mux bus B */ 1014 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1015 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1016 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 1017 P10_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:2 */ 1018 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1019 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1020 P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1021 P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1022 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 1023 P10_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:4 */ 1024 1025 /* P10.5 */ 1026 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1027 P10_5_AMUXA = 4, /* Analog mux bus A */ 1028 P10_5_AMUXB = 5, /* Analog mux bus B */ 1029 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1030 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1031 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 1032 P10_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:2 */ 1033 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ 1034 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ 1035 P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1036 P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1037 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 1038 P10_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:4 */ 1039 1040 /* P10.6 */ 1041 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1042 P10_6_AMUXA = 4, /* Analog mux bus A */ 1043 P10_6_AMUXB = 5, /* Analog mux bus B */ 1044 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1045 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1046 P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 1047 P10_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:2 */ 1048 P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ 1049 P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ 1050 P10_6_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ 1051 P10_6_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ 1052 P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 1053 P10_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:4 */ 1054 P10_6_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1055 1056 /* P10.7 */ 1057 P10_7_GPIO = 0, /* GPIO controls 'out' */ 1058 P10_7_AMUXA = 4, /* Analog mux bus A */ 1059 P10_7_AMUXB = 5, /* Analog mux bus B */ 1060 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1061 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1062 P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 1063 P10_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:2 */ 1064 P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 1065 P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 1066 P10_7_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ 1067 P10_7_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ 1068 P10_7_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1069 P10_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:4 */ 1070 P10_7_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1071 1072 /* P11.2 */ 1073 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1074 P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ 1075 P11_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:2 */ 1076 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1077 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1078 P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1079 P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1080 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1081 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 1082 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 1083 P11_2_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:4 */ 1084 1085 /* P11.3 */ 1086 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1087 P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ 1088 P11_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ 1089 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1090 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1091 P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1092 P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1093 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1094 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 1095 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 1096 P11_3_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:4 */ 1097 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1098 1099 /* P11.4 */ 1100 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1101 P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 1102 P11_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:3 */ 1103 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1104 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1105 P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1106 P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1107 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1108 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 1109 P11_4_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:4 */ 1110 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1111 1112 /* P11.5 */ 1113 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1114 P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1115 P11_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:3 */ 1116 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1117 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1118 P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1119 P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1120 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1121 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 1122 P11_5_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:4 */ 1123 1124 /* P11.6 */ 1125 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1126 P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ 1127 P11_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:3 */ 1128 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1129 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1130 P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1131 P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1132 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1133 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 1134 P11_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:4 */ 1135 1136 /* P11.7 */ 1137 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1138 P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ 1139 P11_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:2 */ 1140 P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1141 P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1142 P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1143 P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1144 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1145 P11_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:4 */ 1146 1147 /* P12.6 */ 1148 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1149 P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ 1150 P12_6_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:3 */ 1151 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ 1152 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ 1153 P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1154 P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1155 P12_6_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:5 */ 1156 1157 /* P12.7 */ 1158 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1159 P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ 1160 P12_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:3 */ 1161 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ 1162 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ 1163 P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1164 P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1165 P12_7_TCPWM0_TR_ONE_CNT_IN1 = 23 /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:5 */ 1166 } en_hsiom_sel_t; 1167 1168 #endif /* _GPIO_PSOC6_04_64_TQFP_H_ */ 1169 1170 1171 /* [] END OF FILE */ 1172
