1 /***************************************************************************//** 2 * \file gpio_psoc6_02_68_qfn.h 3 * 4 * \brief 5 * PSoC6_02 device GPIO header for 68-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_02_68_QFN_H_ 28 #define _GPIO_PSOC6_02_68_QFN_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN 44 #define CY_GPIO_PIN_COUNT 68u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ADFT0_VDDD, 50 AMUXBUS_ANALOG_VDDA, 51 AMUXBUS_ANALOG_VDDD, 52 AMUXBUS_CSD0, 53 AMUXBUS_CSD1, 54 AMUXBUS_MAIN, 55 AMUXBUS_NOISY, 56 AMUXBUS_SAR, 57 AMUXBUS_VDDIO_1, 58 }; 59 60 /* AMUX Splitter Controls */ 61 typedef enum 62 { 63 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ 64 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ 65 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_NOISY; Right = AMUXBUS_CSD0 */ 66 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ 67 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 68 AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 69 AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 70 AMUX_SPLIT_CTL_7 = 0x0007u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ 71 } cy_en_amux_split_t; 72 73 /* Port List */ 74 /* PORT 0 (GPIO) */ 75 #define P0_0_PORT GPIO_PRT0 76 #define P0_0_PIN 0u 77 #define P0_0_NUM 0u 78 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 79 #define P0_1_PORT GPIO_PRT0 80 #define P0_1_PIN 1u 81 #define P0_1_NUM 1u 82 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 83 #define P0_2_PORT GPIO_PRT0 84 #define P0_2_PIN 2u 85 #define P0_2_NUM 2u 86 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 87 #define P0_3_PORT GPIO_PRT0 88 #define P0_3_PIN 3u 89 #define P0_3_NUM 3u 90 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 91 #define P0_4_PORT GPIO_PRT0 92 #define P0_4_PIN 4u 93 #define P0_4_NUM 4u 94 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 95 #define P0_5_PORT GPIO_PRT0 96 #define P0_5_PIN 5u 97 #define P0_5_NUM 5u 98 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 99 100 /* PORT 2 (GPIO) */ 101 #define P2_0_PORT GPIO_PRT2 102 #define P2_0_PIN 0u 103 #define P2_0_NUM 0u 104 #define P2_0_AMUXSEGMENT AMUXBUS_NOISY 105 #define P2_1_PORT GPIO_PRT2 106 #define P2_1_PIN 1u 107 #define P2_1_NUM 1u 108 #define P2_1_AMUXSEGMENT AMUXBUS_NOISY 109 #define P2_2_PORT GPIO_PRT2 110 #define P2_2_PIN 2u 111 #define P2_2_NUM 2u 112 #define P2_2_AMUXSEGMENT AMUXBUS_NOISY 113 #define P2_3_PORT GPIO_PRT2 114 #define P2_3_PIN 3u 115 #define P2_3_NUM 3u 116 #define P2_3_AMUXSEGMENT AMUXBUS_NOISY 117 #define P2_4_PORT GPIO_PRT2 118 #define P2_4_PIN 4u 119 #define P2_4_NUM 4u 120 #define P2_4_AMUXSEGMENT AMUXBUS_NOISY 121 #define P2_5_PORT GPIO_PRT2 122 #define P2_5_PIN 5u 123 #define P2_5_NUM 5u 124 #define P2_5_AMUXSEGMENT AMUXBUS_NOISY 125 #define P2_6_PORT GPIO_PRT2 126 #define P2_6_PIN 6u 127 #define P2_6_NUM 6u 128 #define P2_6_AMUXSEGMENT AMUXBUS_NOISY 129 #define P2_7_PORT GPIO_PRT2 130 #define P2_7_PIN 7u 131 #define P2_7_NUM 7u 132 #define P2_7_AMUXSEGMENT AMUXBUS_NOISY 133 134 /* PORT 3 (GPIO) */ 135 #define P3_0_PORT GPIO_PRT3 136 #define P3_0_PIN 0u 137 #define P3_0_NUM 0u 138 #define P3_0_AMUXSEGMENT AMUXBUS_NOISY 139 #define P3_1_PORT GPIO_PRT3 140 #define P3_1_PIN 1u 141 #define P3_1_NUM 1u 142 #define P3_1_AMUXSEGMENT AMUXBUS_NOISY 143 144 /* PORT 5 (GPIO) */ 145 #define P5_0_PORT GPIO_PRT5 146 #define P5_0_PIN 0u 147 #define P5_0_NUM 0u 148 #define P5_0_AMUXSEGMENT AMUXBUS_CSD0 149 #define P5_1_PORT GPIO_PRT5 150 #define P5_1_PIN 1u 151 #define P5_1_NUM 1u 152 #define P5_1_AMUXSEGMENT AMUXBUS_CSD0 153 #define P5_6_PORT GPIO_PRT5 154 #define P5_6_PIN 6u 155 #define P5_6_NUM 6u 156 #define P5_6_AMUXSEGMENT AMUXBUS_CSD0 157 #define P5_7_PORT GPIO_PRT5 158 #define P5_7_PIN 7u 159 #define P5_7_NUM 7u 160 #define P5_7_AMUXSEGMENT AMUXBUS_CSD0 161 162 /* PORT 6 (GPIO) */ 163 #define P6_2_PORT GPIO_PRT6 164 #define P6_2_PIN 2u 165 #define P6_2_NUM 2u 166 #define P6_2_AMUXSEGMENT AMUXBUS_CSD0 167 #define P6_3_PORT GPIO_PRT6 168 #define P6_3_PIN 3u 169 #define P6_3_NUM 3u 170 #define P6_3_AMUXSEGMENT AMUXBUS_CSD0 171 #define P6_4_PORT GPIO_PRT6 172 #define P6_4_PIN 4u 173 #define P6_4_NUM 4u 174 #define P6_4_AMUXSEGMENT AMUXBUS_CSD0 175 #define P6_5_PORT GPIO_PRT6 176 #define P6_5_PIN 5u 177 #define P6_5_NUM 5u 178 #define P6_5_AMUXSEGMENT AMUXBUS_CSD0 179 #define P6_6_PORT GPIO_PRT6 180 #define P6_6_PIN 6u 181 #define P6_6_NUM 6u 182 #define P6_6_AMUXSEGMENT AMUXBUS_CSD0 183 #define P6_7_PORT GPIO_PRT6 184 #define P6_7_PIN 7u 185 #define P6_7_NUM 7u 186 #define P6_7_AMUXSEGMENT AMUXBUS_CSD0 187 188 /* PORT 7 (GPIO) */ 189 #define P7_0_PORT GPIO_PRT7 190 #define P7_0_PIN 0u 191 #define P7_0_NUM 0u 192 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 193 #define P7_1_PORT GPIO_PRT7 194 #define P7_1_PIN 1u 195 #define P7_1_NUM 1u 196 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 197 #define P7_2_PORT GPIO_PRT7 198 #define P7_2_PIN 2u 199 #define P7_2_NUM 2u 200 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 201 #define P7_3_PORT GPIO_PRT7 202 #define P7_3_PIN 3u 203 #define P7_3_NUM 3u 204 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 205 #define P7_7_PORT GPIO_PRT7 206 #define P7_7_PIN 7u 207 #define P7_7_NUM 7u 208 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 209 210 /* PORT 8 (GPIO) */ 211 #define P8_0_PORT GPIO_PRT8 212 #define P8_0_PIN 0u 213 #define P8_0_NUM 0u 214 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 215 #define P8_1_PORT GPIO_PRT8 216 #define P8_1_PIN 1u 217 #define P8_1_NUM 1u 218 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 219 220 /* PORT 9 (GPIO) */ 221 #define P9_0_PORT GPIO_PRT9 222 #define P9_0_PIN 0u 223 #define P9_0_NUM 0u 224 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 225 #define P9_1_PORT GPIO_PRT9 226 #define P9_1_PIN 1u 227 #define P9_1_NUM 1u 228 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 229 #define P9_2_PORT GPIO_PRT9 230 #define P9_2_PIN 2u 231 #define P9_2_NUM 2u 232 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 233 #define P9_3_PORT GPIO_PRT9 234 #define P9_3_PIN 3u 235 #define P9_3_NUM 3u 236 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 237 238 /* PORT 10 (GPIO) */ 239 #define P10_0_PORT GPIO_PRT10 240 #define P10_0_PIN 0u 241 #define P10_0_NUM 0u 242 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 243 #define P10_1_PORT GPIO_PRT10 244 #define P10_1_PIN 1u 245 #define P10_1_NUM 1u 246 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 247 #define P10_2_PORT GPIO_PRT10 248 #define P10_2_PIN 2u 249 #define P10_2_NUM 2u 250 #define P10_2_AMUXSEGMENT AMUXBUS_SAR 251 #define P10_3_PORT GPIO_PRT10 252 #define P10_3_PIN 3u 253 #define P10_3_NUM 3u 254 #define P10_3_AMUXSEGMENT AMUXBUS_SAR 255 #define P10_4_PORT GPIO_PRT10 256 #define P10_4_PIN 4u 257 #define P10_4_NUM 4u 258 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 259 #define P10_5_PORT GPIO_PRT10 260 #define P10_5_PIN 5u 261 #define P10_5_NUM 5u 262 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 263 264 /* PORT 11 (GPIO) */ 265 #define P11_0_PORT GPIO_PRT11 266 #define P11_0_PIN 0u 267 #define P11_0_NUM 0u 268 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 269 #define P11_1_PORT GPIO_PRT11 270 #define P11_1_PIN 1u 271 #define P11_1_NUM 1u 272 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 273 #define P11_2_PORT GPIO_PRT11 274 #define P11_2_PIN 2u 275 #define P11_2_NUM 2u 276 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 277 #define P11_3_PORT GPIO_PRT11 278 #define P11_3_PIN 3u 279 #define P11_3_NUM 3u 280 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 281 #define P11_4_PORT GPIO_PRT11 282 #define P11_4_PIN 4u 283 #define P11_4_NUM 4u 284 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 285 #define P11_5_PORT GPIO_PRT11 286 #define P11_5_PIN 5u 287 #define P11_5_NUM 5u 288 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 289 #define P11_6_PORT GPIO_PRT11 290 #define P11_6_PIN 6u 291 #define P11_6_NUM 6u 292 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 293 #define P11_7_PORT GPIO_PRT11 294 #define P11_7_PIN 7u 295 #define P11_7_NUM 7u 296 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 297 298 /* PORT 12 (GPIO) */ 299 #define P12_6_PORT GPIO_PRT12 300 #define P12_6_PIN 6u 301 #define P12_6_NUM 6u 302 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 303 #define P12_7_PORT GPIO_PRT12 304 #define P12_7_PIN 7u 305 #define P12_7_NUM 7u 306 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 307 308 /* PORT 14 (AUX) */ 309 #define USBDP_PORT GPIO_PRT14 310 #define USBDP_PIN 0u 311 #define USBDP_NUM 0u 312 #define USBDP_AMUXSEGMENT AMUXBUS_NOISY 313 #define P14_0_PORT GPIO_PRT14 314 #define P14_0_PIN 0u 315 #define P14_0_NUM 0u 316 #define P14_0_AMUXSEGMENT AMUXBUS_NOISY 317 #define USBDM_PORT GPIO_PRT14 318 #define USBDM_PIN 1u 319 #define USBDM_NUM 1u 320 #define USBDM_AMUXSEGMENT AMUXBUS_NOISY 321 #define P14_1_PORT GPIO_PRT14 322 #define P14_1_PIN 1u 323 #define P14_1_NUM 1u 324 #define P14_1_AMUXSEGMENT AMUXBUS_NOISY 325 326 /* Analog Connections */ 327 #define CSD_CMODPADD_PORT 7u 328 #define CSD_CMODPADD_PIN 1u 329 #define CSD_CMODPADS_PORT 7u 330 #define CSD_CMODPADS_PIN 1u 331 #define CSD_CSH_TANKPADD_PORT 7u 332 #define CSD_CSH_TANKPADD_PIN 2u 333 #define CSD_CSH_TANKPADS_PORT 7u 334 #define CSD_CSH_TANKPADS_PIN 2u 335 #define CSD_CSHIELDPADS_PORT 7u 336 #define CSD_CSHIELDPADS_PIN 7u 337 #define CSD_VREF_EXT_PORT 7u 338 #define CSD_VREF_EXT_PIN 3u 339 #define IOSS_ADFT0_NET_PORT 10u 340 #define IOSS_ADFT0_NET_PIN 0u 341 #define IOSS_ADFT1_NET_PORT 10u 342 #define IOSS_ADFT1_NET_PIN 1u 343 #define LPCOMP_INN_COMP0_PORT 5u 344 #define LPCOMP_INN_COMP0_PIN 7u 345 #define LPCOMP_INN_COMP1_PORT 6u 346 #define LPCOMP_INN_COMP1_PIN 3u 347 #define LPCOMP_INP_COMP0_PORT 5u 348 #define LPCOMP_INP_COMP0_PIN 6u 349 #define LPCOMP_INP_COMP1_PORT 6u 350 #define LPCOMP_INP_COMP1_PIN 2u 351 #define PASS_SARMUX_PADS0_PORT 10u 352 #define PASS_SARMUX_PADS0_PIN 0u 353 #define PASS_SARMUX_PADS1_PORT 10u 354 #define PASS_SARMUX_PADS1_PIN 1u 355 #define PASS_SARMUX_PADS2_PORT 10u 356 #define PASS_SARMUX_PADS2_PIN 2u 357 #define PASS_SARMUX_PADS3_PORT 10u 358 #define PASS_SARMUX_PADS3_PIN 3u 359 #define PASS_SARMUX_PADS4_PORT 10u 360 #define PASS_SARMUX_PADS4_PIN 4u 361 #define PASS_SARMUX_PADS5_PORT 10u 362 #define PASS_SARMUX_PADS5_PIN 5u 363 #define SRSS_ADFT_PIN0_PORT 10u 364 #define SRSS_ADFT_PIN0_PIN 0u 365 #define SRSS_ADFT_PIN1_PORT 10u 366 #define SRSS_ADFT_PIN1_PIN 1u 367 #define SRSS_ECO_IN_PORT 12u 368 #define SRSS_ECO_IN_PIN 6u 369 #define SRSS_ECO_OUT_PORT 12u 370 #define SRSS_ECO_OUT_PIN 7u 371 #define SRSS_WCO_IN_PORT 0u 372 #define SRSS_WCO_IN_PIN 0u 373 #define SRSS_WCO_OUT_PORT 0u 374 #define SRSS_WCO_OUT_PIN 1u 375 376 /* HSIOM Connections */ 377 typedef enum 378 { 379 /* Generic HSIOM connections */ 380 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 381 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 382 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 383 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 384 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 385 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 386 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 387 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 388 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 389 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 390 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 391 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 392 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 393 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 394 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 395 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 396 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 397 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 398 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 399 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 400 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 401 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 402 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 403 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 404 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 405 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 406 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 407 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 408 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 409 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 410 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 411 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 412 413 /* P0.0 */ 414 P0_0_GPIO = 0, /* GPIO controls 'out' */ 415 P0_0_AMUXA = 4, /* Analog mux bus A */ 416 P0_0_AMUXB = 5, /* Analog mux bus B */ 417 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 418 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 419 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 420 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 421 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 422 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 423 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 424 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 425 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 426 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 427 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 428 429 /* P0.1 */ 430 P0_1_GPIO = 0, /* GPIO controls 'out' */ 431 P0_1_AMUXA = 4, /* Analog mux bus A */ 432 P0_1_AMUXB = 5, /* Analog mux bus B */ 433 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 434 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 435 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 436 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 437 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 438 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 439 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 440 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 441 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 442 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 443 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 444 445 /* P0.2 */ 446 P0_2_GPIO = 0, /* GPIO controls 'out' */ 447 P0_2_AMUXA = 4, /* Analog mux bus A */ 448 P0_2_AMUXB = 5, /* Analog mux bus B */ 449 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 450 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 451 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 452 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 453 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 454 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 455 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 456 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 457 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 458 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 459 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 460 461 /* P0.3 */ 462 P0_3_GPIO = 0, /* GPIO controls 'out' */ 463 P0_3_AMUXA = 4, /* Analog mux bus A */ 464 P0_3_AMUXB = 5, /* Analog mux bus B */ 465 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 466 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 467 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 468 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 469 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 470 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 471 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 472 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 473 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 474 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 475 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 476 477 /* P0.4 */ 478 P0_4_GPIO = 0, /* GPIO controls 'out' */ 479 P0_4_AMUXA = 4, /* Analog mux bus A */ 480 P0_4_AMUXB = 5, /* Analog mux bus B */ 481 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 482 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 483 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 484 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 485 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 486 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 487 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 488 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 489 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 490 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 491 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 492 493 /* P0.5 */ 494 P0_5_GPIO = 0, /* GPIO controls 'out' */ 495 P0_5_AMUXA = 4, /* Analog mux bus A */ 496 P0_5_AMUXB = 5, /* Analog mux bus B */ 497 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 498 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 499 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 500 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 501 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 502 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 503 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 504 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 505 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 506 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 507 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 508 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 509 510 /* P2.0 */ 511 P2_0_GPIO = 0, /* GPIO controls 'out' */ 512 P2_0_AMUXA = 4, /* Analog mux bus A */ 513 P2_0_AMUXB = 5, /* Analog mux bus B */ 514 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 515 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 516 P2_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:4 */ 517 P2_0_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:1 */ 518 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 519 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 520 P2_0_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 521 P2_0_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 522 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 523 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 524 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 525 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 526 P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ 527 528 /* P2.1 */ 529 P2_1_GPIO = 0, /* GPIO controls 'out' */ 530 P2_1_AMUXA = 4, /* Analog mux bus A */ 531 P2_1_AMUXB = 5, /* Analog mux bus B */ 532 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 533 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 534 P2_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:4 */ 535 P2_1_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:1 */ 536 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 537 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 538 P2_1_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 539 P2_1_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 540 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 541 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 542 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 543 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 544 P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ 545 546 /* P2.2 */ 547 P2_2_GPIO = 0, /* GPIO controls 'out' */ 548 P2_2_AMUXA = 4, /* Analog mux bus A */ 549 P2_2_AMUXB = 5, /* Analog mux bus B */ 550 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 551 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 552 P2_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:4 */ 553 P2_2_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:1 */ 554 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 555 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 556 P2_2_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 557 P2_2_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 558 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 559 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 560 P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ 561 562 /* P2.3 */ 563 P2_3_GPIO = 0, /* GPIO controls 'out' */ 564 P2_3_AMUXA = 4, /* Analog mux bus A */ 565 P2_3_AMUXB = 5, /* Analog mux bus B */ 566 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 567 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 568 P2_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:4 */ 569 P2_3_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:1 */ 570 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 571 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 572 P2_3_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 573 P2_3_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 574 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 575 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 576 P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ 577 578 /* P2.4 */ 579 P2_4_GPIO = 0, /* GPIO controls 'out' */ 580 P2_4_AMUXA = 4, /* Analog mux bus A */ 581 P2_4_AMUXB = 5, /* Analog mux bus B */ 582 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 583 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 584 P2_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 585 P2_4_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:1 */ 586 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 587 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 588 P2_4_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 589 P2_4_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 590 P2_4_SCB9_UART_RX = 18, /* Digital Active - scb[9].uart_rx:0 */ 591 P2_4_SCB9_I2C_SCL = 19, /* Digital Active - scb[9].i2c_scl:0 */ 592 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 593 P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ 594 595 /* P2.5 */ 596 P2_5_GPIO = 0, /* GPIO controls 'out' */ 597 P2_5_AMUXA = 4, /* Analog mux bus A */ 598 P2_5_AMUXB = 5, /* Analog mux bus B */ 599 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 600 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 601 P2_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 602 P2_5_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */ 603 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 604 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 605 P2_5_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 606 P2_5_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 607 P2_5_SCB9_UART_TX = 18, /* Digital Active - scb[9].uart_tx:0 */ 608 P2_5_SCB9_I2C_SDA = 19, /* Digital Active - scb[9].i2c_sda:0 */ 609 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 610 P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ 611 612 /* P2.6 */ 613 P2_6_GPIO = 0, /* GPIO controls 'out' */ 614 P2_6_AMUXA = 4, /* Analog mux bus A */ 615 P2_6_AMUXB = 5, /* Analog mux bus B */ 616 P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 617 P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 618 P2_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 619 P2_6_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:1 */ 620 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 621 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 622 P2_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 623 P2_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 624 P2_6_SCB9_UART_RTS = 18, /* Digital Active - scb[9].uart_rts:0 */ 625 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 626 P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ 627 628 /* P2.7 */ 629 P2_7_GPIO = 0, /* GPIO controls 'out' */ 630 P2_7_AMUXA = 4, /* Analog mux bus A */ 631 P2_7_AMUXB = 5, /* Analog mux bus B */ 632 P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 633 P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 634 P2_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 635 P2_7_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */ 636 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 637 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 638 P2_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 639 P2_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 640 P2_7_SCB9_UART_CTS = 18, /* Digital Active - scb[9].uart_cts:0 */ 641 P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ 642 643 /* P3.0 */ 644 P3_0_GPIO = 0, /* GPIO controls 'out' */ 645 P3_0_AMUXA = 4, /* Analog mux bus A */ 646 P3_0_AMUXB = 5, /* Analog mux bus B */ 647 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 648 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 649 P3_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ 650 P3_0_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:1 */ 651 P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ 652 P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ 653 P3_0_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:0 */ 654 P3_0_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:0 */ 655 P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 656 P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 657 P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ 658 P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 659 P3_0_SDHC0_IO_VOLT_SEL = 26, /* Digital Active - sdhc[0].io_volt_sel */ 660 661 /* P3.1 */ 662 P3_1_GPIO = 0, /* GPIO controls 'out' */ 663 P3_1_AMUXA = 4, /* Analog mux bus A */ 664 P3_1_AMUXB = 5, /* Analog mux bus B */ 665 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 666 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 667 P3_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ 668 P3_1_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:1 */ 669 P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */ 670 P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */ 671 P3_1_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:0 */ 672 P3_1_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:0 */ 673 P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 674 P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 675 P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ 676 P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 677 P3_1_SDHC0_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[0].card_if_pwr_en */ 678 679 /* P5.0 */ 680 P5_0_GPIO = 0, /* GPIO controls 'out' */ 681 P5_0_AMUXA = 4, /* Analog mux bus A */ 682 P5_0_AMUXB = 5, /* Analog mux bus B */ 683 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 684 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 685 P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 686 P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 687 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 688 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 689 P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 690 P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 691 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 692 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 693 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 694 P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */ 695 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 696 697 /* P5.1 */ 698 P5_1_GPIO = 0, /* GPIO controls 'out' */ 699 P5_1_AMUXA = 4, /* Analog mux bus A */ 700 P5_1_AMUXB = 5, /* Analog mux bus B */ 701 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 702 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 703 P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 704 P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 705 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 706 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 707 P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 708 P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 709 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 710 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 711 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 712 P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */ 713 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 714 715 /* P5.6 */ 716 P5_6_GPIO = 0, /* GPIO controls 'out' */ 717 P5_6_AMUXA = 4, /* Analog mux bus A */ 718 P5_6_AMUXB = 5, /* Analog mux bus B */ 719 P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 720 P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 721 P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 722 P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 723 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 724 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 725 P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 726 P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 727 P5_6_SCB10_UART_RTS = 18, /* Digital Active - scb[10].uart_rts:0 */ 728 P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 729 P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */ 730 731 /* P5.7 */ 732 P5_7_GPIO = 0, /* GPIO controls 'out' */ 733 P5_7_AMUXA = 4, /* Analog mux bus A */ 734 P5_7_AMUXB = 5, /* Analog mux bus B */ 735 P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 736 P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 737 P5_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:0 */ 738 P5_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 739 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 740 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 741 P5_7_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 742 P5_7_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 743 P5_7_SCB10_UART_CTS = 18, /* Digital Active - scb[10].uart_cts:0 */ 744 P5_7_SCB3_SPI_SELECT3 = 20, /* Digital Active - scb[3].spi_select3:0 */ 745 746 /* P6.2 */ 747 P6_2_GPIO = 0, /* GPIO controls 'out' */ 748 P6_2_AMUXA = 4, /* Analog mux bus A */ 749 P6_2_AMUXB = 5, /* Analog mux bus B */ 750 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 751 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 752 P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 753 P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ 754 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 755 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 756 P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 757 P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 758 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 759 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 760 P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ 761 762 /* P6.3 */ 763 P6_3_GPIO = 0, /* GPIO controls 'out' */ 764 P6_3_AMUXA = 4, /* Analog mux bus A */ 765 P6_3_AMUXB = 5, /* Analog mux bus B */ 766 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 767 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 768 P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 769 P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 770 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 771 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 772 P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 773 P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 774 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 775 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 776 P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ 777 778 /* P6.4 */ 779 P6_4_GPIO = 0, /* GPIO controls 'out' */ 780 P6_4_AMUXA = 4, /* Analog mux bus A */ 781 P6_4_AMUXB = 5, /* Analog mux bus B */ 782 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 783 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 784 P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 785 P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ 786 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 787 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 788 P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 789 P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 790 P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ 791 P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ 792 P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ 793 P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ 794 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 795 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 796 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 797 P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ 798 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 799 800 /* P6.5 */ 801 P6_5_GPIO = 0, /* GPIO controls 'out' */ 802 P6_5_AMUXA = 4, /* Analog mux bus A */ 803 P6_5_AMUXB = 5, /* Analog mux bus B */ 804 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 805 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 806 P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 807 P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 808 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 809 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 810 P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 811 P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 812 P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ 813 P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ 814 P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ 815 P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ 816 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 817 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 818 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 819 P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ 820 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 821 822 /* P6.6 */ 823 P6_6_GPIO = 0, /* GPIO controls 'out' */ 824 P6_6_AMUXA = 4, /* Analog mux bus A */ 825 P6_6_AMUXB = 5, /* Analog mux bus B */ 826 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 827 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 828 P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 829 P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ 830 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 831 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 832 P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 833 P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 834 P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ 835 P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ 836 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 837 P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ 838 839 /* P6.7 */ 840 P6_7_GPIO = 0, /* GPIO controls 'out' */ 841 P6_7_AMUXA = 4, /* Analog mux bus A */ 842 P6_7_AMUXB = 5, /* Analog mux bus B */ 843 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 844 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 845 P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 846 P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 847 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 848 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 849 P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 850 P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 851 P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ 852 P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ 853 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 854 P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ 855 856 /* P7.0 */ 857 P7_0_GPIO = 0, /* GPIO controls 'out' */ 858 P7_0_AMUXA = 4, /* Analog mux bus A */ 859 P7_0_AMUXB = 5, /* Analog mux bus B */ 860 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 861 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 862 P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 863 P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ 864 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 865 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 866 P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 867 P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 868 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 869 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 870 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 871 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 872 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 873 874 /* P7.1 */ 875 P7_1_GPIO = 0, /* GPIO controls 'out' */ 876 P7_1_AMUXA = 4, /* Analog mux bus A */ 877 P7_1_AMUXB = 5, /* Analog mux bus B */ 878 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 879 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 880 P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 881 P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 882 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 883 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 884 P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 885 P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 886 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 887 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 888 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 889 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 890 891 /* P7.2 */ 892 P7_2_GPIO = 0, /* GPIO controls 'out' */ 893 P7_2_AMUXA = 4, /* Analog mux bus A */ 894 P7_2_AMUXB = 5, /* Analog mux bus B */ 895 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 896 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 897 P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 898 P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ 899 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 900 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 901 P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 902 P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 903 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 904 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 905 906 /* P7.3 */ 907 P7_3_GPIO = 0, /* GPIO controls 'out' */ 908 P7_3_AMUXA = 4, /* Analog mux bus A */ 909 P7_3_AMUXB = 5, /* Analog mux bus B */ 910 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 911 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 912 P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 913 P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 914 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 915 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 916 P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 917 P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 918 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 919 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 920 921 /* P7.7 */ 922 P7_7_GPIO = 0, /* GPIO controls 'out' */ 923 P7_7_AMUXA = 4, /* Analog mux bus A */ 924 P7_7_AMUXB = 5, /* Analog mux bus B */ 925 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 926 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 927 P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 928 P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 929 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 930 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 931 P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 932 P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 933 P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ 934 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 935 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 936 937 /* P8.0 */ 938 P8_0_GPIO = 0, /* GPIO controls 'out' */ 939 P8_0_AMUXA = 4, /* Analog mux bus A */ 940 P8_0_AMUXB = 5, /* Analog mux bus B */ 941 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 942 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 943 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 944 P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ 945 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 946 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 947 P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 948 P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 949 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 950 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 951 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 952 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 953 954 /* P8.1 */ 955 P8_1_GPIO = 0, /* GPIO controls 'out' */ 956 P8_1_AMUXA = 4, /* Analog mux bus A */ 957 P8_1_AMUXB = 5, /* Analog mux bus B */ 958 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 959 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 960 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 961 P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 962 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 963 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 964 P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 965 P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 966 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 967 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 968 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 969 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 970 971 /* P9.0 */ 972 P9_0_GPIO = 0, /* GPIO controls 'out' */ 973 P9_0_AMUXA = 4, /* Analog mux bus A */ 974 P9_0_AMUXB = 5, /* Analog mux bus B */ 975 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 976 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 977 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ 978 P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ 979 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 980 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 981 P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 982 P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 983 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 984 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 985 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 986 P9_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:1 */ 987 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 988 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 989 990 /* P9.1 */ 991 P9_1_GPIO = 0, /* GPIO controls 'out' */ 992 P9_1_AMUXA = 4, /* Analog mux bus A */ 993 P9_1_AMUXB = 5, /* Analog mux bus B */ 994 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 995 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 996 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ 997 P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 998 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 999 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1000 P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 1001 P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 1002 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 1003 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 1004 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 1005 P9_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:1 */ 1006 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 1007 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1008 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1009 1010 /* P9.2 */ 1011 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1012 P9_2_AMUXA = 4, /* Analog mux bus A */ 1013 P9_2_AMUXB = 5, /* Analog mux bus B */ 1014 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1015 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1016 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ 1017 P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ 1018 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ 1019 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ 1020 P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1021 P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1022 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 1023 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 1024 P9_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:1 */ 1025 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1026 1027 /* P9.3 */ 1028 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1029 P9_3_AMUXA = 4, /* Analog mux bus A */ 1030 P9_3_AMUXB = 5, /* Analog mux bus B */ 1031 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1032 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1033 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ 1034 P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 1035 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ 1036 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ 1037 P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1038 P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1039 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1040 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1041 P9_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:1 */ 1042 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1043 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1044 1045 /* P10.0 */ 1046 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1047 P10_0_AMUXA = 4, /* Analog mux bus A */ 1048 P10_0_AMUXB = 5, /* Analog mux bus B */ 1049 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1050 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1051 P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ 1052 P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ 1053 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ 1054 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ 1055 P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ 1056 P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ 1057 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 1058 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 1059 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 1060 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1061 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1062 1063 /* P10.1 */ 1064 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1065 P10_1_AMUXA = 4, /* Analog mux bus A */ 1066 P10_1_AMUXB = 5, /* Analog mux bus B */ 1067 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1068 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1069 P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ 1070 P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 1071 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ 1072 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ 1073 P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ 1074 P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ 1075 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 1076 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 1077 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 1078 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1079 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1080 1081 /* P10.2 */ 1082 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1083 P10_2_AMUXA = 4, /* Analog mux bus A */ 1084 P10_2_AMUXB = 5, /* Analog mux bus B */ 1085 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1086 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1087 P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ 1088 P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ 1089 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ 1090 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ 1091 P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ 1092 P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ 1093 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 1094 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 1095 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1096 1097 /* P10.3 */ 1098 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1099 P10_3_AMUXA = 4, /* Analog mux bus A */ 1100 P10_3_AMUXB = 5, /* Analog mux bus B */ 1101 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1102 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1103 P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ 1104 P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 1105 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ 1106 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ 1107 P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ 1108 P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ 1109 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 1110 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 1111 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1112 1113 /* P10.4 */ 1114 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1115 P10_4_AMUXA = 4, /* Analog mux bus A */ 1116 P10_4_AMUXB = 5, /* Analog mux bus B */ 1117 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1118 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1119 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 1120 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 1121 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ 1122 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ 1123 P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ 1124 P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ 1125 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 1126 P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0 */ 1127 1128 /* P10.5 */ 1129 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1130 P10_5_AMUXA = 4, /* Analog mux bus A */ 1131 P10_5_AMUXB = 5, /* Analog mux bus B */ 1132 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1133 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1134 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 1135 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1136 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ 1137 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ 1138 P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ 1139 P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ 1140 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 1141 P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0 */ 1142 1143 /* P11.0 */ 1144 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1145 P11_0_AMUXA = 4, /* Analog mux bus A */ 1146 P11_0_AMUXB = 5, /* Analog mux bus B */ 1147 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1148 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1149 P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 1150 P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 1151 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ 1152 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ 1153 P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ 1154 P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ 1155 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1156 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 1157 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 1158 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 1159 P11_0_AUDIOSS1_CLK_I2S_IF = 22, /* Digital Active - audioss[1].clk_i2s_if:1 */ 1160 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1161 1162 /* P11.1 */ 1163 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1164 P11_1_AMUXA = 4, /* Analog mux bus A */ 1165 P11_1_AMUXB = 5, /* Analog mux bus B */ 1166 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1167 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1168 P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 1169 P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1170 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ 1171 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ 1172 P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ 1173 P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ 1174 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1175 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 1176 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 1177 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 1178 P11_1_AUDIOSS1_TX_SCK = 22, /* Digital Active - audioss[1].tx_sck:1 */ 1179 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1180 1181 /* P11.2 */ 1182 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1183 P11_2_AMUXA = 4, /* Analog mux bus A */ 1184 P11_2_AMUXB = 5, /* Analog mux bus B */ 1185 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1186 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1187 P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 1188 P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 1189 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ 1190 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ 1191 P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ 1192 P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ 1193 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1194 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ 1195 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ 1196 P11_2_AUDIOSS1_TX_WS = 22, /* Digital Active - audioss[1].tx_ws:1 */ 1197 1198 /* P11.3 */ 1199 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1200 P11_3_AMUXA = 4, /* Analog mux bus A */ 1201 P11_3_AMUXB = 5, /* Analog mux bus B */ 1202 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1203 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1204 P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 1205 P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1206 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ 1207 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ 1208 P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ 1209 P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ 1210 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1211 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ 1212 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ 1213 P11_3_AUDIOSS1_TX_SDO = 22, /* Digital Active - audioss[1].tx_sdo:1 */ 1214 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1215 1216 /* P11.4 */ 1217 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1218 P11_4_AMUXA = 4, /* Analog mux bus A */ 1219 P11_4_AMUXB = 5, /* Analog mux bus B */ 1220 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1221 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1222 P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 1223 P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 1224 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ 1225 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ 1226 P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ 1227 P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ 1228 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1229 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ 1230 P11_4_AUDIOSS1_RX_SCK = 22, /* Digital Active - audioss[1].rx_sck:1 */ 1231 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1232 1233 /* P11.5 */ 1234 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1235 P11_5_AMUXA = 4, /* Analog mux bus A */ 1236 P11_5_AMUXB = 5, /* Analog mux bus B */ 1237 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1238 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1239 P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 1240 P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1241 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ 1242 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ 1243 P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ 1244 P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ 1245 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1246 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ 1247 P11_5_AUDIOSS1_RX_WS = 22, /* Digital Active - audioss[1].rx_ws:1 */ 1248 1249 /* P11.6 */ 1250 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1251 P11_6_AMUXA = 4, /* Analog mux bus A */ 1252 P11_6_AMUXB = 5, /* Analog mux bus B */ 1253 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1254 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1255 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ 1256 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ 1257 P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ 1258 P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ 1259 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1260 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ 1261 P11_6_AUDIOSS1_RX_SDI = 22, /* Digital Active - audioss[1].rx_sdi:1 */ 1262 1263 /* P11.7 */ 1264 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1265 P11_7_AMUXA = 4, /* Analog mux bus A */ 1266 P11_7_AMUXB = 5, /* Analog mux bus B */ 1267 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1268 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1269 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1270 1271 /* P12.6 */ 1272 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1273 P12_6_AMUXA = 4, /* Analog mux bus A */ 1274 P12_6_AMUXB = 5, /* Analog mux bus B */ 1275 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1276 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1277 P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ 1278 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 1279 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ 1280 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ 1281 P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ 1282 P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ 1283 P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 1284 P12_6_SDHC1_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[1].card_if_pwr_en */ 1285 1286 /* P12.7 */ 1287 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1288 P12_7_AMUXA = 4, /* Analog mux bus A */ 1289 P12_7_AMUXB = 5, /* Analog mux bus B */ 1290 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1291 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1292 P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ 1293 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 1294 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ 1295 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ 1296 P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ 1297 P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ 1298 P12_7_SDHC1_IO_VOLT_SEL = 26, /* Digital Active - sdhc[1].io_volt_sel */ 1299 1300 /* USBDP */ 1301 USBDP_GPIO = 0, /* GPIO controls 'out' */ 1302 1303 /* USBDM */ 1304 USBDM_GPIO = 0 /* GPIO controls 'out' */ 1305 } en_hsiom_sel_t; 1306 1307 #endif /* _GPIO_PSOC6_02_68_QFN_H_ */ 1308 1309 1310 /* [] END OF FILE */ 1311
