1 /***************************************************************************//** 2 * \file gpio_psoc6_02_128_tqfp.h 3 * 4 * \brief 5 * PSoC6_02 device GPIO header for 128-TQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_02_128_TQFP_H_ 28 #define _GPIO_PSOC6_02_128_TQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_TQFP 44 #define CY_GPIO_PIN_COUNT 128u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ADFT0_VDDD, 50 AMUXBUS_ANALOG_VDDA, 51 AMUXBUS_ANALOG_VDDD, 52 AMUXBUS_CSD0, 53 AMUXBUS_CSD1, 54 AMUXBUS_MAIN, 55 AMUXBUS_NOISY, 56 AMUXBUS_SAR, 57 AMUXBUS_VDDIO_1, 58 }; 59 60 /* AMUX Splitter Controls */ 61 typedef enum 62 { 63 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ 64 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ 65 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_NOISY; Right = AMUXBUS_CSD0 */ 66 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ 67 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 68 AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 69 AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 70 AMUX_SPLIT_CTL_7 = 0x0007u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ 71 } cy_en_amux_split_t; 72 73 /* Port List */ 74 /* PORT 0 (GPIO) */ 75 #define P0_0_PORT GPIO_PRT0 76 #define P0_0_PIN 0u 77 #define P0_0_NUM 0u 78 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 79 #define P0_1_PORT GPIO_PRT0 80 #define P0_1_PIN 1u 81 #define P0_1_NUM 1u 82 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 83 #define P0_2_PORT GPIO_PRT0 84 #define P0_2_PIN 2u 85 #define P0_2_NUM 2u 86 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 87 #define P0_3_PORT GPIO_PRT0 88 #define P0_3_PIN 3u 89 #define P0_3_NUM 3u 90 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 91 #define P0_4_PORT GPIO_PRT0 92 #define P0_4_PIN 4u 93 #define P0_4_NUM 4u 94 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 95 #define P0_5_PORT GPIO_PRT0 96 #define P0_5_PIN 5u 97 #define P0_5_NUM 5u 98 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 99 100 /* PORT 1 (GPIO_OVT) */ 101 #define P1_0_PORT GPIO_PRT1 102 #define P1_0_PIN 0u 103 #define P1_0_NUM 0u 104 #define P1_0_AMUXSEGMENT AMUXBUS_NOISY 105 #define P1_1_PORT GPIO_PRT1 106 #define P1_1_PIN 1u 107 #define P1_1_NUM 1u 108 #define P1_1_AMUXSEGMENT AMUXBUS_NOISY 109 #define P1_2_PORT GPIO_PRT1 110 #define P1_2_PIN 2u 111 #define P1_2_NUM 2u 112 #define P1_2_AMUXSEGMENT AMUXBUS_NOISY 113 #define P1_3_PORT GPIO_PRT1 114 #define P1_3_PIN 3u 115 #define P1_3_NUM 3u 116 #define P1_3_AMUXSEGMENT AMUXBUS_NOISY 117 #define P1_4_PORT GPIO_PRT1 118 #define P1_4_PIN 4u 119 #define P1_4_NUM 4u 120 #define P1_4_AMUXSEGMENT AMUXBUS_NOISY 121 #define P1_5_PORT GPIO_PRT1 122 #define P1_5_PIN 5u 123 #define P1_5_NUM 5u 124 #define P1_5_AMUXSEGMENT AMUXBUS_NOISY 125 126 /* PORT 2 (GPIO) */ 127 #define P2_0_PORT GPIO_PRT2 128 #define P2_0_PIN 0u 129 #define P2_0_NUM 0u 130 #define P2_0_AMUXSEGMENT AMUXBUS_NOISY 131 #define P2_1_PORT GPIO_PRT2 132 #define P2_1_PIN 1u 133 #define P2_1_NUM 1u 134 #define P2_1_AMUXSEGMENT AMUXBUS_NOISY 135 #define P2_2_PORT GPIO_PRT2 136 #define P2_2_PIN 2u 137 #define P2_2_NUM 2u 138 #define P2_2_AMUXSEGMENT AMUXBUS_NOISY 139 #define P2_3_PORT GPIO_PRT2 140 #define P2_3_PIN 3u 141 #define P2_3_NUM 3u 142 #define P2_3_AMUXSEGMENT AMUXBUS_NOISY 143 #define P2_4_PORT GPIO_PRT2 144 #define P2_4_PIN 4u 145 #define P2_4_NUM 4u 146 #define P2_4_AMUXSEGMENT AMUXBUS_NOISY 147 #define P2_5_PORT GPIO_PRT2 148 #define P2_5_PIN 5u 149 #define P2_5_NUM 5u 150 #define P2_5_AMUXSEGMENT AMUXBUS_NOISY 151 #define P2_6_PORT GPIO_PRT2 152 #define P2_6_PIN 6u 153 #define P2_6_NUM 6u 154 #define P2_6_AMUXSEGMENT AMUXBUS_NOISY 155 #define P2_7_PORT GPIO_PRT2 156 #define P2_7_PIN 7u 157 #define P2_7_NUM 7u 158 #define P2_7_AMUXSEGMENT AMUXBUS_NOISY 159 160 /* PORT 3 (GPIO) */ 161 #define P3_0_PORT GPIO_PRT3 162 #define P3_0_PIN 0u 163 #define P3_0_NUM 0u 164 #define P3_0_AMUXSEGMENT AMUXBUS_NOISY 165 #define P3_1_PORT GPIO_PRT3 166 #define P3_1_PIN 1u 167 #define P3_1_NUM 1u 168 #define P3_1_AMUXSEGMENT AMUXBUS_NOISY 169 #define P3_2_PORT GPIO_PRT3 170 #define P3_2_PIN 2u 171 #define P3_2_NUM 2u 172 #define P3_2_AMUXSEGMENT AMUXBUS_NOISY 173 #define P3_3_PORT GPIO_PRT3 174 #define P3_3_PIN 3u 175 #define P3_3_NUM 3u 176 #define P3_3_AMUXSEGMENT AMUXBUS_NOISY 177 #define P3_4_PORT GPIO_PRT3 178 #define P3_4_PIN 4u 179 #define P3_4_NUM 4u 180 #define P3_4_AMUXSEGMENT AMUXBUS_NOISY 181 #define P3_5_PORT GPIO_PRT3 182 #define P3_5_PIN 5u 183 #define P3_5_NUM 5u 184 #define P3_5_AMUXSEGMENT AMUXBUS_NOISY 185 186 /* PORT 4 (GPIO) */ 187 #define P4_0_PORT GPIO_PRT4 188 #define P4_0_PIN 0u 189 #define P4_0_NUM 0u 190 #define P4_0_AMUXSEGMENT AMUXBUS_NOISY 191 #define P4_1_PORT GPIO_PRT4 192 #define P4_1_PIN 1u 193 #define P4_1_NUM 1u 194 #define P4_1_AMUXSEGMENT AMUXBUS_NOISY 195 #define P4_2_PORT GPIO_PRT4 196 #define P4_2_PIN 2u 197 #define P4_2_NUM 2u 198 #define P4_2_AMUXSEGMENT AMUXBUS_NOISY 199 #define P4_3_PORT GPIO_PRT4 200 #define P4_3_PIN 3u 201 #define P4_3_NUM 3u 202 #define P4_3_AMUXSEGMENT AMUXBUS_NOISY 203 204 /* PORT 5 (GPIO) */ 205 #define P5_0_PORT GPIO_PRT5 206 #define P5_0_PIN 0u 207 #define P5_0_NUM 0u 208 #define P5_0_AMUXSEGMENT AMUXBUS_CSD0 209 #define P5_1_PORT GPIO_PRT5 210 #define P5_1_PIN 1u 211 #define P5_1_NUM 1u 212 #define P5_1_AMUXSEGMENT AMUXBUS_CSD0 213 #define P5_2_PORT GPIO_PRT5 214 #define P5_2_PIN 2u 215 #define P5_2_NUM 2u 216 #define P5_2_AMUXSEGMENT AMUXBUS_CSD0 217 #define P5_3_PORT GPIO_PRT5 218 #define P5_3_PIN 3u 219 #define P5_3_NUM 3u 220 #define P5_3_AMUXSEGMENT AMUXBUS_CSD0 221 #define P5_4_PORT GPIO_PRT5 222 #define P5_4_PIN 4u 223 #define P5_4_NUM 4u 224 #define P5_4_AMUXSEGMENT AMUXBUS_CSD0 225 #define P5_5_PORT GPIO_PRT5 226 #define P5_5_PIN 5u 227 #define P5_5_NUM 5u 228 #define P5_5_AMUXSEGMENT AMUXBUS_CSD0 229 #define P5_6_PORT GPIO_PRT5 230 #define P5_6_PIN 6u 231 #define P5_6_NUM 6u 232 #define P5_6_AMUXSEGMENT AMUXBUS_CSD0 233 #define P5_7_PORT GPIO_PRT5 234 #define P5_7_PIN 7u 235 #define P5_7_NUM 7u 236 #define P5_7_AMUXSEGMENT AMUXBUS_CSD0 237 238 /* PORT 6 (GPIO) */ 239 #define P6_0_PORT GPIO_PRT6 240 #define P6_0_PIN 0u 241 #define P6_0_NUM 0u 242 #define P6_0_AMUXSEGMENT AMUXBUS_CSD0 243 #define P6_1_PORT GPIO_PRT6 244 #define P6_1_PIN 1u 245 #define P6_1_NUM 1u 246 #define P6_1_AMUXSEGMENT AMUXBUS_CSD0 247 #define P6_2_PORT GPIO_PRT6 248 #define P6_2_PIN 2u 249 #define P6_2_NUM 2u 250 #define P6_2_AMUXSEGMENT AMUXBUS_CSD0 251 #define P6_3_PORT GPIO_PRT6 252 #define P6_3_PIN 3u 253 #define P6_3_NUM 3u 254 #define P6_3_AMUXSEGMENT AMUXBUS_CSD0 255 #define P6_4_PORT GPIO_PRT6 256 #define P6_4_PIN 4u 257 #define P6_4_NUM 4u 258 #define P6_4_AMUXSEGMENT AMUXBUS_CSD0 259 #define P6_5_PORT GPIO_PRT6 260 #define P6_5_PIN 5u 261 #define P6_5_NUM 5u 262 #define P6_5_AMUXSEGMENT AMUXBUS_CSD0 263 #define P6_6_PORT GPIO_PRT6 264 #define P6_6_PIN 6u 265 #define P6_6_NUM 6u 266 #define P6_6_AMUXSEGMENT AMUXBUS_CSD0 267 #define P6_7_PORT GPIO_PRT6 268 #define P6_7_PIN 7u 269 #define P6_7_NUM 7u 270 #define P6_7_AMUXSEGMENT AMUXBUS_CSD0 271 272 /* PORT 7 (GPIO) */ 273 #define P7_0_PORT GPIO_PRT7 274 #define P7_0_PIN 0u 275 #define P7_0_NUM 0u 276 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 277 #define P7_1_PORT GPIO_PRT7 278 #define P7_1_PIN 1u 279 #define P7_1_NUM 1u 280 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 281 #define P7_2_PORT GPIO_PRT7 282 #define P7_2_PIN 2u 283 #define P7_2_NUM 2u 284 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 285 #define P7_3_PORT GPIO_PRT7 286 #define P7_3_PIN 3u 287 #define P7_3_NUM 3u 288 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 289 #define P7_4_PORT GPIO_PRT7 290 #define P7_4_PIN 4u 291 #define P7_4_NUM 4u 292 #define P7_4_AMUXSEGMENT AMUXBUS_CSD0 293 #define P7_5_PORT GPIO_PRT7 294 #define P7_5_PIN 5u 295 #define P7_5_NUM 5u 296 #define P7_5_AMUXSEGMENT AMUXBUS_CSD0 297 #define P7_6_PORT GPIO_PRT7 298 #define P7_6_PIN 6u 299 #define P7_6_NUM 6u 300 #define P7_6_AMUXSEGMENT AMUXBUS_CSD0 301 #define P7_7_PORT GPIO_PRT7 302 #define P7_7_PIN 7u 303 #define P7_7_NUM 7u 304 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 305 306 /* PORT 8 (GPIO) */ 307 #define P8_0_PORT GPIO_PRT8 308 #define P8_0_PIN 0u 309 #define P8_0_NUM 0u 310 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 311 #define P8_1_PORT GPIO_PRT8 312 #define P8_1_PIN 1u 313 #define P8_1_NUM 1u 314 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 315 #define P8_2_PORT GPIO_PRT8 316 #define P8_2_PIN 2u 317 #define P8_2_NUM 2u 318 #define P8_2_AMUXSEGMENT AMUXBUS_CSD0 319 #define P8_3_PORT GPIO_PRT8 320 #define P8_3_PIN 3u 321 #define P8_3_NUM 3u 322 #define P8_3_AMUXSEGMENT AMUXBUS_CSD0 323 #define P8_4_PORT GPIO_PRT8 324 #define P8_4_PIN 4u 325 #define P8_4_NUM 4u 326 #define P8_4_AMUXSEGMENT AMUXBUS_CSD0 327 #define P8_5_PORT GPIO_PRT8 328 #define P8_5_PIN 5u 329 #define P8_5_NUM 5u 330 #define P8_5_AMUXSEGMENT AMUXBUS_CSD0 331 #define P8_6_PORT GPIO_PRT8 332 #define P8_6_PIN 6u 333 #define P8_6_NUM 6u 334 #define P8_6_AMUXSEGMENT AMUXBUS_CSD0 335 #define P8_7_PORT GPIO_PRT8 336 #define P8_7_PIN 7u 337 #define P8_7_NUM 7u 338 #define P8_7_AMUXSEGMENT AMUXBUS_CSD0 339 340 /* PORT 9 (GPIO) */ 341 #define P9_0_PORT GPIO_PRT9 342 #define P9_0_PIN 0u 343 #define P9_0_NUM 0u 344 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 345 #define P9_1_PORT GPIO_PRT9 346 #define P9_1_PIN 1u 347 #define P9_1_NUM 1u 348 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 349 #define P9_2_PORT GPIO_PRT9 350 #define P9_2_PIN 2u 351 #define P9_2_NUM 2u 352 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 353 #define P9_3_PORT GPIO_PRT9 354 #define P9_3_PIN 3u 355 #define P9_3_NUM 3u 356 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 357 #define P9_4_PORT GPIO_PRT9 358 #define P9_4_PIN 4u 359 #define P9_4_NUM 4u 360 #define P9_4_AMUXSEGMENT AMUXBUS_SAR 361 #define P9_5_PORT GPIO_PRT9 362 #define P9_5_PIN 5u 363 #define P9_5_NUM 5u 364 #define P9_5_AMUXSEGMENT AMUXBUS_SAR 365 #define P9_6_PORT GPIO_PRT9 366 #define P9_6_PIN 6u 367 #define P9_6_NUM 6u 368 #define P9_6_AMUXSEGMENT AMUXBUS_SAR 369 #define P9_7_PORT GPIO_PRT9 370 #define P9_7_PIN 7u 371 #define P9_7_NUM 7u 372 #define P9_7_AMUXSEGMENT AMUXBUS_SAR 373 374 /* PORT 10 (GPIO) */ 375 #define P10_0_PORT GPIO_PRT10 376 #define P10_0_PIN 0u 377 #define P10_0_NUM 0u 378 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 379 #define P10_1_PORT GPIO_PRT10 380 #define P10_1_PIN 1u 381 #define P10_1_NUM 1u 382 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 383 #define P10_2_PORT GPIO_PRT10 384 #define P10_2_PIN 2u 385 #define P10_2_NUM 2u 386 #define P10_2_AMUXSEGMENT AMUXBUS_SAR 387 #define P10_3_PORT GPIO_PRT10 388 #define P10_3_PIN 3u 389 #define P10_3_NUM 3u 390 #define P10_3_AMUXSEGMENT AMUXBUS_SAR 391 #define P10_4_PORT GPIO_PRT10 392 #define P10_4_PIN 4u 393 #define P10_4_NUM 4u 394 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 395 #define P10_5_PORT GPIO_PRT10 396 #define P10_5_PIN 5u 397 #define P10_5_NUM 5u 398 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 399 #define P10_6_PORT GPIO_PRT10 400 #define P10_6_PIN 6u 401 #define P10_6_NUM 6u 402 #define P10_6_AMUXSEGMENT AMUXBUS_SAR 403 #define P10_7_PORT GPIO_PRT10 404 #define P10_7_PIN 7u 405 #define P10_7_NUM 7u 406 #define P10_7_AMUXSEGMENT AMUXBUS_SAR 407 408 /* PORT 11 (GPIO) */ 409 #define P11_0_PORT GPIO_PRT11 410 #define P11_0_PIN 0u 411 #define P11_0_NUM 0u 412 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 413 #define P11_1_PORT GPIO_PRT11 414 #define P11_1_PIN 1u 415 #define P11_1_NUM 1u 416 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 417 #define P11_2_PORT GPIO_PRT11 418 #define P11_2_PIN 2u 419 #define P11_2_NUM 2u 420 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 421 #define P11_3_PORT GPIO_PRT11 422 #define P11_3_PIN 3u 423 #define P11_3_NUM 3u 424 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 425 #define P11_4_PORT GPIO_PRT11 426 #define P11_4_PIN 4u 427 #define P11_4_NUM 4u 428 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 429 #define P11_5_PORT GPIO_PRT11 430 #define P11_5_PIN 5u 431 #define P11_5_NUM 5u 432 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 433 #define P11_6_PORT GPIO_PRT11 434 #define P11_6_PIN 6u 435 #define P11_6_NUM 6u 436 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 437 #define P11_7_PORT GPIO_PRT11 438 #define P11_7_PIN 7u 439 #define P11_7_NUM 7u 440 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 441 442 /* PORT 12 (GPIO) */ 443 #define P12_0_PORT GPIO_PRT12 444 #define P12_0_PIN 0u 445 #define P12_0_NUM 0u 446 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 447 #define P12_1_PORT GPIO_PRT12 448 #define P12_1_PIN 1u 449 #define P12_1_NUM 1u 450 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 451 #define P12_2_PORT GPIO_PRT12 452 #define P12_2_PIN 2u 453 #define P12_2_NUM 2u 454 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 455 #define P12_3_PORT GPIO_PRT12 456 #define P12_3_PIN 3u 457 #define P12_3_NUM 3u 458 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 459 #define P12_4_PORT GPIO_PRT12 460 #define P12_4_PIN 4u 461 #define P12_4_NUM 4u 462 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 463 #define P12_5_PORT GPIO_PRT12 464 #define P12_5_PIN 5u 465 #define P12_5_NUM 5u 466 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 467 #define P12_6_PORT GPIO_PRT12 468 #define P12_6_PIN 6u 469 #define P12_6_NUM 6u 470 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 471 #define P12_7_PORT GPIO_PRT12 472 #define P12_7_PIN 7u 473 #define P12_7_NUM 7u 474 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 475 476 /* PORT 13 (GPIO) */ 477 #define P13_0_PORT GPIO_PRT13 478 #define P13_0_PIN 0u 479 #define P13_0_NUM 0u 480 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 481 #define P13_1_PORT GPIO_PRT13 482 #define P13_1_PIN 1u 483 #define P13_1_NUM 1u 484 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 485 #define P13_2_PORT GPIO_PRT13 486 #define P13_2_PIN 2u 487 #define P13_2_NUM 2u 488 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 489 #define P13_3_PORT GPIO_PRT13 490 #define P13_3_PIN 3u 491 #define P13_3_NUM 3u 492 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 493 #define P13_4_PORT GPIO_PRT13 494 #define P13_4_PIN 4u 495 #define P13_4_NUM 4u 496 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 497 #define P13_5_PORT GPIO_PRT13 498 #define P13_5_PIN 5u 499 #define P13_5_NUM 5u 500 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 501 #define P13_6_PORT GPIO_PRT13 502 #define P13_6_PIN 6u 503 #define P13_6_NUM 6u 504 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 505 #define P13_7_PORT GPIO_PRT13 506 #define P13_7_PIN 7u 507 #define P13_7_NUM 7u 508 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 509 510 /* PORT 14 (AUX) */ 511 #define USBDP_PORT GPIO_PRT14 512 #define USBDP_PIN 0u 513 #define USBDP_NUM 0u 514 #define USBDP_AMUXSEGMENT AMUXBUS_NOISY 515 #define P14_0_PORT GPIO_PRT14 516 #define P14_0_PIN 0u 517 #define P14_0_NUM 0u 518 #define P14_0_AMUXSEGMENT AMUXBUS_NOISY 519 #define USBDM_PORT GPIO_PRT14 520 #define USBDM_PIN 1u 521 #define USBDM_NUM 1u 522 #define USBDM_AMUXSEGMENT AMUXBUS_NOISY 523 #define P14_1_PORT GPIO_PRT14 524 #define P14_1_PIN 1u 525 #define P14_1_NUM 1u 526 #define P14_1_AMUXSEGMENT AMUXBUS_NOISY 527 528 /* Analog Connections */ 529 #define CSD_CMODPADD_PORT 7u 530 #define CSD_CMODPADD_PIN 1u 531 #define CSD_CMODPADS_PORT 7u 532 #define CSD_CMODPADS_PIN 1u 533 #define CSD_CSH_TANKPADD_PORT 7u 534 #define CSD_CSH_TANKPADD_PIN 2u 535 #define CSD_CSH_TANKPADS_PORT 7u 536 #define CSD_CSH_TANKPADS_PIN 2u 537 #define CSD_CSHIELDPADS_PORT 7u 538 #define CSD_CSHIELDPADS_PIN 7u 539 #define CSD_VREF_EXT_PORT 7u 540 #define CSD_VREF_EXT_PIN 3u 541 #define IOSS_ADFT0_NET_PORT 10u 542 #define IOSS_ADFT0_NET_PIN 0u 543 #define IOSS_ADFT1_NET_PORT 10u 544 #define IOSS_ADFT1_NET_PIN 1u 545 #define LPCOMP_INN_COMP0_PORT 5u 546 #define LPCOMP_INN_COMP0_PIN 7u 547 #define LPCOMP_INN_COMP1_PORT 6u 548 #define LPCOMP_INN_COMP1_PIN 3u 549 #define LPCOMP_INP_COMP0_PORT 5u 550 #define LPCOMP_INP_COMP0_PIN 6u 551 #define LPCOMP_INP_COMP1_PORT 6u 552 #define LPCOMP_INP_COMP1_PIN 2u 553 #define PASS_AREF_EXT_VREF_PORT 9u 554 #define PASS_AREF_EXT_VREF_PIN 7u 555 #define PASS_SARMUX_PADS0_PORT 10u 556 #define PASS_SARMUX_PADS0_PIN 0u 557 #define PASS_SARMUX_PADS1_PORT 10u 558 #define PASS_SARMUX_PADS1_PIN 1u 559 #define PASS_SARMUX_PADS2_PORT 10u 560 #define PASS_SARMUX_PADS2_PIN 2u 561 #define PASS_SARMUX_PADS3_PORT 10u 562 #define PASS_SARMUX_PADS3_PIN 3u 563 #define PASS_SARMUX_PADS4_PORT 10u 564 #define PASS_SARMUX_PADS4_PIN 4u 565 #define PASS_SARMUX_PADS5_PORT 10u 566 #define PASS_SARMUX_PADS5_PIN 5u 567 #define PASS_SARMUX_PADS6_PORT 10u 568 #define PASS_SARMUX_PADS6_PIN 6u 569 #define PASS_SARMUX_PADS7_PORT 10u 570 #define PASS_SARMUX_PADS7_PIN 7u 571 #define SRSS_ADFT_PIN0_PORT 10u 572 #define SRSS_ADFT_PIN0_PIN 0u 573 #define SRSS_ADFT_PIN1_PORT 10u 574 #define SRSS_ADFT_PIN1_PIN 1u 575 #define SRSS_ECO_IN_PORT 12u 576 #define SRSS_ECO_IN_PIN 6u 577 #define SRSS_ECO_OUT_PORT 12u 578 #define SRSS_ECO_OUT_PIN 7u 579 #define SRSS_WCO_IN_PORT 0u 580 #define SRSS_WCO_IN_PIN 0u 581 #define SRSS_WCO_OUT_PORT 0u 582 #define SRSS_WCO_OUT_PIN 1u 583 584 /* HSIOM Connections */ 585 typedef enum 586 { 587 /* Generic HSIOM connections */ 588 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 589 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 590 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 591 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 592 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 593 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 594 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 595 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 596 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 597 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 598 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 599 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 600 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 601 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 602 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 603 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 604 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 605 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 606 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 607 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 608 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 609 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 610 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 611 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 612 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 613 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 614 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 615 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 616 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 617 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 618 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 619 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 620 621 /* P0.0 */ 622 P0_0_GPIO = 0, /* GPIO controls 'out' */ 623 P0_0_AMUXA = 4, /* Analog mux bus A */ 624 P0_0_AMUXB = 5, /* Analog mux bus B */ 625 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 626 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 627 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 628 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 629 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 630 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 631 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 632 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 633 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 634 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 635 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 636 637 /* P0.1 */ 638 P0_1_GPIO = 0, /* GPIO controls 'out' */ 639 P0_1_AMUXA = 4, /* Analog mux bus A */ 640 P0_1_AMUXB = 5, /* Analog mux bus B */ 641 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 642 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 643 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 644 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 645 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 646 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 647 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 648 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 649 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 650 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 651 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 652 653 /* P0.2 */ 654 P0_2_GPIO = 0, /* GPIO controls 'out' */ 655 P0_2_AMUXA = 4, /* Analog mux bus A */ 656 P0_2_AMUXB = 5, /* Analog mux bus B */ 657 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 658 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 659 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 660 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 661 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 662 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 663 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 664 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 665 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 666 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 667 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 668 669 /* P0.3 */ 670 P0_3_GPIO = 0, /* GPIO controls 'out' */ 671 P0_3_AMUXA = 4, /* Analog mux bus A */ 672 P0_3_AMUXB = 5, /* Analog mux bus B */ 673 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 674 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 675 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 676 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 677 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 678 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 679 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 680 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 681 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 682 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 683 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 684 685 /* P0.4 */ 686 P0_4_GPIO = 0, /* GPIO controls 'out' */ 687 P0_4_AMUXA = 4, /* Analog mux bus A */ 688 P0_4_AMUXB = 5, /* Analog mux bus B */ 689 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 690 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 691 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 692 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 693 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 694 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 695 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 696 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 697 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 698 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 699 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 700 701 /* P0.5 */ 702 P0_5_GPIO = 0, /* GPIO controls 'out' */ 703 P0_5_AMUXA = 4, /* Analog mux bus A */ 704 P0_5_AMUXB = 5, /* Analog mux bus B */ 705 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 706 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 707 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 708 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 709 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 710 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 711 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 712 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 713 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 714 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 715 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 716 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 717 718 /* P1.0 */ 719 P1_0_GPIO = 0, /* GPIO controls 'out' */ 720 P1_0_AMUXA = 4, /* Analog mux bus A */ 721 P1_0_AMUXB = 5, /* Analog mux bus B */ 722 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 723 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 724 P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 725 P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 726 P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 727 P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 728 P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 729 P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 730 P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ 731 P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ 732 P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ 733 P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 734 735 /* P1.1 */ 736 P1_1_GPIO = 0, /* GPIO controls 'out' */ 737 P1_1_AMUXA = 4, /* Analog mux bus A */ 738 P1_1_AMUXB = 5, /* Analog mux bus B */ 739 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 740 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 741 P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 742 P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 743 P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 744 P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 745 P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 746 P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 747 P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ 748 P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ 749 P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ 750 P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 751 752 /* P1.2 */ 753 P1_2_GPIO = 0, /* GPIO controls 'out' */ 754 P1_2_AMUXA = 4, /* Analog mux bus A */ 755 P1_2_AMUXB = 5, /* Analog mux bus B */ 756 P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 757 P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 758 P1_2_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:4 */ 759 P1_2_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:1 */ 760 P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ 761 P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ 762 P1_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 763 P1_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 764 P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */ 765 P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */ 766 767 /* P1.3 */ 768 P1_3_GPIO = 0, /* GPIO controls 'out' */ 769 P1_3_AMUXA = 4, /* Analog mux bus A */ 770 P1_3_AMUXB = 5, /* Analog mux bus B */ 771 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 772 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 773 P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */ 774 P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ 775 P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 776 P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 777 P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 778 P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 779 P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */ 780 P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */ 781 782 /* P1.4 */ 783 P1_4_GPIO = 0, /* GPIO controls 'out' */ 784 P1_4_AMUXA = 4, /* Analog mux bus A */ 785 P1_4_AMUXB = 5, /* Analog mux bus B */ 786 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 787 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 788 P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ 789 P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ 790 P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 791 P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 792 P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 793 P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 794 P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ 795 796 /* P1.5 */ 797 P1_5_GPIO = 0, /* GPIO controls 'out' */ 798 P1_5_AMUXA = 4, /* Analog mux bus A */ 799 P1_5_AMUXB = 5, /* Analog mux bus B */ 800 P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 801 P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 802 P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ 803 P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 804 P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 805 P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 806 P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 807 P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 808 P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ 809 810 /* P2.0 */ 811 P2_0_GPIO = 0, /* GPIO controls 'out' */ 812 P2_0_AMUXA = 4, /* Analog mux bus A */ 813 P2_0_AMUXB = 5, /* Analog mux bus B */ 814 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 815 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 816 P2_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:4 */ 817 P2_0_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:1 */ 818 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 819 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 820 P2_0_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 821 P2_0_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 822 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 823 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 824 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 825 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 826 P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ 827 828 /* P2.1 */ 829 P2_1_GPIO = 0, /* GPIO controls 'out' */ 830 P2_1_AMUXA = 4, /* Analog mux bus A */ 831 P2_1_AMUXB = 5, /* Analog mux bus B */ 832 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 833 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 834 P2_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:4 */ 835 P2_1_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:1 */ 836 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 837 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 838 P2_1_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 839 P2_1_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 840 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 841 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 842 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 843 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 844 P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ 845 846 /* P2.2 */ 847 P2_2_GPIO = 0, /* GPIO controls 'out' */ 848 P2_2_AMUXA = 4, /* Analog mux bus A */ 849 P2_2_AMUXB = 5, /* Analog mux bus B */ 850 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 851 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 852 P2_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:4 */ 853 P2_2_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:1 */ 854 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 855 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 856 P2_2_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 857 P2_2_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 858 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 859 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 860 P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ 861 862 /* P2.3 */ 863 P2_3_GPIO = 0, /* GPIO controls 'out' */ 864 P2_3_AMUXA = 4, /* Analog mux bus A */ 865 P2_3_AMUXB = 5, /* Analog mux bus B */ 866 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 867 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 868 P2_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:4 */ 869 P2_3_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:1 */ 870 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 871 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 872 P2_3_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 873 P2_3_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 874 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 875 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 876 P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ 877 878 /* P2.4 */ 879 P2_4_GPIO = 0, /* GPIO controls 'out' */ 880 P2_4_AMUXA = 4, /* Analog mux bus A */ 881 P2_4_AMUXB = 5, /* Analog mux bus B */ 882 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 883 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 884 P2_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 885 P2_4_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:1 */ 886 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 887 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 888 P2_4_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 889 P2_4_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 890 P2_4_SCB9_UART_RX = 18, /* Digital Active - scb[9].uart_rx:0 */ 891 P2_4_SCB9_I2C_SCL = 19, /* Digital Active - scb[9].i2c_scl:0 */ 892 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 893 P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ 894 895 /* P2.5 */ 896 P2_5_GPIO = 0, /* GPIO controls 'out' */ 897 P2_5_AMUXA = 4, /* Analog mux bus A */ 898 P2_5_AMUXB = 5, /* Analog mux bus B */ 899 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 900 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 901 P2_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 902 P2_5_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */ 903 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 904 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 905 P2_5_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 906 P2_5_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 907 P2_5_SCB9_UART_TX = 18, /* Digital Active - scb[9].uart_tx:0 */ 908 P2_5_SCB9_I2C_SDA = 19, /* Digital Active - scb[9].i2c_sda:0 */ 909 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 910 P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ 911 912 /* P2.6 */ 913 P2_6_GPIO = 0, /* GPIO controls 'out' */ 914 P2_6_AMUXA = 4, /* Analog mux bus A */ 915 P2_6_AMUXB = 5, /* Analog mux bus B */ 916 P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 917 P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 918 P2_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 919 P2_6_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:1 */ 920 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 921 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 922 P2_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 923 P2_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 924 P2_6_SCB9_UART_RTS = 18, /* Digital Active - scb[9].uart_rts:0 */ 925 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 926 P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ 927 928 /* P2.7 */ 929 P2_7_GPIO = 0, /* GPIO controls 'out' */ 930 P2_7_AMUXA = 4, /* Analog mux bus A */ 931 P2_7_AMUXB = 5, /* Analog mux bus B */ 932 P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 933 P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 934 P2_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 935 P2_7_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */ 936 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 937 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 938 P2_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 939 P2_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 940 P2_7_SCB9_UART_CTS = 18, /* Digital Active - scb[9].uart_cts:0 */ 941 P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ 942 943 /* P3.0 */ 944 P3_0_GPIO = 0, /* GPIO controls 'out' */ 945 P3_0_AMUXA = 4, /* Analog mux bus A */ 946 P3_0_AMUXB = 5, /* Analog mux bus B */ 947 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 948 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 949 P3_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ 950 P3_0_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:1 */ 951 P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ 952 P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ 953 P3_0_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:0 */ 954 P3_0_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:0 */ 955 P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 956 P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 957 P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ 958 P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 959 P3_0_SDHC0_IO_VOLT_SEL = 26, /* Digital Active - sdhc[0].io_volt_sel */ 960 961 /* P3.1 */ 962 P3_1_GPIO = 0, /* GPIO controls 'out' */ 963 P3_1_AMUXA = 4, /* Analog mux bus A */ 964 P3_1_AMUXB = 5, /* Analog mux bus B */ 965 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 966 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 967 P3_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ 968 P3_1_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:1 */ 969 P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */ 970 P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */ 971 P3_1_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:0 */ 972 P3_1_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:0 */ 973 P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 974 P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 975 P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ 976 P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 977 P3_1_SDHC0_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[0].card_if_pwr_en */ 978 979 /* P3.2 */ 980 P3_2_GPIO = 0, /* GPIO controls 'out' */ 981 P3_2_AMUXA = 4, /* Analog mux bus A */ 982 P3_2_AMUXB = 5, /* Analog mux bus B */ 983 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 984 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 985 P3_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ 986 P3_2_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:1 */ 987 P3_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ 988 P3_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ 989 P3_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ 990 P3_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ 991 P3_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:1 */ 992 P3_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:1 */ 993 994 /* P3.3 */ 995 P3_3_GPIO = 0, /* GPIO controls 'out' */ 996 P3_3_AMUXA = 4, /* Analog mux bus A */ 997 P3_3_AMUXB = 5, /* Analog mux bus B */ 998 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 999 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1000 P3_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ 1001 P3_3_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:1 */ 1002 P3_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ 1003 P3_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ 1004 P3_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ 1005 P3_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ 1006 P3_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:1 */ 1007 P3_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:1 */ 1008 1009 /* P3.4 */ 1010 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1011 P3_4_AMUXA = 4, /* Analog mux bus A */ 1012 P3_4_AMUXB = 5, /* Analog mux bus B */ 1013 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1014 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1015 P3_4_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:5 */ 1016 P3_4_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:1 */ 1017 P3_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ 1018 P3_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ 1019 P3_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ 1020 P3_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ 1021 P3_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:1 */ 1022 1023 /* P3.5 */ 1024 P3_5_GPIO = 0, /* GPIO controls 'out' */ 1025 P3_5_AMUXA = 4, /* Analog mux bus A */ 1026 P3_5_AMUXB = 5, /* Analog mux bus B */ 1027 P3_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1028 P3_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1029 P3_5_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:5 */ 1030 P3_5_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:1 */ 1031 P3_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ 1032 P3_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ 1033 P3_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ 1034 P3_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ 1035 P3_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:1 */ 1036 1037 /* P4.0 */ 1038 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1039 P4_0_AMUXA = 4, /* Analog mux bus A */ 1040 P4_0_AMUXB = 5, /* Analog mux bus B */ 1041 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1042 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1043 P4_0_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:5 */ 1044 P4_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:1 */ 1045 P4_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ 1046 P4_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ 1047 P4_0_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ 1048 P4_0_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ 1049 P4_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:1 */ 1050 P4_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:1 */ 1051 P4_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:1 */ 1052 P4_0_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 1053 1054 /* P4.1 */ 1055 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1056 P4_1_AMUXA = 4, /* Analog mux bus A */ 1057 P4_1_AMUXB = 5, /* Analog mux bus B */ 1058 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1059 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1060 P4_1_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:5 */ 1061 P4_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:1 */ 1062 P4_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ 1063 P4_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ 1064 P4_1_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ 1065 P4_1_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ 1066 P4_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:1 */ 1067 P4_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:1 */ 1068 P4_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:1 */ 1069 P4_1_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 1070 1071 /* P4.2 */ 1072 P4_2_GPIO = 0, /* GPIO controls 'out' */ 1073 P4_2_AMUXA = 4, /* Analog mux bus A */ 1074 P4_2_AMUXB = 5, /* Analog mux bus B */ 1075 P4_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1076 P4_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1077 P4_2_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:5 */ 1078 P4_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:1 */ 1079 P4_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ 1080 P4_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ 1081 P4_2_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ 1082 P4_2_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ 1083 P4_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:1 */ 1084 P4_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:1 */ 1085 1086 /* P4.3 */ 1087 P4_3_GPIO = 0, /* GPIO controls 'out' */ 1088 P4_3_AMUXA = 4, /* Analog mux bus A */ 1089 P4_3_AMUXB = 5, /* Analog mux bus B */ 1090 P4_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1091 P4_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1092 P4_3_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:5 */ 1093 P4_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:1 */ 1094 P4_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ 1095 P4_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ 1096 P4_3_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ 1097 P4_3_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ 1098 P4_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:1 */ 1099 P4_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:1 */ 1100 1101 /* P5.0 */ 1102 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1103 P5_0_AMUXA = 4, /* Analog mux bus A */ 1104 P5_0_AMUXB = 5, /* Analog mux bus B */ 1105 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1106 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1107 P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 1108 P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 1109 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 1110 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 1111 P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 1112 P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 1113 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 1114 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 1115 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 1116 P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */ 1117 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 1118 1119 /* P5.1 */ 1120 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1121 P5_1_AMUXA = 4, /* Analog mux bus A */ 1122 P5_1_AMUXB = 5, /* Analog mux bus B */ 1123 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1124 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1125 P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 1126 P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 1127 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 1128 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 1129 P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 1130 P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 1131 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 1132 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 1133 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 1134 P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */ 1135 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 1136 1137 /* P5.2 */ 1138 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1139 P5_2_AMUXA = 4, /* Analog mux bus A */ 1140 P5_2_AMUXB = 5, /* Analog mux bus B */ 1141 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1142 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1143 P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 1144 P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 1145 P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 1146 P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 1147 P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 1148 P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 1149 P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 1150 P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 1151 P5_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:0 */ 1152 1153 /* P5.3 */ 1154 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1155 P5_3_AMUXA = 4, /* Analog mux bus A */ 1156 P5_3_AMUXB = 5, /* Analog mux bus B */ 1157 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1158 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1159 P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ 1160 P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 1161 P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 1162 P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 1163 P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ 1164 P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ 1165 P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 1166 P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 1167 P5_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:0 */ 1168 1169 /* P5.4 */ 1170 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1171 P5_4_AMUXA = 4, /* Analog mux bus A */ 1172 P5_4_AMUXB = 5, /* Analog mux bus B */ 1173 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1174 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1175 P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ 1176 P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 1177 P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ 1178 P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ 1179 P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ 1180 P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ 1181 P5_4_SCB10_UART_RX = 18, /* Digital Active - scb[10].uart_rx:0 */ 1182 P5_4_SCB10_I2C_SCL = 19, /* Digital Active - scb[10].i2c_scl:0 */ 1183 P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 1184 P5_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:0 */ 1185 1186 /* P5.5 */ 1187 P5_5_GPIO = 0, /* GPIO controls 'out' */ 1188 P5_5_AMUXA = 4, /* Analog mux bus A */ 1189 P5_5_AMUXB = 5, /* Analog mux bus B */ 1190 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1191 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1192 P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ 1193 P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 1194 P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 1195 P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 1196 P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 1197 P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 1198 P5_5_SCB10_UART_TX = 18, /* Digital Active - scb[10].uart_tx:0 */ 1199 P5_5_SCB10_I2C_SDA = 19, /* Digital Active - scb[10].i2c_sda:0 */ 1200 P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 1201 P5_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:0 */ 1202 1203 /* P5.6 */ 1204 P5_6_GPIO = 0, /* GPIO controls 'out' */ 1205 P5_6_AMUXA = 4, /* Analog mux bus A */ 1206 P5_6_AMUXB = 5, /* Analog mux bus B */ 1207 P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1208 P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1209 P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 1210 P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 1211 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 1212 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 1213 P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 1214 P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 1215 P5_6_SCB10_UART_RTS = 18, /* Digital Active - scb[10].uart_rts:0 */ 1216 P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 1217 P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */ 1218 1219 /* P5.7 */ 1220 P5_7_GPIO = 0, /* GPIO controls 'out' */ 1221 P5_7_AMUXA = 4, /* Analog mux bus A */ 1222 P5_7_AMUXB = 5, /* Analog mux bus B */ 1223 P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1224 P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1225 P5_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:0 */ 1226 P5_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 1227 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 1228 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 1229 P5_7_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 1230 P5_7_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 1231 P5_7_SCB10_UART_CTS = 18, /* Digital Active - scb[10].uart_cts:0 */ 1232 P5_7_SCB3_SPI_SELECT3 = 20, /* Digital Active - scb[3].spi_select3:0 */ 1233 1234 /* P6.0 */ 1235 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1236 P6_0_AMUXA = 4, /* Analog mux bus A */ 1237 P6_0_AMUXB = 5, /* Analog mux bus B */ 1238 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1239 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1240 P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 1241 P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ 1242 P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 1243 P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 1244 P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ 1245 P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ 1246 P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ 1247 P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 1248 P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 1249 P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ 1250 P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 1251 P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ 1252 1253 /* P6.1 */ 1254 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1255 P6_1_AMUXA = 4, /* Analog mux bus A */ 1256 P6_1_AMUXB = 5, /* Analog mux bus B */ 1257 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1258 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1259 P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 1260 P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 1261 P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 1262 P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 1263 P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ 1264 P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ 1265 P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ 1266 P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 1267 P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 1268 P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ 1269 P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 1270 P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ 1271 1272 /* P6.2 */ 1273 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1274 P6_2_AMUXA = 4, /* Analog mux bus A */ 1275 P6_2_AMUXB = 5, /* Analog mux bus B */ 1276 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1277 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1278 P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 1279 P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ 1280 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 1281 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 1282 P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 1283 P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 1284 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 1285 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 1286 P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ 1287 1288 /* P6.3 */ 1289 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1290 P6_3_AMUXA = 4, /* Analog mux bus A */ 1291 P6_3_AMUXB = 5, /* Analog mux bus B */ 1292 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1293 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1294 P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 1295 P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 1296 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 1297 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 1298 P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 1299 P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 1300 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 1301 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 1302 P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ 1303 1304 /* P6.4 */ 1305 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1306 P6_4_AMUXA = 4, /* Analog mux bus A */ 1307 P6_4_AMUXB = 5, /* Analog mux bus B */ 1308 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1309 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1310 P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 1311 P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ 1312 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 1313 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 1314 P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 1315 P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 1316 P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ 1317 P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ 1318 P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ 1319 P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ 1320 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 1321 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 1322 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 1323 P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ 1324 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 1325 1326 /* P6.5 */ 1327 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1328 P6_5_AMUXA = 4, /* Analog mux bus A */ 1329 P6_5_AMUXB = 5, /* Analog mux bus B */ 1330 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1331 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1332 P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 1333 P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 1334 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 1335 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 1336 P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 1337 P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 1338 P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ 1339 P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ 1340 P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ 1341 P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ 1342 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 1343 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 1344 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 1345 P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ 1346 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1347 1348 /* P6.6 */ 1349 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1350 P6_6_AMUXA = 4, /* Analog mux bus A */ 1351 P6_6_AMUXB = 5, /* Analog mux bus B */ 1352 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1353 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1354 P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 1355 P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ 1356 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 1357 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 1358 P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 1359 P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 1360 P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ 1361 P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ 1362 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 1363 P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ 1364 1365 /* P6.7 */ 1366 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1367 P6_7_AMUXA = 4, /* Analog mux bus A */ 1368 P6_7_AMUXB = 5, /* Analog mux bus B */ 1369 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1370 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1371 P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 1372 P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 1373 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 1374 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 1375 P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 1376 P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 1377 P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ 1378 P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ 1379 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 1380 P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ 1381 1382 /* P7.0 */ 1383 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1384 P7_0_AMUXA = 4, /* Analog mux bus A */ 1385 P7_0_AMUXB = 5, /* Analog mux bus B */ 1386 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1387 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1388 P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 1389 P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ 1390 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 1391 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 1392 P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 1393 P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 1394 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 1395 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 1396 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 1397 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 1398 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 1399 1400 /* P7.1 */ 1401 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1402 P7_1_AMUXA = 4, /* Analog mux bus A */ 1403 P7_1_AMUXB = 5, /* Analog mux bus B */ 1404 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1405 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1406 P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 1407 P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1408 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1409 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1410 P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1411 P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1412 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 1413 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 1414 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 1415 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 1416 1417 /* P7.2 */ 1418 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1419 P7_2_AMUXA = 4, /* Analog mux bus A */ 1420 P7_2_AMUXB = 5, /* Analog mux bus B */ 1421 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1422 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1423 P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 1424 P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ 1425 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1426 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1427 P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1428 P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1429 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 1430 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 1431 1432 /* P7.3 */ 1433 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1434 P7_3_AMUXA = 4, /* Analog mux bus A */ 1435 P7_3_AMUXB = 5, /* Analog mux bus B */ 1436 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1437 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1438 P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 1439 P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1440 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1441 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1442 P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1443 P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1444 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 1445 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 1446 1447 /* P7.4 */ 1448 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1449 P7_4_AMUXA = 4, /* Analog mux bus A */ 1450 P7_4_AMUXB = 5, /* Analog mux bus B */ 1451 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1452 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1453 P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 1454 P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ 1455 P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ 1456 P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ 1457 P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ 1458 P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ 1459 P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ 1460 P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 1461 1462 /* P7.5 */ 1463 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1464 P7_5_AMUXA = 4, /* Analog mux bus A */ 1465 P7_5_AMUXB = 5, /* Analog mux bus B */ 1466 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1467 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1468 P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 1469 P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ 1470 P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ 1471 P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ 1472 P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ 1473 P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ 1474 P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ 1475 P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ 1476 1477 /* P7.6 */ 1478 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1479 P7_6_AMUXA = 4, /* Analog mux bus A */ 1480 P7_6_AMUXB = 5, /* Analog mux bus B */ 1481 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1482 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1483 P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 1484 P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ 1485 P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 1486 P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 1487 P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ 1488 P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ 1489 P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ 1490 P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ 1491 1492 /* P7.7 */ 1493 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1494 P7_7_AMUXA = 4, /* Analog mux bus A */ 1495 P7_7_AMUXB = 5, /* Analog mux bus B */ 1496 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1497 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1498 P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 1499 P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 1500 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1501 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1502 P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1503 P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1504 P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ 1505 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 1506 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 1507 1508 /* P8.0 */ 1509 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1510 P8_0_AMUXA = 4, /* Analog mux bus A */ 1511 P8_0_AMUXB = 5, /* Analog mux bus B */ 1512 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1513 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1514 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 1515 P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ 1516 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1517 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1518 P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1519 P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1520 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 1521 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 1522 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 1523 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 1524 1525 /* P8.1 */ 1526 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1527 P8_1_AMUXA = 4, /* Analog mux bus A */ 1528 P8_1_AMUXB = 5, /* Analog mux bus B */ 1529 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1530 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1531 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 1532 P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 1533 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1534 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1535 P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1536 P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1537 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 1538 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 1539 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 1540 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 1541 1542 /* P8.2 */ 1543 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1544 P8_2_AMUXA = 4, /* Analog mux bus A */ 1545 P8_2_AMUXB = 5, /* Analog mux bus B */ 1546 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1547 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1548 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 1549 P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ 1550 P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1551 P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1552 P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1553 P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1554 P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 1555 P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 1556 P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 1557 1558 /* P8.3 */ 1559 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1560 P8_3_AMUXA = 4, /* Analog mux bus A */ 1561 P8_3_AMUXB = 5, /* Analog mux bus B */ 1562 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1563 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1564 P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 1565 P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 1566 P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1567 P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1568 P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1569 P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1570 P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 1571 P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 1572 P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 1573 1574 /* P8.4 */ 1575 P8_4_GPIO = 0, /* GPIO controls 'out' */ 1576 P8_4_AMUXA = 4, /* Analog mux bus A */ 1577 P8_4_AMUXB = 5, /* Analog mux bus B */ 1578 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1579 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1580 P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 1581 P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ 1582 P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1583 P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1584 P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1585 P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1586 P8_4_SCB11_UART_RX = 18, /* Digital Active - scb[11].uart_rx:0 */ 1587 P8_4_SCB11_I2C_SCL = 19, /* Digital Active - scb[11].i2c_scl:0 */ 1588 P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ 1589 1590 /* P8.5 */ 1591 P8_5_GPIO = 0, /* GPIO controls 'out' */ 1592 P8_5_AMUXA = 4, /* Analog mux bus A */ 1593 P8_5_AMUXB = 5, /* Analog mux bus B */ 1594 P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1595 P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1596 P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ 1597 P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ 1598 P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1599 P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1600 P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1601 P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1602 P8_5_SCB11_UART_TX = 18, /* Digital Active - scb[11].uart_tx:0 */ 1603 P8_5_SCB11_I2C_SDA = 19, /* Digital Active - scb[11].i2c_sda:0 */ 1604 P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */ 1605 1606 /* P8.6 */ 1607 P8_6_GPIO = 0, /* GPIO controls 'out' */ 1608 P8_6_AMUXA = 4, /* Analog mux bus A */ 1609 P8_6_AMUXB = 5, /* Analog mux bus B */ 1610 P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1611 P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1612 P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 1613 P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */ 1614 P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ 1615 P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ 1616 P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */ 1617 P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */ 1618 P8_6_SCB11_UART_RTS = 18, /* Digital Active - scb[11].uart_rts:0 */ 1619 P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */ 1620 1621 /* P8.7 */ 1622 P8_7_GPIO = 0, /* GPIO controls 'out' */ 1623 P8_7_AMUXA = 4, /* Analog mux bus A */ 1624 P8_7_AMUXB = 5, /* Analog mux bus B */ 1625 P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1626 P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1627 P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 1628 P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ 1629 P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ 1630 P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ 1631 P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */ 1632 P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */ 1633 P8_7_SCB11_UART_CTS = 18, /* Digital Active - scb[11].uart_cts:0 */ 1634 P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */ 1635 1636 /* P9.0 */ 1637 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1638 P9_0_AMUXA = 4, /* Analog mux bus A */ 1639 P9_0_AMUXB = 5, /* Analog mux bus B */ 1640 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1641 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1642 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ 1643 P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ 1644 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1645 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1646 P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 1647 P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 1648 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 1649 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 1650 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 1651 P9_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:1 */ 1652 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 1653 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1654 1655 /* P9.1 */ 1656 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1657 P9_1_AMUXA = 4, /* Analog mux bus A */ 1658 P9_1_AMUXB = 5, /* Analog mux bus B */ 1659 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1660 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1661 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ 1662 P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 1663 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1664 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1665 P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 1666 P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 1667 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 1668 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 1669 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 1670 P9_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:1 */ 1671 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 1672 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1673 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1674 1675 /* P9.2 */ 1676 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1677 P9_2_AMUXA = 4, /* Analog mux bus A */ 1678 P9_2_AMUXB = 5, /* Analog mux bus B */ 1679 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1680 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1681 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ 1682 P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ 1683 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ 1684 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ 1685 P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1686 P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1687 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 1688 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 1689 P9_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:1 */ 1690 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1691 1692 /* P9.3 */ 1693 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1694 P9_3_AMUXA = 4, /* Analog mux bus A */ 1695 P9_3_AMUXB = 5, /* Analog mux bus B */ 1696 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1697 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1698 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ 1699 P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 1700 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ 1701 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ 1702 P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1703 P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1704 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1705 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1706 P9_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:1 */ 1707 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1708 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1709 1710 /* P9.4 */ 1711 P9_4_GPIO = 0, /* GPIO controls 'out' */ 1712 P9_4_AMUXA = 4, /* Analog mux bus A */ 1713 P9_4_AMUXB = 5, /* Analog mux bus B */ 1714 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1715 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1716 P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */ 1717 P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ 1718 P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */ 1719 P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */ 1720 P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */ 1721 P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */ 1722 P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ 1723 P9_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:1 */ 1724 1725 /* P9.5 */ 1726 P9_5_GPIO = 0, /* GPIO controls 'out' */ 1727 P9_5_AMUXA = 4, /* Analog mux bus A */ 1728 P9_5_AMUXB = 5, /* Analog mux bus B */ 1729 P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1730 P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1731 P9_5_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:5 */ 1732 P9_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */ 1733 P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:67 */ 1734 P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:67 */ 1735 P9_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:1 */ 1736 P9_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:1 */ 1737 P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */ 1738 P9_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:1 */ 1739 1740 /* P9.6 */ 1741 P9_6_GPIO = 0, /* GPIO controls 'out' */ 1742 P9_6_AMUXA = 4, /* Analog mux bus A */ 1743 P9_6_AMUXB = 5, /* Analog mux bus B */ 1744 P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1745 P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1746 P9_6_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 1747 P9_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */ 1748 P9_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:68 */ 1749 P9_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:68 */ 1750 P9_6_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:1 */ 1751 P9_6_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:1 */ 1752 P9_6_SCB2_SPI_SELECT3 = 20, /* Digital Active - scb[2].spi_select3:0 */ 1753 P9_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:1 */ 1754 1755 /* P9.7 */ 1756 P9_7_GPIO = 0, /* GPIO controls 'out' */ 1757 P9_7_AMUXA = 4, /* Analog mux bus A */ 1758 P9_7_AMUXB = 5, /* Analog mux bus B */ 1759 P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1760 P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1761 P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1762 P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ 1763 P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */ 1764 P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */ 1765 P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */ 1766 P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */ 1767 1768 /* P10.0 */ 1769 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1770 P10_0_AMUXA = 4, /* Analog mux bus A */ 1771 P10_0_AMUXB = 5, /* Analog mux bus B */ 1772 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1773 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1774 P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ 1775 P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ 1776 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ 1777 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ 1778 P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ 1779 P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ 1780 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 1781 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 1782 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 1783 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1784 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1785 1786 /* P10.1 */ 1787 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1788 P10_1_AMUXA = 4, /* Analog mux bus A */ 1789 P10_1_AMUXB = 5, /* Analog mux bus B */ 1790 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1791 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1792 P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ 1793 P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 1794 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ 1795 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ 1796 P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ 1797 P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ 1798 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 1799 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 1800 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 1801 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1802 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1803 1804 /* P10.2 */ 1805 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1806 P10_2_AMUXA = 4, /* Analog mux bus A */ 1807 P10_2_AMUXB = 5, /* Analog mux bus B */ 1808 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1809 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1810 P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ 1811 P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ 1812 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ 1813 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ 1814 P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ 1815 P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ 1816 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 1817 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 1818 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1819 1820 /* P10.3 */ 1821 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1822 P10_3_AMUXA = 4, /* Analog mux bus A */ 1823 P10_3_AMUXB = 5, /* Analog mux bus B */ 1824 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1825 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1826 P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ 1827 P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 1828 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ 1829 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ 1830 P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ 1831 P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ 1832 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 1833 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 1834 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1835 1836 /* P10.4 */ 1837 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1838 P10_4_AMUXA = 4, /* Analog mux bus A */ 1839 P10_4_AMUXB = 5, /* Analog mux bus B */ 1840 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1841 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1842 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 1843 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 1844 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ 1845 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ 1846 P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ 1847 P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ 1848 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 1849 P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0 */ 1850 1851 /* P10.5 */ 1852 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1853 P10_5_AMUXA = 4, /* Analog mux bus A */ 1854 P10_5_AMUXB = 5, /* Analog mux bus B */ 1855 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1856 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1857 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 1858 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1859 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ 1860 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ 1861 P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ 1862 P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ 1863 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 1864 P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0 */ 1865 1866 /* P10.6 */ 1867 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1868 P10_6_AMUXA = 4, /* Analog mux bus A */ 1869 P10_6_AMUXB = 5, /* Analog mux bus B */ 1870 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1871 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1872 P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ 1873 P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ 1874 P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */ 1875 P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */ 1876 P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */ 1877 P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */ 1878 P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 1879 1880 /* P10.7 */ 1881 P10_7_GPIO = 0, /* GPIO controls 'out' */ 1882 P10_7_AMUXA = 4, /* Analog mux bus A */ 1883 P10_7_AMUXB = 5, /* Analog mux bus B */ 1884 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1885 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1886 P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ 1887 P10_7_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ 1888 P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:77 */ 1889 P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:77 */ 1890 P10_7_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:1 */ 1891 P10_7_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:1 */ 1892 1893 /* P11.0 */ 1894 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1895 P11_0_AMUXA = 4, /* Analog mux bus A */ 1896 P11_0_AMUXB = 5, /* Analog mux bus B */ 1897 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1898 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1899 P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 1900 P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 1901 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ 1902 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ 1903 P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ 1904 P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ 1905 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1906 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 1907 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 1908 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 1909 P11_0_AUDIOSS1_CLK_I2S_IF = 22, /* Digital Active - audioss[1].clk_i2s_if:1 */ 1910 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1911 1912 /* P11.1 */ 1913 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1914 P11_1_AMUXA = 4, /* Analog mux bus A */ 1915 P11_1_AMUXB = 5, /* Analog mux bus B */ 1916 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1917 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1918 P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 1919 P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1920 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ 1921 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ 1922 P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ 1923 P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ 1924 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1925 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 1926 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 1927 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 1928 P11_1_AUDIOSS1_TX_SCK = 22, /* Digital Active - audioss[1].tx_sck:1 */ 1929 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1930 1931 /* P11.2 */ 1932 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1933 P11_2_AMUXA = 4, /* Analog mux bus A */ 1934 P11_2_AMUXB = 5, /* Analog mux bus B */ 1935 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1936 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1937 P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 1938 P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 1939 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ 1940 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ 1941 P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ 1942 P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ 1943 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1944 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ 1945 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ 1946 P11_2_AUDIOSS1_TX_WS = 22, /* Digital Active - audioss[1].tx_ws:1 */ 1947 1948 /* P11.3 */ 1949 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1950 P11_3_AMUXA = 4, /* Analog mux bus A */ 1951 P11_3_AMUXB = 5, /* Analog mux bus B */ 1952 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1953 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1954 P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 1955 P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1956 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ 1957 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ 1958 P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ 1959 P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ 1960 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1961 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ 1962 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ 1963 P11_3_AUDIOSS1_TX_SDO = 22, /* Digital Active - audioss[1].tx_sdo:1 */ 1964 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1965 1966 /* P11.4 */ 1967 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1968 P11_4_AMUXA = 4, /* Analog mux bus A */ 1969 P11_4_AMUXB = 5, /* Analog mux bus B */ 1970 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1971 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1972 P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 1973 P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 1974 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ 1975 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ 1976 P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ 1977 P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ 1978 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1979 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ 1980 P11_4_AUDIOSS1_RX_SCK = 22, /* Digital Active - audioss[1].rx_sck:1 */ 1981 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1982 1983 /* P11.5 */ 1984 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1985 P11_5_AMUXA = 4, /* Analog mux bus A */ 1986 P11_5_AMUXB = 5, /* Analog mux bus B */ 1987 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1988 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1989 P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 1990 P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1991 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ 1992 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ 1993 P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ 1994 P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ 1995 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1996 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ 1997 P11_5_AUDIOSS1_RX_WS = 22, /* Digital Active - audioss[1].rx_ws:1 */ 1998 1999 /* P11.6 */ 2000 P11_6_GPIO = 0, /* GPIO controls 'out' */ 2001 P11_6_AMUXA = 4, /* Analog mux bus A */ 2002 P11_6_AMUXB = 5, /* Analog mux bus B */ 2003 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2004 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2005 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ 2006 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ 2007 P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ 2008 P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ 2009 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 2010 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ 2011 P11_6_AUDIOSS1_RX_SDI = 22, /* Digital Active - audioss[1].rx_sdi:1 */ 2012 2013 /* P11.7 */ 2014 P11_7_GPIO = 0, /* GPIO controls 'out' */ 2015 P11_7_AMUXA = 4, /* Analog mux bus A */ 2016 P11_7_AMUXB = 5, /* Analog mux bus B */ 2017 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2018 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2019 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 2020 2021 /* P12.0 */ 2022 P12_0_GPIO = 0, /* GPIO controls 'out' */ 2023 P12_0_AMUXA = 4, /* Analog mux bus A */ 2024 P12_0_AMUXB = 5, /* Analog mux bus B */ 2025 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2026 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2027 P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ 2028 P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 2029 P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ 2030 P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ 2031 P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ 2032 P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ 2033 P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ 2034 P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ 2035 P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ 2036 P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ 2037 P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 2038 P12_0_SDHC1_CARD_EMMC_RESET_N = 26, /* Digital Active - sdhc[1].card_emmc_reset_n */ 2039 2040 /* P12.1 */ 2041 P12_1_GPIO = 0, /* GPIO controls 'out' */ 2042 P12_1_AMUXA = 4, /* Analog mux bus A */ 2043 P12_1_AMUXB = 5, /* Analog mux bus B */ 2044 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2045 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2046 P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ 2047 P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 2048 P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ 2049 P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ 2050 P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ 2051 P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ 2052 P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ 2053 P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ 2054 P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ 2055 P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ 2056 P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 2057 P12_1_SDHC1_CARD_DETECT_N = 26, /* Digital Active - sdhc[1].card_detect_n */ 2058 2059 /* P12.2 */ 2060 P12_2_GPIO = 0, /* GPIO controls 'out' */ 2061 P12_2_AMUXA = 4, /* Analog mux bus A */ 2062 P12_2_AMUXB = 5, /* Analog mux bus B */ 2063 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2064 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2065 P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ 2066 P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 2067 P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ 2068 P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ 2069 P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ 2070 P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ 2071 P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ 2072 P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ 2073 P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ 2074 P12_2_SDHC1_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[1].card_mech_write_prot */ 2075 2076 /* P12.3 */ 2077 P12_3_GPIO = 0, /* GPIO controls 'out' */ 2078 P12_3_AMUXA = 4, /* Analog mux bus A */ 2079 P12_3_AMUXB = 5, /* Analog mux bus B */ 2080 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2081 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2082 P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ 2083 P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 2084 P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ 2085 P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ 2086 P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ 2087 P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ 2088 P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ 2089 P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ 2090 P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ 2091 P12_3_SDHC1_LED_CTRL = 26, /* Digital Active - sdhc[1].led_ctrl */ 2092 2093 /* P12.4 */ 2094 P12_4_GPIO = 0, /* GPIO controls 'out' */ 2095 P12_4_AMUXA = 4, /* Analog mux bus A */ 2096 P12_4_AMUXB = 5, /* Analog mux bus B */ 2097 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2098 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2099 P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ 2100 P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 2101 P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ 2102 P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ 2103 P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ 2104 P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ 2105 P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ 2106 P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ 2107 P12_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:1 */ 2108 P12_4_SDHC1_CARD_CMD = 26, /* Digital Active - sdhc[1].card_cmd */ 2109 2110 /* P12.5 */ 2111 P12_5_GPIO = 0, /* GPIO controls 'out' */ 2112 P12_5_AMUXA = 4, /* Analog mux bus A */ 2113 P12_5_AMUXB = 5, /* Analog mux bus B */ 2114 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2115 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2116 P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */ 2117 P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 2118 P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */ 2119 P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */ 2120 P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */ 2121 P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */ 2122 P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ 2123 P12_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:1 */ 2124 P12_5_SDHC1_CLK_CARD = 26, /* Digital Active - sdhc[1].clk_card */ 2125 2126 /* P12.6 */ 2127 P12_6_GPIO = 0, /* GPIO controls 'out' */ 2128 P12_6_AMUXA = 4, /* Analog mux bus A */ 2129 P12_6_AMUXB = 5, /* Analog mux bus B */ 2130 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2131 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2132 P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ 2133 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 2134 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ 2135 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ 2136 P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ 2137 P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ 2138 P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 2139 P12_6_SDHC1_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[1].card_if_pwr_en */ 2140 2141 /* P12.7 */ 2142 P12_7_GPIO = 0, /* GPIO controls 'out' */ 2143 P12_7_AMUXA = 4, /* Analog mux bus A */ 2144 P12_7_AMUXB = 5, /* Analog mux bus B */ 2145 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2146 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2147 P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ 2148 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 2149 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ 2150 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ 2151 P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ 2152 P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ 2153 P12_7_SDHC1_IO_VOLT_SEL = 26, /* Digital Active - sdhc[1].io_volt_sel */ 2154 2155 /* P13.0 */ 2156 P13_0_GPIO = 0, /* GPIO controls 'out' */ 2157 P13_0_AMUXA = 4, /* Analog mux bus A */ 2158 P13_0_AMUXB = 5, /* Analog mux bus B */ 2159 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2160 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2161 P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 2162 P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */ 2163 P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */ 2164 P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */ 2165 P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */ 2166 P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */ 2167 P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ 2168 P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ 2169 P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */ 2170 P13_0_AUDIOSS1_CLK_I2S_IF = 22, /* Digital Active - audioss[1].clk_i2s_if:0 */ 2171 P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */ 2172 P13_0_SDHC1_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[1].card_dat_3to0[0] */ 2173 2174 /* P13.1 */ 2175 P13_1_GPIO = 0, /* GPIO controls 'out' */ 2176 P13_1_AMUXA = 4, /* Analog mux bus A */ 2177 P13_1_AMUXB = 5, /* Analog mux bus B */ 2178 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2179 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2180 P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 2181 P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ 2182 P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */ 2183 P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */ 2184 P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */ 2185 P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */ 2186 P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ 2187 P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ 2188 P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ 2189 P13_1_AUDIOSS1_TX_SCK = 22, /* Digital Active - audioss[1].tx_sck:0 */ 2190 P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ 2191 P13_1_SDHC1_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[1].card_dat_3to0[1] */ 2192 2193 /* P13.2 */ 2194 P13_2_GPIO = 0, /* GPIO controls 'out' */ 2195 P13_2_AMUXA = 4, /* Analog mux bus A */ 2196 P13_2_AMUXB = 5, /* Analog mux bus B */ 2197 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2198 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2199 P13_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 2200 P13_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:1 */ 2201 P13_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:95 */ 2202 P13_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:95 */ 2203 P13_2_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:1 */ 2204 P13_2_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:1 */ 2205 P13_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:1 */ 2206 P13_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:1 */ 2207 P13_2_AUDIOSS1_TX_WS = 22, /* Digital Active - audioss[1].tx_ws:0 */ 2208 P13_2_SDHC1_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[1].card_dat_3to0[2] */ 2209 2210 /* P13.3 */ 2211 P13_3_GPIO = 0, /* GPIO controls 'out' */ 2212 P13_3_AMUXA = 4, /* Analog mux bus A */ 2213 P13_3_AMUXB = 5, /* Analog mux bus B */ 2214 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2215 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2216 P13_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 2217 P13_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:1 */ 2218 P13_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:96 */ 2219 P13_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:96 */ 2220 P13_3_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:1 */ 2221 P13_3_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:1 */ 2222 P13_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:1 */ 2223 P13_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:1 */ 2224 P13_3_AUDIOSS1_TX_SDO = 22, /* Digital Active - audioss[1].tx_sdo:0 */ 2225 P13_3_SDHC1_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[1].card_dat_3to0[3] */ 2226 2227 /* P13.4 */ 2228 P13_4_GPIO = 0, /* GPIO controls 'out' */ 2229 P13_4_AMUXA = 4, /* Analog mux bus A */ 2230 P13_4_AMUXB = 5, /* Analog mux bus B */ 2231 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2232 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2233 P13_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ 2234 P13_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:1 */ 2235 P13_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:97 */ 2236 P13_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:97 */ 2237 P13_4_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:1 */ 2238 P13_4_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:1 */ 2239 P13_4_SCB12_UART_RX = 18, /* Digital Active - scb[12].uart_rx:0 */ 2240 P13_4_SCB12_I2C_SCL = 19, /* Digital Active - scb[12].i2c_scl:0 */ 2241 P13_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:1 */ 2242 P13_4_AUDIOSS1_RX_SCK = 22, /* Digital Active - audioss[1].rx_sck:0 */ 2243 P13_4_SDHC1_CARD_DAT_7TO40 = 26, /* Digital Active - sdhc[1].card_dat_7to4[0] */ 2244 2245 /* P13.5 */ 2246 P13_5_GPIO = 0, /* GPIO controls 'out' */ 2247 P13_5_AMUXA = 4, /* Analog mux bus A */ 2248 P13_5_AMUXB = 5, /* Analog mux bus B */ 2249 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2250 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2251 P13_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ 2252 P13_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:1 */ 2253 P13_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:98 */ 2254 P13_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:98 */ 2255 P13_5_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:1 */ 2256 P13_5_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:1 */ 2257 P13_5_SCB12_UART_TX = 18, /* Digital Active - scb[12].uart_tx:0 */ 2258 P13_5_SCB12_I2C_SDA = 19, /* Digital Active - scb[12].i2c_sda:0 */ 2259 P13_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:1 */ 2260 P13_5_AUDIOSS1_RX_WS = 22, /* Digital Active - audioss[1].rx_ws:0 */ 2261 P13_5_SDHC1_CARD_DAT_7TO41 = 26, /* Digital Active - sdhc[1].card_dat_7to4[1] */ 2262 2263 /* P13.6 */ 2264 P13_6_GPIO = 0, /* GPIO controls 'out' */ 2265 P13_6_AMUXA = 4, /* Analog mux bus A */ 2266 P13_6_AMUXB = 5, /* Analog mux bus B */ 2267 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2268 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2269 P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ 2270 P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */ 2271 P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */ 2272 P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */ 2273 P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */ 2274 P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */ 2275 P13_6_SCB12_UART_RTS = 18, /* Digital Active - scb[12].uart_rts:0 */ 2276 P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */ 2277 P13_6_AUDIOSS1_RX_SDI = 22, /* Digital Active - audioss[1].rx_sdi:0 */ 2278 P13_6_SDHC1_CARD_DAT_7TO42 = 26, /* Digital Active - sdhc[1].card_dat_7to4[2] */ 2279 2280 /* P13.7 */ 2281 P13_7_GPIO = 0, /* GPIO controls 'out' */ 2282 P13_7_AMUXA = 4, /* Analog mux bus A */ 2283 P13_7_AMUXB = 5, /* Analog mux bus B */ 2284 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2285 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2286 P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ 2287 P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ 2288 P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ 2289 P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ 2290 P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ 2291 P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ 2292 P13_7_SCB12_UART_CTS = 18, /* Digital Active - scb[12].uart_cts:0 */ 2293 P13_7_SDHC1_CARD_DAT_7TO43 = 26, /* Digital Active - sdhc[1].card_dat_7to4[3] */ 2294 2295 /* USBDP */ 2296 USBDP_GPIO = 0, /* GPIO controls 'out' */ 2297 2298 /* USBDM */ 2299 USBDM_GPIO = 0 /* GPIO controls 'out' */ 2300 } en_hsiom_sel_t; 2301 2302 #endif /* _GPIO_PSOC6_02_128_TQFP_H_ */ 2303 2304 2305 /* [] END OF FILE */ 2306
