1 /***************************************************************************//** 2 * \file gpio_psoc6_01_68_qfn_ble.h 3 * 4 * \brief 5 * PSoC6_01 device GPIO header for 68-QFN-BLE package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_01_68_QFN_BLE_H_ 28 #define _GPIO_PSOC6_01_68_QFN_BLE_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN 44 #define CY_GPIO_PIN_COUNT 68u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ADFT0_VDDD, 50 AMUXBUS_ADFT1_VDDD, 51 AMUXBUS_ANALOG_VDDA, 52 AMUXBUS_ANALOG_VDDD, 53 AMUXBUS_CSD0, 54 AMUXBUS_CSD1, 55 AMUXBUS_MAIN, 56 AMUXBUS_NOISY, 57 AMUXBUS_SAR, 58 AMUXBUS_VDDIO_1, 59 }; 60 61 /* AMUX Splitter Controls */ 62 typedef enum 63 { 64 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ 65 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ 66 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ 67 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ 68 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 69 AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 70 AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 71 AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ 72 AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ 73 } cy_en_amux_split_t; 74 75 /* Port List */ 76 /* PORT 0 (GPIO) */ 77 #define P0_0_PORT GPIO_PRT0 78 #define P0_0_PIN 0u 79 #define P0_0_NUM 0u 80 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 81 #define P0_1_PORT GPIO_PRT0 82 #define P0_1_PIN 1u 83 #define P0_1_NUM 1u 84 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 85 #define P0_2_PORT GPIO_PRT0 86 #define P0_2_PIN 2u 87 #define P0_2_NUM 2u 88 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 89 #define P0_3_PORT GPIO_PRT0 90 #define P0_3_PIN 3u 91 #define P0_3_NUM 3u 92 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 93 #define P0_4_PORT GPIO_PRT0 94 #define P0_4_PIN 4u 95 #define P0_4_NUM 4u 96 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 97 #define P0_5_PORT GPIO_PRT0 98 #define P0_5_PIN 5u 99 #define P0_5_NUM 5u 100 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 101 102 /* PORT 6 (GPIO) */ 103 #define P6_0_PORT GPIO_PRT6 104 #define P6_0_PIN 0u 105 #define P6_0_NUM 0u 106 #define P6_0_AMUXSEGMENT AMUXBUS_CSD0 107 #define P6_1_PORT GPIO_PRT6 108 #define P6_1_PIN 1u 109 #define P6_1_NUM 1u 110 #define P6_1_AMUXSEGMENT AMUXBUS_CSD0 111 #define P6_2_PORT GPIO_PRT6 112 #define P6_2_PIN 2u 113 #define P6_2_NUM 2u 114 #define P6_2_AMUXSEGMENT AMUXBUS_CSD0 115 #define P6_3_PORT GPIO_PRT6 116 #define P6_3_PIN 3u 117 #define P6_3_NUM 3u 118 #define P6_3_AMUXSEGMENT AMUXBUS_CSD0 119 #define P6_4_PORT GPIO_PRT6 120 #define P6_4_PIN 4u 121 #define P6_4_NUM 4u 122 #define P6_4_AMUXSEGMENT AMUXBUS_CSD0 123 #define P6_5_PORT GPIO_PRT6 124 #define P6_5_PIN 5u 125 #define P6_5_NUM 5u 126 #define P6_5_AMUXSEGMENT AMUXBUS_CSD0 127 #define P6_6_PORT GPIO_PRT6 128 #define P6_6_PIN 6u 129 #define P6_6_NUM 6u 130 #define P6_6_AMUXSEGMENT AMUXBUS_CSD0 131 #define P6_7_PORT GPIO_PRT6 132 #define P6_7_PIN 7u 133 #define P6_7_NUM 7u 134 #define P6_7_AMUXSEGMENT AMUXBUS_CSD0 135 136 /* PORT 7 (GPIO) */ 137 #define P7_0_PORT GPIO_PRT7 138 #define P7_0_PIN 0u 139 #define P7_0_NUM 0u 140 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 141 #define P7_1_PORT GPIO_PRT7 142 #define P7_1_PIN 1u 143 #define P7_1_NUM 1u 144 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 145 #define P7_2_PORT GPIO_PRT7 146 #define P7_2_PIN 2u 147 #define P7_2_NUM 2u 148 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 149 #define P7_3_PORT GPIO_PRT7 150 #define P7_3_PIN 3u 151 #define P7_3_NUM 3u 152 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 153 #define P7_4_PORT GPIO_PRT7 154 #define P7_4_PIN 4u 155 #define P7_4_NUM 4u 156 #define P7_4_AMUXSEGMENT AMUXBUS_CSD0 157 #define P7_5_PORT GPIO_PRT7 158 #define P7_5_PIN 5u 159 #define P7_5_NUM 5u 160 #define P7_5_AMUXSEGMENT AMUXBUS_CSD0 161 #define P7_6_PORT GPIO_PRT7 162 #define P7_6_PIN 6u 163 #define P7_6_NUM 6u 164 #define P7_6_AMUXSEGMENT AMUXBUS_CSD0 165 #define P7_7_PORT GPIO_PRT7 166 #define P7_7_PIN 7u 167 #define P7_7_NUM 7u 168 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 169 170 /* PORT 8 (GPIO) */ 171 #define P8_0_PORT GPIO_PRT8 172 #define P8_0_PIN 0u 173 #define P8_0_NUM 0u 174 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 175 #define P8_1_PORT GPIO_PRT8 176 #define P8_1_PIN 1u 177 #define P8_1_NUM 1u 178 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 179 #define P8_2_PORT GPIO_PRT8 180 #define P8_2_PIN 2u 181 #define P8_2_NUM 2u 182 #define P8_2_AMUXSEGMENT AMUXBUS_CSD0 183 184 /* PORT 9 (GPIO) */ 185 #define P9_0_PORT GPIO_PRT9 186 #define P9_0_PIN 0u 187 #define P9_0_NUM 0u 188 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 189 #define P9_1_PORT GPIO_PRT9 190 #define P9_1_PIN 1u 191 #define P9_1_NUM 1u 192 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 193 #define P9_2_PORT GPIO_PRT9 194 #define P9_2_PIN 2u 195 #define P9_2_NUM 2u 196 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 197 #define P9_3_PORT GPIO_PRT9 198 #define P9_3_PIN 3u 199 #define P9_3_NUM 3u 200 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 201 202 /* PORT 10 (GPIO) */ 203 #define P10_0_PORT GPIO_PRT10 204 #define P10_0_PIN 0u 205 #define P10_0_NUM 0u 206 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 207 #define P10_1_PORT GPIO_PRT10 208 #define P10_1_PIN 1u 209 #define P10_1_NUM 1u 210 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 211 212 /* PORT 11 (GPIO) */ 213 #define P11_0_PORT GPIO_PRT11 214 #define P11_0_PIN 0u 215 #define P11_0_NUM 0u 216 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 217 #define P11_1_PORT GPIO_PRT11 218 #define P11_1_PIN 1u 219 #define P11_1_NUM 1u 220 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 221 #define P11_2_PORT GPIO_PRT11 222 #define P11_2_PIN 2u 223 #define P11_2_NUM 2u 224 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 225 #define P11_3_PORT GPIO_PRT11 226 #define P11_3_PIN 3u 227 #define P11_3_NUM 3u 228 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 229 #define P11_4_PORT GPIO_PRT11 230 #define P11_4_PIN 4u 231 #define P11_4_NUM 4u 232 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 233 #define P11_5_PORT GPIO_PRT11 234 #define P11_5_PIN 5u 235 #define P11_5_NUM 5u 236 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 237 #define P11_6_PORT GPIO_PRT11 238 #define P11_6_PIN 6u 239 #define P11_6_NUM 6u 240 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 241 #define P11_7_PORT GPIO_PRT11 242 #define P11_7_PIN 7u 243 #define P11_7_NUM 7u 244 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 245 246 /* PORT 12 (GPIO) */ 247 #define P12_6_PORT GPIO_PRT12 248 #define P12_6_PIN 6u 249 #define P12_6_NUM 6u 250 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 251 #define P12_7_PORT GPIO_PRT12 252 #define P12_7_PIN 7u 253 #define P12_7_NUM 7u 254 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 255 256 /* Analog Connections */ 257 #define CSD_CMODPADD_PORT 7u 258 #define CSD_CMODPADD_PIN 1u 259 #define CSD_CMODPADS_PORT 7u 260 #define CSD_CMODPADS_PIN 1u 261 #define CSD_CSH_TANKPADD_PORT 7u 262 #define CSD_CSH_TANKPADD_PIN 2u 263 #define CSD_CSH_TANKPADS_PORT 7u 264 #define CSD_CSH_TANKPADS_PIN 2u 265 #define CSD_CSHIELDPADS_PORT 7u 266 #define CSD_CSHIELDPADS_PIN 7u 267 #define CSD_VREF_EXT_PORT 7u 268 #define CSD_VREF_EXT_PIN 3u 269 #define IOSS_ADFT0_NET_PORT 10u 270 #define IOSS_ADFT0_NET_PIN 0u 271 #define IOSS_ADFT1_NET_PORT 10u 272 #define IOSS_ADFT1_NET_PIN 1u 273 #define LPCOMP_INN_COMP1_PORT 6u 274 #define LPCOMP_INN_COMP1_PIN 3u 275 #define LPCOMP_INP_COMP1_PORT 6u 276 #define LPCOMP_INP_COMP1_PIN 2u 277 #define PASS_CTB_OA0_OUT_10X_PORT 9u 278 #define PASS_CTB_OA0_OUT_10X_PIN 2u 279 #define PASS_CTB_OA1_OUT_10X_PORT 9u 280 #define PASS_CTB_OA1_OUT_10X_PIN 3u 281 #define PASS_CTB_PADS0_PORT 9u 282 #define PASS_CTB_PADS0_PIN 0u 283 #define PASS_CTB_PADS1_PORT 9u 284 #define PASS_CTB_PADS1_PIN 1u 285 #define PASS_CTB_PADS2_PORT 9u 286 #define PASS_CTB_PADS2_PIN 2u 287 #define PASS_CTB_PADS3_PORT 9u 288 #define PASS_CTB_PADS3_PIN 3u 289 #define PASS_SARMUX_PADS0_PORT 10u 290 #define PASS_SARMUX_PADS0_PIN 0u 291 #define PASS_SARMUX_PADS1_PORT 10u 292 #define PASS_SARMUX_PADS1_PIN 1u 293 #define SRSS_ADFT_PIN0_PORT 10u 294 #define SRSS_ADFT_PIN0_PIN 0u 295 #define SRSS_ADFT_PIN1_PORT 10u 296 #define SRSS_ADFT_PIN1_PIN 1u 297 #define SRSS_ECO_IN_PORT 12u 298 #define SRSS_ECO_IN_PIN 6u 299 #define SRSS_ECO_OUT_PORT 12u 300 #define SRSS_ECO_OUT_PIN 7u 301 #define SRSS_WCO_IN_PORT 0u 302 #define SRSS_WCO_IN_PIN 0u 303 #define SRSS_WCO_OUT_PORT 0u 304 #define SRSS_WCO_OUT_PIN 1u 305 306 /* HSIOM Connections */ 307 typedef enum 308 { 309 /* Generic HSIOM connections */ 310 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 311 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 312 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 313 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 314 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 315 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 316 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 317 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 318 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 319 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 320 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 321 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 322 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 323 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 324 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 325 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 326 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 327 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 328 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 329 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 330 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 331 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 332 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 333 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 334 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 335 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 336 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 337 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 338 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 339 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 340 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 341 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 342 343 /* P0.0 */ 344 P0_0_GPIO = 0, /* GPIO controls 'out' */ 345 P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 346 P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 347 P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 348 P0_0_AMUXA = 4, /* Analog mux bus A */ 349 P0_0_AMUXB = 5, /* Analog mux bus B */ 350 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 351 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 352 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 353 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 354 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 355 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 356 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 357 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 358 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 359 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 360 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 361 362 /* P0.1 */ 363 P0_1_GPIO = 0, /* GPIO controls 'out' */ 364 P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 365 P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 366 P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 367 P0_1_AMUXA = 4, /* Analog mux bus A */ 368 P0_1_AMUXB = 5, /* Analog mux bus B */ 369 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 370 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 371 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 372 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 373 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 374 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 375 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 376 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 377 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 378 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 379 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 380 381 /* P0.2 */ 382 P0_2_GPIO = 0, /* GPIO controls 'out' */ 383 P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 384 P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 385 P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 386 P0_2_AMUXA = 4, /* Analog mux bus A */ 387 P0_2_AMUXB = 5, /* Analog mux bus B */ 388 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 389 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 390 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 391 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 392 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 393 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 394 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 395 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 396 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 397 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 398 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 399 400 /* P0.3 */ 401 P0_3_GPIO = 0, /* GPIO controls 'out' */ 402 P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 403 P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 404 P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 405 P0_3_AMUXA = 4, /* Analog mux bus A */ 406 P0_3_AMUXB = 5, /* Analog mux bus B */ 407 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 408 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 409 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 410 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 411 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 412 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 413 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 414 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 415 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 416 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 417 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 418 419 /* P0.4 */ 420 P0_4_GPIO = 0, /* GPIO controls 'out' */ 421 P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 422 P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 423 P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 424 P0_4_AMUXA = 4, /* Analog mux bus A */ 425 P0_4_AMUXB = 5, /* Analog mux bus B */ 426 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 427 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 428 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 429 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 430 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 431 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 432 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 433 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 434 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 435 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 436 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 437 438 /* P0.5 */ 439 P0_5_GPIO = 0, /* GPIO controls 'out' */ 440 P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 441 P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 442 P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 443 P0_5_AMUXA = 4, /* Analog mux bus A */ 444 P0_5_AMUXB = 5, /* Analog mux bus B */ 445 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 446 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 447 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 448 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 449 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 450 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 451 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 452 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 453 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 454 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 455 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 456 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 457 458 /* P6.0 */ 459 P6_0_GPIO = 0, /* GPIO controls 'out' */ 460 P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 461 P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 462 P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 463 P6_0_AMUXA = 4, /* Analog mux bus A */ 464 P6_0_AMUXB = 5, /* Analog mux bus B */ 465 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 466 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 467 P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 468 P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ 469 P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 470 P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 471 P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ 472 P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ 473 P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ 474 P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 475 P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 476 P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ 477 P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 478 P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ 479 480 /* P6.1 */ 481 P6_1_GPIO = 0, /* GPIO controls 'out' */ 482 P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 483 P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 484 P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 485 P6_1_AMUXA = 4, /* Analog mux bus A */ 486 P6_1_AMUXB = 5, /* Analog mux bus B */ 487 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 488 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 489 P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 490 P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 491 P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 492 P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 493 P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ 494 P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ 495 P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ 496 P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 497 P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 498 P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ 499 P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 500 P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ 501 502 /* P6.2 */ 503 P6_2_GPIO = 0, /* GPIO controls 'out' */ 504 P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 505 P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 506 P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 507 P6_2_AMUXA = 4, /* Analog mux bus A */ 508 P6_2_AMUXB = 5, /* Analog mux bus B */ 509 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 510 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 511 P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 512 P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ 513 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 514 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 515 P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 516 P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 517 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 518 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 519 P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ 520 521 /* P6.3 */ 522 P6_3_GPIO = 0, /* GPIO controls 'out' */ 523 P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 524 P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 525 P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 526 P6_3_AMUXA = 4, /* Analog mux bus A */ 527 P6_3_AMUXB = 5, /* Analog mux bus B */ 528 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 529 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 530 P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 531 P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 532 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 533 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 534 P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 535 P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 536 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 537 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 538 P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ 539 540 /* P6.4 */ 541 P6_4_GPIO = 0, /* GPIO controls 'out' */ 542 P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 543 P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 544 P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 545 P6_4_AMUXA = 4, /* Analog mux bus A */ 546 P6_4_AMUXB = 5, /* Analog mux bus B */ 547 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 548 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 549 P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 550 P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ 551 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 552 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 553 P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 554 P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 555 P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ 556 P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ 557 P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ 558 P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ 559 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 560 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 561 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 562 P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ 563 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 564 565 /* P6.5 */ 566 P6_5_GPIO = 0, /* GPIO controls 'out' */ 567 P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 568 P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 569 P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 570 P6_5_AMUXA = 4, /* Analog mux bus A */ 571 P6_5_AMUXB = 5, /* Analog mux bus B */ 572 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 573 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 574 P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 575 P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 576 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 577 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 578 P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 579 P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 580 P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ 581 P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ 582 P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ 583 P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ 584 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 585 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 586 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 587 P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ 588 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 589 590 /* P6.6 */ 591 P6_6_GPIO = 0, /* GPIO controls 'out' */ 592 P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 593 P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 594 P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 595 P6_6_AMUXA = 4, /* Analog mux bus A */ 596 P6_6_AMUXB = 5, /* Analog mux bus B */ 597 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 598 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 599 P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 600 P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ 601 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 602 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 603 P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 604 P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 605 P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ 606 P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ 607 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 608 P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ 609 610 /* P6.7 */ 611 P6_7_GPIO = 0, /* GPIO controls 'out' */ 612 P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 613 P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 614 P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 615 P6_7_AMUXA = 4, /* Analog mux bus A */ 616 P6_7_AMUXB = 5, /* Analog mux bus B */ 617 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 618 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 619 P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 620 P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 621 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 622 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 623 P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 624 P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 625 P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ 626 P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ 627 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 628 P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ 629 630 /* P7.0 */ 631 P7_0_GPIO = 0, /* GPIO controls 'out' */ 632 P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 633 P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 634 P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 635 P7_0_AMUXA = 4, /* Analog mux bus A */ 636 P7_0_AMUXB = 5, /* Analog mux bus B */ 637 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 638 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 639 P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 640 P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ 641 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 642 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 643 P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 644 P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 645 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 646 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 647 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 648 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 649 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 650 651 /* P7.1 */ 652 P7_1_GPIO = 0, /* GPIO controls 'out' */ 653 P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 654 P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 655 P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 656 P7_1_AMUXA = 4, /* Analog mux bus A */ 657 P7_1_AMUXB = 5, /* Analog mux bus B */ 658 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 659 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 660 P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 661 P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 662 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 663 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 664 P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 665 P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 666 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 667 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 668 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 669 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 670 671 /* P7.2 */ 672 P7_2_GPIO = 0, /* GPIO controls 'out' */ 673 P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 674 P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 675 P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 676 P7_2_AMUXA = 4, /* Analog mux bus A */ 677 P7_2_AMUXB = 5, /* Analog mux bus B */ 678 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 679 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 680 P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 681 P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ 682 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 683 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 684 P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 685 P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 686 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 687 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 688 689 /* P7.3 */ 690 P7_3_GPIO = 0, /* GPIO controls 'out' */ 691 P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 692 P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 693 P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 694 P7_3_AMUXA = 4, /* Analog mux bus A */ 695 P7_3_AMUXB = 5, /* Analog mux bus B */ 696 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 697 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 698 P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 699 P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 700 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 701 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 702 P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 703 P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 704 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 705 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 706 707 /* P7.4 */ 708 P7_4_GPIO = 0, /* GPIO controls 'out' */ 709 P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 710 P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 711 P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 712 P7_4_AMUXA = 4, /* Analog mux bus A */ 713 P7_4_AMUXB = 5, /* Analog mux bus B */ 714 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 715 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 716 P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 717 P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ 718 P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ 719 P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ 720 P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ 721 P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ 722 P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ 723 P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */ 724 P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 725 726 /* P7.5 */ 727 P7_5_GPIO = 0, /* GPIO controls 'out' */ 728 P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 729 P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 730 P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 731 P7_5_AMUXA = 4, /* Analog mux bus A */ 732 P7_5_AMUXB = 5, /* Analog mux bus B */ 733 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 734 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 735 P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 736 P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ 737 P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ 738 P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ 739 P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ 740 P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ 741 P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ 742 P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */ 743 P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ 744 745 /* P7.6 */ 746 P7_6_GPIO = 0, /* GPIO controls 'out' */ 747 P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 748 P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 749 P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 750 P7_6_AMUXA = 4, /* Analog mux bus A */ 751 P7_6_AMUXB = 5, /* Analog mux bus B */ 752 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 753 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 754 P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 755 P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ 756 P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 757 P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 758 P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ 759 P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ 760 P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ 761 P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */ 762 P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ 763 764 /* P7.7 */ 765 P7_7_GPIO = 0, /* GPIO controls 'out' */ 766 P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 767 P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 768 P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 769 P7_7_AMUXA = 4, /* Analog mux bus A */ 770 P7_7_AMUXB = 5, /* Analog mux bus B */ 771 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 772 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 773 P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 774 P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 775 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 776 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 777 P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 778 P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 779 P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ 780 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 781 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 782 783 /* P8.0 */ 784 P8_0_GPIO = 0, /* GPIO controls 'out' */ 785 P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 786 P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 787 P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 788 P8_0_AMUXA = 4, /* Analog mux bus A */ 789 P8_0_AMUXB = 5, /* Analog mux bus B */ 790 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 791 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 792 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 793 P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ 794 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 795 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 796 P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 797 P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 798 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 799 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 800 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 801 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 802 803 /* P8.1 */ 804 P8_1_GPIO = 0, /* GPIO controls 'out' */ 805 P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 806 P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 807 P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 808 P8_1_AMUXA = 4, /* Analog mux bus A */ 809 P8_1_AMUXB = 5, /* Analog mux bus B */ 810 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 811 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 812 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 813 P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 814 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 815 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 816 P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 817 P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 818 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 819 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 820 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 821 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 822 823 /* P8.2 */ 824 P8_2_GPIO = 0, /* GPIO controls 'out' */ 825 P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 826 P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 827 P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 828 P8_2_AMUXA = 4, /* Analog mux bus A */ 829 P8_2_AMUXB = 5, /* Analog mux bus B */ 830 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 831 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 832 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 833 P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ 834 P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 835 P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 836 P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 837 P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 838 P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 839 P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 840 P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 841 842 /* P9.0 */ 843 P9_0_GPIO = 0, /* GPIO controls 'out' */ 844 P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 845 P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 846 P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 847 P9_0_AMUXA = 4, /* Analog mux bus A */ 848 P9_0_AMUXB = 5, /* Analog mux bus B */ 849 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 850 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 851 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ 852 P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ 853 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 854 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 855 P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 856 P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 857 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 858 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 859 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 860 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 861 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 862 863 /* P9.1 */ 864 P9_1_GPIO = 0, /* GPIO controls 'out' */ 865 P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 866 P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 867 P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 868 P9_1_AMUXA = 4, /* Analog mux bus A */ 869 P9_1_AMUXB = 5, /* Analog mux bus B */ 870 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 871 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 872 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ 873 P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 874 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 875 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 876 P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 877 P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 878 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 879 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 880 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 881 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 882 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 883 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 884 885 /* P9.2 */ 886 P9_2_GPIO = 0, /* GPIO controls 'out' */ 887 P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 888 P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 889 P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 890 P9_2_AMUXA = 4, /* Analog mux bus A */ 891 P9_2_AMUXB = 5, /* Analog mux bus B */ 892 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 893 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 894 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ 895 P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ 896 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ 897 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ 898 P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 899 P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 900 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 901 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 902 P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ 903 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 904 905 /* P9.3 */ 906 P9_3_GPIO = 0, /* GPIO controls 'out' */ 907 P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 908 P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 909 P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 910 P9_3_AMUXA = 4, /* Analog mux bus A */ 911 P9_3_AMUXB = 5, /* Analog mux bus B */ 912 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 913 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 914 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ 915 P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 916 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ 917 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ 918 P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 919 P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 920 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 921 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 922 P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ 923 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 924 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 925 926 /* P10.0 */ 927 P10_0_GPIO = 0, /* GPIO controls 'out' */ 928 P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 929 P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 930 P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 931 P10_0_AMUXA = 4, /* Analog mux bus A */ 932 P10_0_AMUXB = 5, /* Analog mux bus B */ 933 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 934 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 935 P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ 936 P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ 937 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ 938 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ 939 P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ 940 P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ 941 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 942 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 943 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 944 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 945 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 946 947 /* P10.1 */ 948 P10_1_GPIO = 0, /* GPIO controls 'out' */ 949 P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 950 P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 951 P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 952 P10_1_AMUXA = 4, /* Analog mux bus A */ 953 P10_1_AMUXB = 5, /* Analog mux bus B */ 954 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 955 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 956 P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ 957 P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 958 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ 959 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ 960 P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ 961 P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ 962 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 963 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 964 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 965 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 966 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 967 968 /* P11.0 */ 969 P11_0_GPIO = 0, /* GPIO controls 'out' */ 970 P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 971 P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 972 P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 973 P11_0_AMUXA = 4, /* Analog mux bus A */ 974 P11_0_AMUXB = 5, /* Analog mux bus B */ 975 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 976 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 977 P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 978 P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 979 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ 980 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ 981 P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ 982 P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ 983 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 984 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 985 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 986 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 987 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 988 989 /* P11.1 */ 990 P11_1_GPIO = 0, /* GPIO controls 'out' */ 991 P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 992 P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 993 P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 994 P11_1_AMUXA = 4, /* Analog mux bus A */ 995 P11_1_AMUXB = 5, /* Analog mux bus B */ 996 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 997 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 998 P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 999 P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1000 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ 1001 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ 1002 P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ 1003 P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ 1004 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1005 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 1006 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 1007 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 1008 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1009 1010 /* P11.2 */ 1011 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1012 P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1013 P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1014 P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1015 P11_2_AMUXA = 4, /* Analog mux bus A */ 1016 P11_2_AMUXB = 5, /* Analog mux bus B */ 1017 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1018 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1019 P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 1020 P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 1021 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ 1022 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ 1023 P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ 1024 P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ 1025 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1026 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ 1027 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ 1028 1029 /* P11.3 */ 1030 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1031 P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1032 P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1033 P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1034 P11_3_AMUXA = 4, /* Analog mux bus A */ 1035 P11_3_AMUXB = 5, /* Analog mux bus B */ 1036 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1037 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1038 P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 1039 P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1040 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ 1041 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ 1042 P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ 1043 P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ 1044 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1045 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ 1046 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ 1047 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1048 1049 /* P11.4 */ 1050 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1051 P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1052 P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1053 P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1054 P11_4_AMUXA = 4, /* Analog mux bus A */ 1055 P11_4_AMUXB = 5, /* Analog mux bus B */ 1056 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1057 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1058 P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 1059 P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 1060 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ 1061 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ 1062 P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ 1063 P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ 1064 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1065 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ 1066 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1067 1068 /* P11.5 */ 1069 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1070 P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1071 P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1072 P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1073 P11_5_AMUXA = 4, /* Analog mux bus A */ 1074 P11_5_AMUXB = 5, /* Analog mux bus B */ 1075 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1076 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1077 P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 1078 P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1079 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ 1080 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ 1081 P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ 1082 P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ 1083 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1084 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ 1085 1086 /* P11.6 */ 1087 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1088 P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1089 P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1090 P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1091 P11_6_AMUXA = 4, /* Analog mux bus A */ 1092 P11_6_AMUXB = 5, /* Analog mux bus B */ 1093 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1094 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1095 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ 1096 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ 1097 P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ 1098 P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ 1099 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1100 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ 1101 1102 /* P11.7 */ 1103 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1104 P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1105 P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1106 P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1107 P11_7_AMUXA = 4, /* Analog mux bus A */ 1108 P11_7_AMUXB = 5, /* Analog mux bus B */ 1109 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1110 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1111 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1112 1113 /* P12.6 */ 1114 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1115 P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1116 P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1117 P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1118 P12_6_AMUXA = 4, /* Analog mux bus A */ 1119 P12_6_AMUXB = 5, /* Analog mux bus B */ 1120 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1121 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1122 P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ 1123 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 1124 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ 1125 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ 1126 P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ 1127 P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ 1128 P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 1129 1130 /* P12.7 */ 1131 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1132 P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1133 P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1134 P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1135 P12_7_AMUXA = 4, /* Analog mux bus A */ 1136 P12_7_AMUXB = 5, /* Analog mux bus B */ 1137 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1138 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1139 P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ 1140 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 1141 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ 1142 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ 1143 P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ 1144 P12_7_LCD_SEG30 = 13 /* Digital Deep Sleep - lcd.seg[30]:1 */ 1145 } en_hsiom_sel_t; 1146 1147 #endif /* _GPIO_PSOC6_01_68_QFN_BLE_H_ */ 1148 1149 1150 /* [] END OF FILE */ 1151
