1 /***************************************************************************//** 2 * \file gpio_psoc6_01_116_bga_ble.h 3 * 4 * \brief 5 * PSoC6_01 device GPIO header for 116-BGA-BLE package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_01_116_BGA_BLE_H_ 28 #define _GPIO_PSOC6_01_116_BGA_BLE_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA 44 #define CY_GPIO_PIN_COUNT 116u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ADFT0_VDDD, 50 AMUXBUS_ADFT1_VDDD, 51 AMUXBUS_ANALOG_VDDA, 52 AMUXBUS_ANALOG_VDDD, 53 AMUXBUS_CSD0, 54 AMUXBUS_CSD1, 55 AMUXBUS_MAIN, 56 AMUXBUS_NOISY, 57 AMUXBUS_SAR, 58 AMUXBUS_VDDIO_1, 59 }; 60 61 /* AMUX Splitter Controls */ 62 typedef enum 63 { 64 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ 65 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ 66 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ 67 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ 68 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 69 AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 70 AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 71 AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ 72 AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ 73 } cy_en_amux_split_t; 74 75 /* Port List */ 76 /* PORT 0 (GPIO) */ 77 #define P0_0_PORT GPIO_PRT0 78 #define P0_0_PIN 0u 79 #define P0_0_NUM 0u 80 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 81 #define P0_1_PORT GPIO_PRT0 82 #define P0_1_PIN 1u 83 #define P0_1_NUM 1u 84 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 85 #define P0_2_PORT GPIO_PRT0 86 #define P0_2_PIN 2u 87 #define P0_2_NUM 2u 88 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 89 #define P0_3_PORT GPIO_PRT0 90 #define P0_3_PIN 3u 91 #define P0_3_NUM 3u 92 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 93 #define P0_4_PORT GPIO_PRT0 94 #define P0_4_PIN 4u 95 #define P0_4_NUM 4u 96 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 97 #define P0_5_PORT GPIO_PRT0 98 #define P0_5_PIN 5u 99 #define P0_5_NUM 5u 100 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 101 102 /* PORT 1 (GPIO_OVT) */ 103 #define P1_0_PORT GPIO_PRT1 104 #define P1_0_PIN 0u 105 #define P1_0_NUM 0u 106 #define P1_0_AMUXSEGMENT AMUXBUS_NOISY 107 #define P1_1_PORT GPIO_PRT1 108 #define P1_1_PIN 1u 109 #define P1_1_NUM 1u 110 #define P1_1_AMUXSEGMENT AMUXBUS_NOISY 111 #define P1_2_PORT GPIO_PRT1 112 #define P1_2_PIN 2u 113 #define P1_2_NUM 2u 114 #define P1_2_AMUXSEGMENT AMUXBUS_NOISY 115 #define P1_3_PORT GPIO_PRT1 116 #define P1_3_PIN 3u 117 #define P1_3_NUM 3u 118 #define P1_3_AMUXSEGMENT AMUXBUS_NOISY 119 #define P1_4_PORT GPIO_PRT1 120 #define P1_4_PIN 4u 121 #define P1_4_NUM 4u 122 #define P1_4_AMUXSEGMENT AMUXBUS_NOISY 123 #define P1_5_PORT GPIO_PRT1 124 #define P1_5_PIN 5u 125 #define P1_5_NUM 5u 126 #define P1_5_AMUXSEGMENT AMUXBUS_NOISY 127 128 /* PORT 5 (GPIO) */ 129 #define P5_0_PORT GPIO_PRT5 130 #define P5_0_PIN 0u 131 #define P5_0_NUM 0u 132 #define P5_0_AMUXSEGMENT AMUXBUS_CSD0 133 #define P5_1_PORT GPIO_PRT5 134 #define P5_1_PIN 1u 135 #define P5_1_NUM 1u 136 #define P5_1_AMUXSEGMENT AMUXBUS_CSD0 137 #define P5_2_PORT GPIO_PRT5 138 #define P5_2_PIN 2u 139 #define P5_2_NUM 2u 140 #define P5_2_AMUXSEGMENT AMUXBUS_CSD0 141 #define P5_3_PORT GPIO_PRT5 142 #define P5_3_PIN 3u 143 #define P5_3_NUM 3u 144 #define P5_3_AMUXSEGMENT AMUXBUS_CSD0 145 #define P5_4_PORT GPIO_PRT5 146 #define P5_4_PIN 4u 147 #define P5_4_NUM 4u 148 #define P5_4_AMUXSEGMENT AMUXBUS_CSD0 149 #define P5_5_PORT GPIO_PRT5 150 #define P5_5_PIN 5u 151 #define P5_5_NUM 5u 152 #define P5_5_AMUXSEGMENT AMUXBUS_CSD0 153 #define P5_6_PORT GPIO_PRT5 154 #define P5_6_PIN 6u 155 #define P5_6_NUM 6u 156 #define P5_6_AMUXSEGMENT AMUXBUS_CSD0 157 158 /* PORT 6 (GPIO) */ 159 #define P6_0_PORT GPIO_PRT6 160 #define P6_0_PIN 0u 161 #define P6_0_NUM 0u 162 #define P6_0_AMUXSEGMENT AMUXBUS_CSD0 163 #define P6_1_PORT GPIO_PRT6 164 #define P6_1_PIN 1u 165 #define P6_1_NUM 1u 166 #define P6_1_AMUXSEGMENT AMUXBUS_CSD0 167 #define P6_2_PORT GPIO_PRT6 168 #define P6_2_PIN 2u 169 #define P6_2_NUM 2u 170 #define P6_2_AMUXSEGMENT AMUXBUS_CSD0 171 #define P6_3_PORT GPIO_PRT6 172 #define P6_3_PIN 3u 173 #define P6_3_NUM 3u 174 #define P6_3_AMUXSEGMENT AMUXBUS_CSD0 175 #define P6_4_PORT GPIO_PRT6 176 #define P6_4_PIN 4u 177 #define P6_4_NUM 4u 178 #define P6_4_AMUXSEGMENT AMUXBUS_CSD0 179 #define P6_5_PORT GPIO_PRT6 180 #define P6_5_PIN 5u 181 #define P6_5_NUM 5u 182 #define P6_5_AMUXSEGMENT AMUXBUS_CSD0 183 #define P6_6_PORT GPIO_PRT6 184 #define P6_6_PIN 6u 185 #define P6_6_NUM 6u 186 #define P6_6_AMUXSEGMENT AMUXBUS_CSD0 187 #define P6_7_PORT GPIO_PRT6 188 #define P6_7_PIN 7u 189 #define P6_7_NUM 7u 190 #define P6_7_AMUXSEGMENT AMUXBUS_CSD0 191 192 /* PORT 7 (GPIO) */ 193 #define P7_0_PORT GPIO_PRT7 194 #define P7_0_PIN 0u 195 #define P7_0_NUM 0u 196 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 197 #define P7_1_PORT GPIO_PRT7 198 #define P7_1_PIN 1u 199 #define P7_1_NUM 1u 200 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 201 #define P7_2_PORT GPIO_PRT7 202 #define P7_2_PIN 2u 203 #define P7_2_NUM 2u 204 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 205 #define P7_3_PORT GPIO_PRT7 206 #define P7_3_PIN 3u 207 #define P7_3_NUM 3u 208 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 209 #define P7_4_PORT GPIO_PRT7 210 #define P7_4_PIN 4u 211 #define P7_4_NUM 4u 212 #define P7_4_AMUXSEGMENT AMUXBUS_CSD0 213 #define P7_5_PORT GPIO_PRT7 214 #define P7_5_PIN 5u 215 #define P7_5_NUM 5u 216 #define P7_5_AMUXSEGMENT AMUXBUS_CSD0 217 #define P7_6_PORT GPIO_PRT7 218 #define P7_6_PIN 6u 219 #define P7_6_NUM 6u 220 #define P7_6_AMUXSEGMENT AMUXBUS_CSD0 221 #define P7_7_PORT GPIO_PRT7 222 #define P7_7_PIN 7u 223 #define P7_7_NUM 7u 224 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 225 226 /* PORT 8 (GPIO) */ 227 #define P8_0_PORT GPIO_PRT8 228 #define P8_0_PIN 0u 229 #define P8_0_NUM 0u 230 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 231 #define P8_1_PORT GPIO_PRT8 232 #define P8_1_PIN 1u 233 #define P8_1_NUM 1u 234 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 235 #define P8_2_PORT GPIO_PRT8 236 #define P8_2_PIN 2u 237 #define P8_2_NUM 2u 238 #define P8_2_AMUXSEGMENT AMUXBUS_CSD0 239 #define P8_3_PORT GPIO_PRT8 240 #define P8_3_PIN 3u 241 #define P8_3_NUM 3u 242 #define P8_3_AMUXSEGMENT AMUXBUS_CSD0 243 #define P8_4_PORT GPIO_PRT8 244 #define P8_4_PIN 4u 245 #define P8_4_NUM 4u 246 #define P8_4_AMUXSEGMENT AMUXBUS_CSD0 247 #define P8_5_PORT GPIO_PRT8 248 #define P8_5_PIN 5u 249 #define P8_5_NUM 5u 250 #define P8_5_AMUXSEGMENT AMUXBUS_CSD0 251 #define P8_6_PORT GPIO_PRT8 252 #define P8_6_PIN 6u 253 #define P8_6_NUM 6u 254 #define P8_6_AMUXSEGMENT AMUXBUS_CSD0 255 #define P8_7_PORT GPIO_PRT8 256 #define P8_7_PIN 7u 257 #define P8_7_NUM 7u 258 #define P8_7_AMUXSEGMENT AMUXBUS_CSD0 259 260 /* PORT 9 (GPIO) */ 261 #define P9_0_PORT GPIO_PRT9 262 #define P9_0_PIN 0u 263 #define P9_0_NUM 0u 264 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 265 #define P9_1_PORT GPIO_PRT9 266 #define P9_1_PIN 1u 267 #define P9_1_NUM 1u 268 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 269 #define P9_2_PORT GPIO_PRT9 270 #define P9_2_PIN 2u 271 #define P9_2_NUM 2u 272 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 273 #define P9_3_PORT GPIO_PRT9 274 #define P9_3_PIN 3u 275 #define P9_3_NUM 3u 276 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 277 #define P9_4_PORT GPIO_PRT9 278 #define P9_4_PIN 4u 279 #define P9_4_NUM 4u 280 #define P9_4_AMUXSEGMENT AMUXBUS_SAR 281 #define P9_5_PORT GPIO_PRT9 282 #define P9_5_PIN 5u 283 #define P9_5_NUM 5u 284 #define P9_5_AMUXSEGMENT AMUXBUS_SAR 285 #define P9_6_PORT GPIO_PRT9 286 #define P9_6_PIN 6u 287 #define P9_6_NUM 6u 288 #define P9_6_AMUXSEGMENT AMUXBUS_SAR 289 #define P9_7_PORT GPIO_PRT9 290 #define P9_7_PIN 7u 291 #define P9_7_NUM 7u 292 #define P9_7_AMUXSEGMENT AMUXBUS_SAR 293 294 /* PORT 10 (GPIO) */ 295 #define P10_0_PORT GPIO_PRT10 296 #define P10_0_PIN 0u 297 #define P10_0_NUM 0u 298 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 299 #define P10_1_PORT GPIO_PRT10 300 #define P10_1_PIN 1u 301 #define P10_1_NUM 1u 302 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 303 #define P10_2_PORT GPIO_PRT10 304 #define P10_2_PIN 2u 305 #define P10_2_NUM 2u 306 #define P10_2_AMUXSEGMENT AMUXBUS_SAR 307 #define P10_3_PORT GPIO_PRT10 308 #define P10_3_PIN 3u 309 #define P10_3_NUM 3u 310 #define P10_3_AMUXSEGMENT AMUXBUS_SAR 311 #define P10_4_PORT GPIO_PRT10 312 #define P10_4_PIN 4u 313 #define P10_4_NUM 4u 314 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 315 #define P10_5_PORT GPIO_PRT10 316 #define P10_5_PIN 5u 317 #define P10_5_NUM 5u 318 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 319 #define P10_6_PORT GPIO_PRT10 320 #define P10_6_PIN 6u 321 #define P10_6_NUM 6u 322 #define P10_6_AMUXSEGMENT AMUXBUS_SAR 323 324 /* PORT 11 (GPIO) */ 325 #define P11_0_PORT GPIO_PRT11 326 #define P11_0_PIN 0u 327 #define P11_0_NUM 0u 328 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 329 #define P11_1_PORT GPIO_PRT11 330 #define P11_1_PIN 1u 331 #define P11_1_NUM 1u 332 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 333 #define P11_2_PORT GPIO_PRT11 334 #define P11_2_PIN 2u 335 #define P11_2_NUM 2u 336 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 337 #define P11_3_PORT GPIO_PRT11 338 #define P11_3_PIN 3u 339 #define P11_3_NUM 3u 340 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 341 #define P11_4_PORT GPIO_PRT11 342 #define P11_4_PIN 4u 343 #define P11_4_NUM 4u 344 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 345 #define P11_5_PORT GPIO_PRT11 346 #define P11_5_PIN 5u 347 #define P11_5_NUM 5u 348 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 349 #define P11_6_PORT GPIO_PRT11 350 #define P11_6_PIN 6u 351 #define P11_6_NUM 6u 352 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 353 #define P11_7_PORT GPIO_PRT11 354 #define P11_7_PIN 7u 355 #define P11_7_NUM 7u 356 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 357 358 /* PORT 12 (GPIO) */ 359 #define P12_0_PORT GPIO_PRT12 360 #define P12_0_PIN 0u 361 #define P12_0_NUM 0u 362 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 363 #define P12_1_PORT GPIO_PRT12 364 #define P12_1_PIN 1u 365 #define P12_1_NUM 1u 366 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 367 #define P12_2_PORT GPIO_PRT12 368 #define P12_2_PIN 2u 369 #define P12_2_NUM 2u 370 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 371 #define P12_3_PORT GPIO_PRT12 372 #define P12_3_PIN 3u 373 #define P12_3_NUM 3u 374 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 375 #define P12_4_PORT GPIO_PRT12 376 #define P12_4_PIN 4u 377 #define P12_4_NUM 4u 378 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 379 #define P12_5_PORT GPIO_PRT12 380 #define P12_5_PIN 5u 381 #define P12_5_NUM 5u 382 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 383 #define P12_6_PORT GPIO_PRT12 384 #define P12_6_PIN 6u 385 #define P12_6_NUM 6u 386 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 387 #define P12_7_PORT GPIO_PRT12 388 #define P12_7_PIN 7u 389 #define P12_7_NUM 7u 390 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 391 392 /* PORT 13 (GPIO) */ 393 #define P13_0_PORT GPIO_PRT13 394 #define P13_0_PIN 0u 395 #define P13_0_NUM 0u 396 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 397 #define P13_1_PORT GPIO_PRT13 398 #define P13_1_PIN 1u 399 #define P13_1_NUM 1u 400 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 401 #define P13_6_PORT GPIO_PRT13 402 #define P13_6_PIN 6u 403 #define P13_6_NUM 6u 404 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 405 #define P13_7_PORT GPIO_PRT13 406 #define P13_7_PIN 7u 407 #define P13_7_NUM 7u 408 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 409 410 /* Analog Connections */ 411 #define CSD_CMODPADD_PORT 7u 412 #define CSD_CMODPADD_PIN 1u 413 #define CSD_CMODPADS_PORT 7u 414 #define CSD_CMODPADS_PIN 1u 415 #define CSD_CSH_TANKPADD_PORT 7u 416 #define CSD_CSH_TANKPADD_PIN 2u 417 #define CSD_CSH_TANKPADS_PORT 7u 418 #define CSD_CSH_TANKPADS_PIN 2u 419 #define CSD_CSHIELDPADS_PORT 7u 420 #define CSD_CSHIELDPADS_PIN 7u 421 #define CSD_VREF_EXT_PORT 7u 422 #define CSD_VREF_EXT_PIN 3u 423 #define IOSS_ADFT0_NET_PORT 10u 424 #define IOSS_ADFT0_NET_PIN 0u 425 #define IOSS_ADFT1_NET_PORT 10u 426 #define IOSS_ADFT1_NET_PIN 1u 427 #define LPCOMP_INN_COMP1_PORT 6u 428 #define LPCOMP_INN_COMP1_PIN 3u 429 #define LPCOMP_INP_COMP0_PORT 5u 430 #define LPCOMP_INP_COMP0_PIN 6u 431 #define LPCOMP_INP_COMP1_PORT 6u 432 #define LPCOMP_INP_COMP1_PIN 2u 433 #define PASS_AREF_EXT_VREF_PORT 9u 434 #define PASS_AREF_EXT_VREF_PIN 7u 435 #define PASS_CTB_OA0_OUT_10X_PORT 9u 436 #define PASS_CTB_OA0_OUT_10X_PIN 2u 437 #define PASS_CTB_OA1_OUT_10X_PORT 9u 438 #define PASS_CTB_OA1_OUT_10X_PIN 3u 439 #define PASS_CTB_PADS0_PORT 9u 440 #define PASS_CTB_PADS0_PIN 0u 441 #define PASS_CTB_PADS1_PORT 9u 442 #define PASS_CTB_PADS1_PIN 1u 443 #define PASS_CTB_PADS2_PORT 9u 444 #define PASS_CTB_PADS2_PIN 2u 445 #define PASS_CTB_PADS3_PORT 9u 446 #define PASS_CTB_PADS3_PIN 3u 447 #define PASS_CTB_PADS4_PORT 9u 448 #define PASS_CTB_PADS4_PIN 4u 449 #define PASS_CTB_PADS5_PORT 9u 450 #define PASS_CTB_PADS5_PIN 5u 451 #define PASS_CTB_PADS6_PORT 9u 452 #define PASS_CTB_PADS6_PIN 6u 453 #define PASS_CTB_PADS7_PORT 9u 454 #define PASS_CTB_PADS7_PIN 7u 455 #define PASS_SARMUX_PADS0_PORT 10u 456 #define PASS_SARMUX_PADS0_PIN 0u 457 #define PASS_SARMUX_PADS1_PORT 10u 458 #define PASS_SARMUX_PADS1_PIN 1u 459 #define PASS_SARMUX_PADS2_PORT 10u 460 #define PASS_SARMUX_PADS2_PIN 2u 461 #define PASS_SARMUX_PADS3_PORT 10u 462 #define PASS_SARMUX_PADS3_PIN 3u 463 #define PASS_SARMUX_PADS4_PORT 10u 464 #define PASS_SARMUX_PADS4_PIN 4u 465 #define PASS_SARMUX_PADS5_PORT 10u 466 #define PASS_SARMUX_PADS5_PIN 5u 467 #define PASS_SARMUX_PADS6_PORT 10u 468 #define PASS_SARMUX_PADS6_PIN 6u 469 #define SRSS_ADFT_PIN0_PORT 10u 470 #define SRSS_ADFT_PIN0_PIN 0u 471 #define SRSS_ADFT_PIN1_PORT 10u 472 #define SRSS_ADFT_PIN1_PIN 1u 473 #define SRSS_ECO_IN_PORT 12u 474 #define SRSS_ECO_IN_PIN 6u 475 #define SRSS_ECO_OUT_PORT 12u 476 #define SRSS_ECO_OUT_PIN 7u 477 #define SRSS_WCO_IN_PORT 0u 478 #define SRSS_WCO_IN_PIN 0u 479 #define SRSS_WCO_OUT_PORT 0u 480 #define SRSS_WCO_OUT_PIN 1u 481 482 /* HSIOM Connections */ 483 typedef enum 484 { 485 /* Generic HSIOM connections */ 486 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 487 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 488 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 489 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 490 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 491 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 492 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 493 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 494 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 495 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 496 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 497 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 498 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 499 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 500 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 501 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 502 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 503 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 504 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 505 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 506 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 507 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 508 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 509 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 510 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 511 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 512 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 513 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 514 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 515 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 516 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 517 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 518 519 /* P0.0 */ 520 P0_0_GPIO = 0, /* GPIO controls 'out' */ 521 P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 522 P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 523 P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 524 P0_0_AMUXA = 4, /* Analog mux bus A */ 525 P0_0_AMUXB = 5, /* Analog mux bus B */ 526 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 527 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 528 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 529 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 530 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 531 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 532 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 533 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 534 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 535 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 536 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 537 538 /* P0.1 */ 539 P0_1_GPIO = 0, /* GPIO controls 'out' */ 540 P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 541 P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 542 P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 543 P0_1_AMUXA = 4, /* Analog mux bus A */ 544 P0_1_AMUXB = 5, /* Analog mux bus B */ 545 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 546 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 547 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 548 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 549 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 550 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 551 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 552 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 553 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 554 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 555 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 556 557 /* P0.2 */ 558 P0_2_GPIO = 0, /* GPIO controls 'out' */ 559 P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 560 P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 561 P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 562 P0_2_AMUXA = 4, /* Analog mux bus A */ 563 P0_2_AMUXB = 5, /* Analog mux bus B */ 564 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 565 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 566 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 567 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 568 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 569 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 570 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 571 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 572 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 573 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 574 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 575 576 /* P0.3 */ 577 P0_3_GPIO = 0, /* GPIO controls 'out' */ 578 P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 579 P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 580 P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 581 P0_3_AMUXA = 4, /* Analog mux bus A */ 582 P0_3_AMUXB = 5, /* Analog mux bus B */ 583 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 584 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 585 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 586 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 587 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 588 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 589 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 590 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 591 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 592 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 593 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 594 595 /* P0.4 */ 596 P0_4_GPIO = 0, /* GPIO controls 'out' */ 597 P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 598 P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 599 P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 600 P0_4_AMUXA = 4, /* Analog mux bus A */ 601 P0_4_AMUXB = 5, /* Analog mux bus B */ 602 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 603 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 604 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 605 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 606 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 607 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 608 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 609 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 610 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 611 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 612 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 613 614 /* P0.5 */ 615 P0_5_GPIO = 0, /* GPIO controls 'out' */ 616 P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 617 P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 618 P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 619 P0_5_AMUXA = 4, /* Analog mux bus A */ 620 P0_5_AMUXB = 5, /* Analog mux bus B */ 621 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 622 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 623 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 624 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 625 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 626 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 627 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 628 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 629 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 630 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 631 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 632 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 633 634 /* P1.0 */ 635 P1_0_GPIO = 0, /* GPIO controls 'out' */ 636 P1_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 637 P1_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 638 P1_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 639 P1_0_AMUXA = 4, /* Analog mux bus A */ 640 P1_0_AMUXB = 5, /* Analog mux bus B */ 641 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 642 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 643 P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 644 P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 645 P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 646 P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 647 P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 648 P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 649 P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ 650 P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ 651 P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ 652 P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 653 654 /* P1.1 */ 655 P1_1_GPIO = 0, /* GPIO controls 'out' */ 656 P1_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 657 P1_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 658 P1_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 659 P1_1_AMUXA = 4, /* Analog mux bus A */ 660 P1_1_AMUXB = 5, /* Analog mux bus B */ 661 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 662 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 663 P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 664 P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 665 P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 666 P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 667 P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 668 P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 669 P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ 670 P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ 671 P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ 672 P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 673 674 /* P1.2 */ 675 P1_2_GPIO = 0, /* GPIO controls 'out' */ 676 P1_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 677 P1_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 678 P1_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 679 P1_2_AMUXA = 4, /* Analog mux bus A */ 680 P1_2_AMUXB = 5, /* Analog mux bus B */ 681 P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 682 P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 683 P1_2_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:4 */ 684 P1_2_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:1 */ 685 P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ 686 P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ 687 P1_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 688 P1_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 689 P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */ 690 P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */ 691 692 /* P1.3 */ 693 P1_3_GPIO = 0, /* GPIO controls 'out' */ 694 P1_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 695 P1_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 696 P1_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 697 P1_3_AMUXA = 4, /* Analog mux bus A */ 698 P1_3_AMUXB = 5, /* Analog mux bus B */ 699 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 700 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 701 P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */ 702 P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ 703 P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 704 P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 705 P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 706 P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 707 P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */ 708 P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */ 709 710 /* P1.4 */ 711 P1_4_GPIO = 0, /* GPIO controls 'out' */ 712 P1_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 713 P1_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 714 P1_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 715 P1_4_AMUXA = 4, /* Analog mux bus A */ 716 P1_4_AMUXB = 5, /* Analog mux bus B */ 717 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 718 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 719 P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ 720 P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ 721 P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 722 P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 723 P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 724 P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 725 P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ 726 727 /* P1.5 */ 728 P1_5_GPIO = 0, /* GPIO controls 'out' */ 729 P1_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 730 P1_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 731 P1_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 732 P1_5_AMUXA = 4, /* Analog mux bus A */ 733 P1_5_AMUXB = 5, /* Analog mux bus B */ 734 P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 735 P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 736 P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ 737 P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 738 P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 739 P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 740 P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 741 P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 742 P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ 743 744 /* P5.0 */ 745 P5_0_GPIO = 0, /* GPIO controls 'out' */ 746 P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 747 P5_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 748 P5_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 749 P5_0_AMUXA = 4, /* Analog mux bus A */ 750 P5_0_AMUXB = 5, /* Analog mux bus B */ 751 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 752 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 753 P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 754 P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 755 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 756 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 757 P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 758 P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 759 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 760 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 761 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 762 P5_0_AUDIOSS_CLK_I2S_IF = 22, /* Digital Active - audioss.clk_i2s_if */ 763 P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */ 764 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 765 766 /* P5.1 */ 767 P5_1_GPIO = 0, /* GPIO controls 'out' */ 768 P5_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 769 P5_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 770 P5_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 771 P5_1_AMUXA = 4, /* Analog mux bus A */ 772 P5_1_AMUXB = 5, /* Analog mux bus B */ 773 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 774 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 775 P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 776 P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 777 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 778 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 779 P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 780 P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 781 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 782 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 783 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 784 P5_1_AUDIOSS_TX_SCK = 22, /* Digital Active - audioss.tx_sck */ 785 P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */ 786 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 787 788 /* P5.2 */ 789 P5_2_GPIO = 0, /* GPIO controls 'out' */ 790 P5_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 791 P5_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 792 P5_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 793 P5_2_AMUXA = 4, /* Analog mux bus A */ 794 P5_2_AMUXB = 5, /* Analog mux bus B */ 795 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 796 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 797 P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 798 P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 799 P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 800 P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 801 P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 802 P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 803 P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 804 P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 805 P5_2_AUDIOSS_TX_WS = 22, /* Digital Active - audioss.tx_ws */ 806 P5_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:0 */ 807 808 /* P5.3 */ 809 P5_3_GPIO = 0, /* GPIO controls 'out' */ 810 P5_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 811 P5_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 812 P5_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 813 P5_3_AMUXA = 4, /* Analog mux bus A */ 814 P5_3_AMUXB = 5, /* Analog mux bus B */ 815 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 816 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 817 P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ 818 P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 819 P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 820 P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 821 P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ 822 P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ 823 P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 824 P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 825 P5_3_AUDIOSS_TX_SDO = 22, /* Digital Active - audioss.tx_sdo */ 826 P5_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:0 */ 827 828 /* P5.4 */ 829 P5_4_GPIO = 0, /* GPIO controls 'out' */ 830 P5_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 831 P5_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 832 P5_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 833 P5_4_AMUXA = 4, /* Analog mux bus A */ 834 P5_4_AMUXB = 5, /* Analog mux bus B */ 835 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 836 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 837 P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ 838 P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 839 P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ 840 P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ 841 P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ 842 P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ 843 P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 844 P5_4_AUDIOSS_RX_SCK = 22, /* Digital Active - audioss.rx_sck */ 845 P5_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:0 */ 846 847 /* P5.5 */ 848 P5_5_GPIO = 0, /* GPIO controls 'out' */ 849 P5_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 850 P5_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 851 P5_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 852 P5_5_AMUXA = 4, /* Analog mux bus A */ 853 P5_5_AMUXB = 5, /* Analog mux bus B */ 854 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 855 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 856 P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ 857 P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 858 P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 859 P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 860 P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 861 P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 862 P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 863 P5_5_AUDIOSS_RX_WS = 22, /* Digital Active - audioss.rx_ws */ 864 P5_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:0 */ 865 866 /* P5.6 */ 867 P5_6_GPIO = 0, /* GPIO controls 'out' */ 868 P5_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 869 P5_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 870 P5_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 871 P5_6_AMUXA = 4, /* Analog mux bus A */ 872 P5_6_AMUXB = 5, /* Analog mux bus B */ 873 P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 874 P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 875 P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 876 P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 877 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 878 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 879 P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 880 P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 881 P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 882 P5_6_AUDIOSS_RX_SDI = 22, /* Digital Active - audioss.rx_sdi */ 883 P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */ 884 885 /* P6.0 */ 886 P6_0_GPIO = 0, /* GPIO controls 'out' */ 887 P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 888 P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 889 P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 890 P6_0_AMUXA = 4, /* Analog mux bus A */ 891 P6_0_AMUXB = 5, /* Analog mux bus B */ 892 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 893 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 894 P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 895 P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ 896 P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 897 P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 898 P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ 899 P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ 900 P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ 901 P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 902 P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 903 P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ 904 P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 905 P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ 906 907 /* P6.1 */ 908 P6_1_GPIO = 0, /* GPIO controls 'out' */ 909 P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 910 P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 911 P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 912 P6_1_AMUXA = 4, /* Analog mux bus A */ 913 P6_1_AMUXB = 5, /* Analog mux bus B */ 914 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 915 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 916 P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 917 P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 918 P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 919 P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 920 P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ 921 P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ 922 P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ 923 P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 924 P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 925 P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ 926 P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 927 P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ 928 929 /* P6.2 */ 930 P6_2_GPIO = 0, /* GPIO controls 'out' */ 931 P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 932 P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 933 P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 934 P6_2_AMUXA = 4, /* Analog mux bus A */ 935 P6_2_AMUXB = 5, /* Analog mux bus B */ 936 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 937 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 938 P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 939 P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ 940 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 941 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 942 P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 943 P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 944 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 945 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 946 P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ 947 948 /* P6.3 */ 949 P6_3_GPIO = 0, /* GPIO controls 'out' */ 950 P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 951 P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 952 P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 953 P6_3_AMUXA = 4, /* Analog mux bus A */ 954 P6_3_AMUXB = 5, /* Analog mux bus B */ 955 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 956 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 957 P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 958 P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 959 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 960 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 961 P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 962 P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 963 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 964 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 965 P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ 966 967 /* P6.4 */ 968 P6_4_GPIO = 0, /* GPIO controls 'out' */ 969 P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 970 P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 971 P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 972 P6_4_AMUXA = 4, /* Analog mux bus A */ 973 P6_4_AMUXB = 5, /* Analog mux bus B */ 974 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 975 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 976 P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 977 P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ 978 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 979 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 980 P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 981 P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 982 P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ 983 P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ 984 P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ 985 P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ 986 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 987 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 988 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 989 P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ 990 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 991 992 /* P6.5 */ 993 P6_5_GPIO = 0, /* GPIO controls 'out' */ 994 P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 995 P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 996 P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 997 P6_5_AMUXA = 4, /* Analog mux bus A */ 998 P6_5_AMUXB = 5, /* Analog mux bus B */ 999 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1000 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1001 P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 1002 P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 1003 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 1004 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 1005 P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 1006 P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 1007 P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ 1008 P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ 1009 P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ 1010 P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ 1011 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 1012 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 1013 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 1014 P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ 1015 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1016 1017 /* P6.6 */ 1018 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1019 P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1020 P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1021 P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1022 P6_6_AMUXA = 4, /* Analog mux bus A */ 1023 P6_6_AMUXB = 5, /* Analog mux bus B */ 1024 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1025 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1026 P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 1027 P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ 1028 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 1029 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 1030 P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 1031 P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 1032 P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ 1033 P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ 1034 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 1035 P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ 1036 1037 /* P6.7 */ 1038 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1039 P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1040 P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1041 P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1042 P6_7_AMUXA = 4, /* Analog mux bus A */ 1043 P6_7_AMUXB = 5, /* Analog mux bus B */ 1044 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1045 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1046 P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 1047 P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 1048 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 1049 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 1050 P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 1051 P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 1052 P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ 1053 P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ 1054 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 1055 P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ 1056 1057 /* P7.0 */ 1058 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1059 P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1060 P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1061 P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1062 P7_0_AMUXA = 4, /* Analog mux bus A */ 1063 P7_0_AMUXB = 5, /* Analog mux bus B */ 1064 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1065 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1066 P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 1067 P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ 1068 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 1069 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 1070 P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 1071 P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 1072 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 1073 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 1074 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 1075 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 1076 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 1077 1078 /* P7.1 */ 1079 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1080 P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1081 P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1082 P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1083 P7_1_AMUXA = 4, /* Analog mux bus A */ 1084 P7_1_AMUXB = 5, /* Analog mux bus B */ 1085 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1086 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1087 P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 1088 P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1089 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1090 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1091 P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1092 P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1093 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 1094 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 1095 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 1096 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 1097 1098 /* P7.2 */ 1099 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1100 P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1101 P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1102 P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1103 P7_2_AMUXA = 4, /* Analog mux bus A */ 1104 P7_2_AMUXB = 5, /* Analog mux bus B */ 1105 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1106 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1107 P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 1108 P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ 1109 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1110 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1111 P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1112 P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1113 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 1114 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 1115 1116 /* P7.3 */ 1117 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1118 P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1119 P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1120 P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1121 P7_3_AMUXA = 4, /* Analog mux bus A */ 1122 P7_3_AMUXB = 5, /* Analog mux bus B */ 1123 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1124 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1125 P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 1126 P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1127 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1128 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1129 P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1130 P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1131 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 1132 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 1133 1134 /* P7.4 */ 1135 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1136 P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1137 P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1138 P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1139 P7_4_AMUXA = 4, /* Analog mux bus A */ 1140 P7_4_AMUXB = 5, /* Analog mux bus B */ 1141 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1142 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1143 P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 1144 P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ 1145 P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ 1146 P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ 1147 P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ 1148 P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ 1149 P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ 1150 P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */ 1151 P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 1152 1153 /* P7.5 */ 1154 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1155 P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1156 P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1157 P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1158 P7_5_AMUXA = 4, /* Analog mux bus A */ 1159 P7_5_AMUXB = 5, /* Analog mux bus B */ 1160 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1161 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1162 P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 1163 P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ 1164 P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ 1165 P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ 1166 P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ 1167 P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ 1168 P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ 1169 P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */ 1170 P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ 1171 1172 /* P7.6 */ 1173 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1174 P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1175 P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1176 P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1177 P7_6_AMUXA = 4, /* Analog mux bus A */ 1178 P7_6_AMUXB = 5, /* Analog mux bus B */ 1179 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1180 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1181 P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 1182 P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ 1183 P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 1184 P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 1185 P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ 1186 P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ 1187 P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ 1188 P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */ 1189 P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ 1190 1191 /* P7.7 */ 1192 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1193 P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1194 P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1195 P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1196 P7_7_AMUXA = 4, /* Analog mux bus A */ 1197 P7_7_AMUXB = 5, /* Analog mux bus B */ 1198 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1199 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1200 P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 1201 P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 1202 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1203 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1204 P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1205 P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1206 P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ 1207 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 1208 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 1209 1210 /* P8.0 */ 1211 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1212 P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1213 P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1214 P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1215 P8_0_AMUXA = 4, /* Analog mux bus A */ 1216 P8_0_AMUXB = 5, /* Analog mux bus B */ 1217 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1218 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1219 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 1220 P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ 1221 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1222 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1223 P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1224 P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1225 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 1226 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 1227 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 1228 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 1229 1230 /* P8.1 */ 1231 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1232 P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1233 P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1234 P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1235 P8_1_AMUXA = 4, /* Analog mux bus A */ 1236 P8_1_AMUXB = 5, /* Analog mux bus B */ 1237 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1238 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1239 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 1240 P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 1241 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1242 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1243 P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1244 P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1245 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 1246 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 1247 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 1248 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 1249 1250 /* P8.2 */ 1251 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1252 P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1253 P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1254 P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1255 P8_2_AMUXA = 4, /* Analog mux bus A */ 1256 P8_2_AMUXB = 5, /* Analog mux bus B */ 1257 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1258 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1259 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 1260 P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ 1261 P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1262 P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1263 P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1264 P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1265 P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 1266 P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 1267 P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 1268 1269 /* P8.3 */ 1270 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1271 P8_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1272 P8_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1273 P8_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1274 P8_3_AMUXA = 4, /* Analog mux bus A */ 1275 P8_3_AMUXB = 5, /* Analog mux bus B */ 1276 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1277 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1278 P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 1279 P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 1280 P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1281 P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1282 P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1283 P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1284 P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 1285 P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 1286 P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 1287 1288 /* P8.4 */ 1289 P8_4_GPIO = 0, /* GPIO controls 'out' */ 1290 P8_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1291 P8_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1292 P8_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1293 P8_4_AMUXA = 4, /* Analog mux bus A */ 1294 P8_4_AMUXB = 5, /* Analog mux bus B */ 1295 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1296 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1297 P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 1298 P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ 1299 P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1300 P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1301 P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1302 P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1303 P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ 1304 1305 /* P8.5 */ 1306 P8_5_GPIO = 0, /* GPIO controls 'out' */ 1307 P8_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1308 P8_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1309 P8_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1310 P8_5_AMUXA = 4, /* Analog mux bus A */ 1311 P8_5_AMUXB = 5, /* Analog mux bus B */ 1312 P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1313 P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1314 P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ 1315 P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ 1316 P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1317 P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1318 P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1319 P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1320 P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */ 1321 1322 /* P8.6 */ 1323 P8_6_GPIO = 0, /* GPIO controls 'out' */ 1324 P8_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1325 P8_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1326 P8_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1327 P8_6_AMUXA = 4, /* Analog mux bus A */ 1328 P8_6_AMUXB = 5, /* Analog mux bus B */ 1329 P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1330 P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1331 P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 1332 P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */ 1333 P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ 1334 P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ 1335 P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */ 1336 P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */ 1337 P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */ 1338 1339 /* P8.7 */ 1340 P8_7_GPIO = 0, /* GPIO controls 'out' */ 1341 P8_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1342 P8_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1343 P8_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1344 P8_7_AMUXA = 4, /* Analog mux bus A */ 1345 P8_7_AMUXB = 5, /* Analog mux bus B */ 1346 P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1347 P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1348 P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 1349 P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ 1350 P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ 1351 P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ 1352 P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */ 1353 P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */ 1354 P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */ 1355 1356 /* P9.0 */ 1357 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1358 P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1359 P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1360 P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1361 P9_0_AMUXA = 4, /* Analog mux bus A */ 1362 P9_0_AMUXB = 5, /* Analog mux bus B */ 1363 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1364 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1365 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ 1366 P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ 1367 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1368 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1369 P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 1370 P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 1371 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 1372 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 1373 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 1374 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 1375 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1376 1377 /* P9.1 */ 1378 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1379 P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1380 P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1381 P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1382 P9_1_AMUXA = 4, /* Analog mux bus A */ 1383 P9_1_AMUXB = 5, /* Analog mux bus B */ 1384 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1385 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1386 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ 1387 P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 1388 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1389 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1390 P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 1391 P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 1392 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 1393 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 1394 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 1395 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 1396 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1397 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1398 1399 /* P9.2 */ 1400 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1401 P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1402 P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1403 P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1404 P9_2_AMUXA = 4, /* Analog mux bus A */ 1405 P9_2_AMUXB = 5, /* Analog mux bus B */ 1406 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1407 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1408 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ 1409 P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ 1410 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ 1411 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ 1412 P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1413 P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1414 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 1415 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 1416 P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ 1417 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1418 1419 /* P9.3 */ 1420 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1421 P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1422 P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1423 P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1424 P9_3_AMUXA = 4, /* Analog mux bus A */ 1425 P9_3_AMUXB = 5, /* Analog mux bus B */ 1426 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1427 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1428 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ 1429 P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 1430 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ 1431 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ 1432 P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1433 P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1434 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1435 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1436 P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ 1437 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1438 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1439 1440 /* P9.4 */ 1441 P9_4_GPIO = 0, /* GPIO controls 'out' */ 1442 P9_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1443 P9_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1444 P9_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1445 P9_4_AMUXA = 4, /* Analog mux bus A */ 1446 P9_4_AMUXB = 5, /* Analog mux bus B */ 1447 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1448 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1449 P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */ 1450 P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ 1451 P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */ 1452 P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */ 1453 P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */ 1454 P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */ 1455 P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ 1456 1457 /* P9.5 */ 1458 P9_5_GPIO = 0, /* GPIO controls 'out' */ 1459 P9_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1460 P9_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1461 P9_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1462 P9_5_AMUXA = 4, /* Analog mux bus A */ 1463 P9_5_AMUXB = 5, /* Analog mux bus B */ 1464 P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1465 P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1466 P9_5_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:5 */ 1467 P9_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */ 1468 P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:67 */ 1469 P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:67 */ 1470 P9_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:1 */ 1471 P9_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:1 */ 1472 P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */ 1473 1474 /* P9.6 */ 1475 P9_6_GPIO = 0, /* GPIO controls 'out' */ 1476 P9_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1477 P9_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1478 P9_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1479 P9_6_AMUXA = 4, /* Analog mux bus A */ 1480 P9_6_AMUXB = 5, /* Analog mux bus B */ 1481 P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1482 P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1483 P9_6_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 1484 P9_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */ 1485 P9_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:68 */ 1486 P9_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:68 */ 1487 P9_6_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:1 */ 1488 P9_6_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:1 */ 1489 P9_6_SCB2_SPI_SELECT3 = 20, /* Digital Active - scb[2].spi_select3:0 */ 1490 1491 /* P9.7 */ 1492 P9_7_GPIO = 0, /* GPIO controls 'out' */ 1493 P9_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1494 P9_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1495 P9_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1496 P9_7_AMUXA = 4, /* Analog mux bus A */ 1497 P9_7_AMUXB = 5, /* Analog mux bus B */ 1498 P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1499 P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1500 P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1501 P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ 1502 P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */ 1503 P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */ 1504 P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */ 1505 P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */ 1506 1507 /* P10.0 */ 1508 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1509 P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1510 P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1511 P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1512 P10_0_AMUXA = 4, /* Analog mux bus A */ 1513 P10_0_AMUXB = 5, /* Analog mux bus B */ 1514 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1515 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1516 P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ 1517 P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ 1518 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ 1519 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ 1520 P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ 1521 P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ 1522 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 1523 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 1524 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 1525 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1526 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1527 1528 /* P10.1 */ 1529 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1530 P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1531 P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1532 P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1533 P10_1_AMUXA = 4, /* Analog mux bus A */ 1534 P10_1_AMUXB = 5, /* Analog mux bus B */ 1535 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1536 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1537 P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ 1538 P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 1539 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ 1540 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ 1541 P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ 1542 P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ 1543 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 1544 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 1545 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 1546 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1547 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1548 1549 /* P10.2 */ 1550 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1551 P10_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1552 P10_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1553 P10_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1554 P10_2_AMUXA = 4, /* Analog mux bus A */ 1555 P10_2_AMUXB = 5, /* Analog mux bus B */ 1556 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1557 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1558 P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ 1559 P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ 1560 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ 1561 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ 1562 P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ 1563 P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ 1564 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 1565 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 1566 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1567 1568 /* P10.3 */ 1569 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1570 P10_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1571 P10_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1572 P10_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1573 P10_3_AMUXA = 4, /* Analog mux bus A */ 1574 P10_3_AMUXB = 5, /* Analog mux bus B */ 1575 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1576 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1577 P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ 1578 P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 1579 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ 1580 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ 1581 P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ 1582 P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ 1583 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 1584 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 1585 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1586 1587 /* P10.4 */ 1588 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1589 P10_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1590 P10_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1591 P10_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1592 P10_4_AMUXA = 4, /* Analog mux bus A */ 1593 P10_4_AMUXB = 5, /* Analog mux bus B */ 1594 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1595 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1596 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 1597 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 1598 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ 1599 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ 1600 P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ 1601 P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ 1602 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 1603 P10_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:0 */ 1604 P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0:0 */ 1605 1606 /* P10.5 */ 1607 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1608 P10_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1609 P10_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1610 P10_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1611 P10_5_AMUXA = 4, /* Analog mux bus A */ 1612 P10_5_AMUXB = 5, /* Analog mux bus B */ 1613 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1614 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1615 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 1616 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1617 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ 1618 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ 1619 P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ 1620 P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ 1621 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 1622 P10_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:0 */ 1623 P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0:0 */ 1624 1625 /* P10.6 */ 1626 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1627 P10_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1628 P10_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1629 P10_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1630 P10_6_AMUXA = 4, /* Analog mux bus A */ 1631 P10_6_AMUXB = 5, /* Analog mux bus B */ 1632 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1633 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1634 P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ 1635 P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ 1636 P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */ 1637 P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */ 1638 P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */ 1639 P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */ 1640 P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 1641 1642 /* P11.0 */ 1643 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1644 P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1645 P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1646 P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1647 P11_0_AMUXA = 4, /* Analog mux bus A */ 1648 P11_0_AMUXB = 5, /* Analog mux bus B */ 1649 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1650 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1651 P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 1652 P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 1653 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ 1654 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ 1655 P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ 1656 P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ 1657 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1658 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 1659 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 1660 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 1661 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1662 1663 /* P11.1 */ 1664 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1665 P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1666 P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1667 P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1668 P11_1_AMUXA = 4, /* Analog mux bus A */ 1669 P11_1_AMUXB = 5, /* Analog mux bus B */ 1670 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1671 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1672 P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 1673 P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1674 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ 1675 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ 1676 P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ 1677 P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ 1678 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1679 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 1680 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 1681 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 1682 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1683 1684 /* P11.2 */ 1685 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1686 P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1687 P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1688 P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1689 P11_2_AMUXA = 4, /* Analog mux bus A */ 1690 P11_2_AMUXB = 5, /* Analog mux bus B */ 1691 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1692 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1693 P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 1694 P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 1695 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ 1696 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ 1697 P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ 1698 P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ 1699 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1700 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ 1701 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ 1702 1703 /* P11.3 */ 1704 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1705 P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1706 P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1707 P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1708 P11_3_AMUXA = 4, /* Analog mux bus A */ 1709 P11_3_AMUXB = 5, /* Analog mux bus B */ 1710 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1711 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1712 P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 1713 P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1714 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ 1715 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ 1716 P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ 1717 P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ 1718 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1719 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ 1720 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ 1721 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1722 1723 /* P11.4 */ 1724 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1725 P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1726 P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1727 P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1728 P11_4_AMUXA = 4, /* Analog mux bus A */ 1729 P11_4_AMUXB = 5, /* Analog mux bus B */ 1730 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1731 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1732 P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 1733 P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 1734 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ 1735 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ 1736 P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ 1737 P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ 1738 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1739 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ 1740 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1741 1742 /* P11.5 */ 1743 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1744 P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1745 P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1746 P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1747 P11_5_AMUXA = 4, /* Analog mux bus A */ 1748 P11_5_AMUXB = 5, /* Analog mux bus B */ 1749 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1750 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1751 P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 1752 P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1753 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ 1754 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ 1755 P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ 1756 P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ 1757 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1758 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ 1759 1760 /* P11.6 */ 1761 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1762 P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1763 P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1764 P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1765 P11_6_AMUXA = 4, /* Analog mux bus A */ 1766 P11_6_AMUXB = 5, /* Analog mux bus B */ 1767 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1768 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1769 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ 1770 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ 1771 P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ 1772 P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ 1773 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1774 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ 1775 1776 /* P11.7 */ 1777 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1778 P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1779 P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1780 P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1781 P11_7_AMUXA = 4, /* Analog mux bus A */ 1782 P11_7_AMUXB = 5, /* Analog mux bus B */ 1783 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1784 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1785 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1786 1787 /* P12.0 */ 1788 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1789 P12_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1790 P12_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1791 P12_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1792 P12_0_AMUXA = 4, /* Analog mux bus A */ 1793 P12_0_AMUXB = 5, /* Analog mux bus B */ 1794 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1795 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1796 P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ 1797 P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 1798 P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ 1799 P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ 1800 P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ 1801 P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ 1802 P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ 1803 P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ 1804 P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ 1805 P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ 1806 P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 1807 1808 /* P12.1 */ 1809 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1810 P12_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1811 P12_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1812 P12_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1813 P12_1_AMUXA = 4, /* Analog mux bus A */ 1814 P12_1_AMUXB = 5, /* Analog mux bus B */ 1815 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1816 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1817 P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ 1818 P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 1819 P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ 1820 P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ 1821 P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ 1822 P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ 1823 P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ 1824 P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ 1825 P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ 1826 P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ 1827 P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 1828 1829 /* P12.2 */ 1830 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1831 P12_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1832 P12_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1833 P12_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1834 P12_2_AMUXA = 4, /* Analog mux bus A */ 1835 P12_2_AMUXB = 5, /* Analog mux bus B */ 1836 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1837 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1838 P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ 1839 P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 1840 P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ 1841 P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ 1842 P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ 1843 P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ 1844 P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ 1845 P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ 1846 P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ 1847 1848 /* P12.3 */ 1849 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1850 P12_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1851 P12_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1852 P12_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1853 P12_3_AMUXA = 4, /* Analog mux bus A */ 1854 P12_3_AMUXB = 5, /* Analog mux bus B */ 1855 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1856 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1857 P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ 1858 P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 1859 P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ 1860 P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ 1861 P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ 1862 P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ 1863 P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ 1864 P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ 1865 P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ 1866 1867 /* P12.4 */ 1868 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1869 P12_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1870 P12_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1871 P12_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1872 P12_4_AMUXA = 4, /* Analog mux bus A */ 1873 P12_4_AMUXB = 5, /* Analog mux bus B */ 1874 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1875 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1876 P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ 1877 P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 1878 P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ 1879 P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ 1880 P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ 1881 P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ 1882 P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ 1883 P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ 1884 P12_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:1 */ 1885 P12_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:1:0 */ 1886 1887 /* P12.5 */ 1888 P12_5_GPIO = 0, /* GPIO controls 'out' */ 1889 P12_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1890 P12_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1891 P12_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1892 P12_5_AMUXA = 4, /* Analog mux bus A */ 1893 P12_5_AMUXB = 5, /* Analog mux bus B */ 1894 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1895 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1896 P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */ 1897 P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 1898 P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */ 1899 P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */ 1900 P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */ 1901 P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */ 1902 P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ 1903 P12_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:1 */ 1904 P12_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:1:0 */ 1905 1906 /* P12.6 */ 1907 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1908 P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1909 P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1910 P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1911 P12_6_AMUXA = 4, /* Analog mux bus A */ 1912 P12_6_AMUXB = 5, /* Analog mux bus B */ 1913 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1914 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1915 P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ 1916 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 1917 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ 1918 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ 1919 P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ 1920 P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ 1921 P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 1922 1923 /* P12.7 */ 1924 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1925 P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1926 P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1927 P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1928 P12_7_AMUXA = 4, /* Analog mux bus A */ 1929 P12_7_AMUXB = 5, /* Analog mux bus B */ 1930 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1931 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1932 P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ 1933 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 1934 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ 1935 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ 1936 P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ 1937 P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ 1938 1939 /* P13.0 */ 1940 P13_0_GPIO = 0, /* GPIO controls 'out' */ 1941 P13_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1942 P13_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1943 P13_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1944 P13_0_AMUXA = 4, /* Analog mux bus A */ 1945 P13_0_AMUXB = 5, /* Analog mux bus B */ 1946 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1947 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1948 P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 1949 P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */ 1950 P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */ 1951 P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */ 1952 P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */ 1953 P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */ 1954 P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ 1955 P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ 1956 P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */ 1957 P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */ 1958 1959 /* P13.1 */ 1960 P13_1_GPIO = 0, /* GPIO controls 'out' */ 1961 P13_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1962 P13_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1963 P13_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1964 P13_1_AMUXA = 4, /* Analog mux bus A */ 1965 P13_1_AMUXB = 5, /* Analog mux bus B */ 1966 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1967 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1968 P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 1969 P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ 1970 P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */ 1971 P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */ 1972 P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */ 1973 P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */ 1974 P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ 1975 P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ 1976 P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ 1977 P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ 1978 1979 /* P13.6 */ 1980 P13_6_GPIO = 0, /* GPIO controls 'out' */ 1981 P13_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1982 P13_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1983 P13_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1984 P13_6_AMUXA = 4, /* Analog mux bus A */ 1985 P13_6_AMUXB = 5, /* Analog mux bus B */ 1986 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1987 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1988 P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ 1989 P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */ 1990 P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */ 1991 P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */ 1992 P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */ 1993 P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */ 1994 P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */ 1995 1996 /* P13.7 */ 1997 P13_7_GPIO = 0, /* GPIO controls 'out' */ 1998 P13_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1999 P13_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 2000 P13_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 2001 P13_7_AMUXA = 4, /* Analog mux bus A */ 2002 P13_7_AMUXB = 5, /* Analog mux bus B */ 2003 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2004 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2005 P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ 2006 P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ 2007 P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ 2008 P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ 2009 P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ 2010 P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ 2011 } en_hsiom_sel_t; 2012 2013 #endif /* _GPIO_PSOC6_01_116_BGA_BLE_H_ */ 2014 2015 2016 /* [] END OF FILE */ 2017
