1 /***************************************************************************//** 2 * \file gpio_psoc6_01_104_m_csp_ble.h 3 * 4 * \brief 5 * PSoC6_01 device GPIO header for 104-M-CSP-BLE package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_01_104_M_CSP_BLE_H_ 28 #define _GPIO_PSOC6_01_104_M_CSP_BLE_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_CSP 44 #define CY_GPIO_PIN_COUNT 104u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ADFT0_VDDD, 50 AMUXBUS_ADFT1_VDDD, 51 AMUXBUS_ANALOG_VDDA, 52 AMUXBUS_ANALOG_VDDD, 53 AMUXBUS_CSD0, 54 AMUXBUS_CSD1, 55 AMUXBUS_MAIN, 56 AMUXBUS_NOISY, 57 AMUXBUS_SAR, 58 AMUXBUS_VDDIO_1, 59 }; 60 61 /* AMUX Splitter Controls */ 62 typedef enum 63 { 64 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ 65 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ 66 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ 67 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ 68 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 69 AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 70 AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 71 AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ 72 AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ 73 } cy_en_amux_split_t; 74 75 /* Port List */ 76 /* PORT 0 (GPIO) */ 77 #define P0_0_PORT GPIO_PRT0 78 #define P0_0_PIN 0u 79 #define P0_0_NUM 0u 80 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 81 #define P0_1_PORT GPIO_PRT0 82 #define P0_1_PIN 1u 83 #define P0_1_NUM 1u 84 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 85 #define P0_2_PORT GPIO_PRT0 86 #define P0_2_PIN 2u 87 #define P0_2_NUM 2u 88 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 89 #define P0_3_PORT GPIO_PRT0 90 #define P0_3_PIN 3u 91 #define P0_3_NUM 3u 92 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 93 #define P0_4_PORT GPIO_PRT0 94 #define P0_4_PIN 4u 95 #define P0_4_NUM 4u 96 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 97 #define P0_5_PORT GPIO_PRT0 98 #define P0_5_PIN 5u 99 #define P0_5_NUM 5u 100 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 101 102 /* PORT 1 (GPIO_OVT) */ 103 #define P1_0_PORT GPIO_PRT1 104 #define P1_0_PIN 0u 105 #define P1_0_NUM 0u 106 #define P1_0_AMUXSEGMENT AMUXBUS_NOISY 107 #define P1_1_PORT GPIO_PRT1 108 #define P1_1_PIN 1u 109 #define P1_1_NUM 1u 110 #define P1_1_AMUXSEGMENT AMUXBUS_NOISY 111 #define P1_3_PORT GPIO_PRT1 112 #define P1_3_PIN 3u 113 #define P1_3_NUM 3u 114 #define P1_3_AMUXSEGMENT AMUXBUS_NOISY 115 #define P1_4_PORT GPIO_PRT1 116 #define P1_4_PIN 4u 117 #define P1_4_NUM 4u 118 #define P1_4_AMUXSEGMENT AMUXBUS_NOISY 119 #define P1_5_PORT GPIO_PRT1 120 #define P1_5_PIN 5u 121 #define P1_5_NUM 5u 122 #define P1_5_AMUXSEGMENT AMUXBUS_NOISY 123 124 /* PORT 5 (GPIO) */ 125 #define P5_0_PORT GPIO_PRT5 126 #define P5_0_PIN 0u 127 #define P5_0_NUM 0u 128 #define P5_0_AMUXSEGMENT AMUXBUS_CSD0 129 #define P5_1_PORT GPIO_PRT5 130 #define P5_1_PIN 1u 131 #define P5_1_NUM 1u 132 #define P5_1_AMUXSEGMENT AMUXBUS_CSD0 133 #define P5_2_PORT GPIO_PRT5 134 #define P5_2_PIN 2u 135 #define P5_2_NUM 2u 136 #define P5_2_AMUXSEGMENT AMUXBUS_CSD0 137 #define P5_3_PORT GPIO_PRT5 138 #define P5_3_PIN 3u 139 #define P5_3_NUM 3u 140 #define P5_3_AMUXSEGMENT AMUXBUS_CSD0 141 #define P5_4_PORT GPIO_PRT5 142 #define P5_4_PIN 4u 143 #define P5_4_NUM 4u 144 #define P5_4_AMUXSEGMENT AMUXBUS_CSD0 145 #define P5_5_PORT GPIO_PRT5 146 #define P5_5_PIN 5u 147 #define P5_5_NUM 5u 148 #define P5_5_AMUXSEGMENT AMUXBUS_CSD0 149 #define P5_6_PORT GPIO_PRT5 150 #define P5_6_PIN 6u 151 #define P5_6_NUM 6u 152 #define P5_6_AMUXSEGMENT AMUXBUS_CSD0 153 #define P5_7_PORT GPIO_PRT5 154 #define P5_7_PIN 7u 155 #define P5_7_NUM 7u 156 #define P5_7_AMUXSEGMENT AMUXBUS_CSD0 157 158 /* PORT 6 (GPIO) */ 159 #define P6_0_PORT GPIO_PRT6 160 #define P6_0_PIN 0u 161 #define P6_0_NUM 0u 162 #define P6_0_AMUXSEGMENT AMUXBUS_CSD0 163 #define P6_1_PORT GPIO_PRT6 164 #define P6_1_PIN 1u 165 #define P6_1_NUM 1u 166 #define P6_1_AMUXSEGMENT AMUXBUS_CSD0 167 #define P6_2_PORT GPIO_PRT6 168 #define P6_2_PIN 2u 169 #define P6_2_NUM 2u 170 #define P6_2_AMUXSEGMENT AMUXBUS_CSD0 171 #define P6_3_PORT GPIO_PRT6 172 #define P6_3_PIN 3u 173 #define P6_3_NUM 3u 174 #define P6_3_AMUXSEGMENT AMUXBUS_CSD0 175 #define P6_4_PORT GPIO_PRT6 176 #define P6_4_PIN 4u 177 #define P6_4_NUM 4u 178 #define P6_4_AMUXSEGMENT AMUXBUS_CSD0 179 #define P6_5_PORT GPIO_PRT6 180 #define P6_5_PIN 5u 181 #define P6_5_NUM 5u 182 #define P6_5_AMUXSEGMENT AMUXBUS_CSD0 183 #define P6_6_PORT GPIO_PRT6 184 #define P6_6_PIN 6u 185 #define P6_6_NUM 6u 186 #define P6_6_AMUXSEGMENT AMUXBUS_CSD0 187 #define P6_7_PORT GPIO_PRT6 188 #define P6_7_PIN 7u 189 #define P6_7_NUM 7u 190 #define P6_7_AMUXSEGMENT AMUXBUS_CSD0 191 192 /* PORT 7 (GPIO) */ 193 #define P7_0_PORT GPIO_PRT7 194 #define P7_0_PIN 0u 195 #define P7_0_NUM 0u 196 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 197 #define P7_1_PORT GPIO_PRT7 198 #define P7_1_PIN 1u 199 #define P7_1_NUM 1u 200 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 201 #define P7_2_PORT GPIO_PRT7 202 #define P7_2_PIN 2u 203 #define P7_2_NUM 2u 204 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 205 #define P7_3_PORT GPIO_PRT7 206 #define P7_3_PIN 3u 207 #define P7_3_NUM 3u 208 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 209 #define P7_4_PORT GPIO_PRT7 210 #define P7_4_PIN 4u 211 #define P7_4_NUM 4u 212 #define P7_4_AMUXSEGMENT AMUXBUS_CSD0 213 #define P7_5_PORT GPIO_PRT7 214 #define P7_5_PIN 5u 215 #define P7_5_NUM 5u 216 #define P7_5_AMUXSEGMENT AMUXBUS_CSD0 217 #define P7_6_PORT GPIO_PRT7 218 #define P7_6_PIN 6u 219 #define P7_6_NUM 6u 220 #define P7_6_AMUXSEGMENT AMUXBUS_CSD0 221 #define P7_7_PORT GPIO_PRT7 222 #define P7_7_PIN 7u 223 #define P7_7_NUM 7u 224 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 225 226 /* PORT 8 (GPIO) */ 227 #define P8_0_PORT GPIO_PRT8 228 #define P8_0_PIN 0u 229 #define P8_0_NUM 0u 230 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 231 #define P8_1_PORT GPIO_PRT8 232 #define P8_1_PIN 1u 233 #define P8_1_NUM 1u 234 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 235 #define P8_2_PORT GPIO_PRT8 236 #define P8_2_PIN 2u 237 #define P8_2_NUM 2u 238 #define P8_2_AMUXSEGMENT AMUXBUS_CSD0 239 #define P8_3_PORT GPIO_PRT8 240 #define P8_3_PIN 3u 241 #define P8_3_NUM 3u 242 #define P8_3_AMUXSEGMENT AMUXBUS_CSD0 243 #define P8_4_PORT GPIO_PRT8 244 #define P8_4_PIN 4u 245 #define P8_4_NUM 4u 246 #define P8_4_AMUXSEGMENT AMUXBUS_CSD0 247 #define P8_5_PORT GPIO_PRT8 248 #define P8_5_PIN 5u 249 #define P8_5_NUM 5u 250 #define P8_5_AMUXSEGMENT AMUXBUS_CSD0 251 #define P8_6_PORT GPIO_PRT8 252 #define P8_6_PIN 6u 253 #define P8_6_NUM 6u 254 #define P8_6_AMUXSEGMENT AMUXBUS_CSD0 255 #define P8_7_PORT GPIO_PRT8 256 #define P8_7_PIN 7u 257 #define P8_7_NUM 7u 258 #define P8_7_AMUXSEGMENT AMUXBUS_CSD0 259 260 /* PORT 9 (GPIO) */ 261 #define P9_0_PORT GPIO_PRT9 262 #define P9_0_PIN 0u 263 #define P9_0_NUM 0u 264 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 265 #define P9_1_PORT GPIO_PRT9 266 #define P9_1_PIN 1u 267 #define P9_1_NUM 1u 268 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 269 #define P9_2_PORT GPIO_PRT9 270 #define P9_2_PIN 2u 271 #define P9_2_NUM 2u 272 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 273 #define P9_3_PORT GPIO_PRT9 274 #define P9_3_PIN 3u 275 #define P9_3_NUM 3u 276 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 277 278 /* PORT 10 (GPIO) */ 279 #define P10_0_PORT GPIO_PRT10 280 #define P10_0_PIN 0u 281 #define P10_0_NUM 0u 282 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 283 #define P10_1_PORT GPIO_PRT10 284 #define P10_1_PIN 1u 285 #define P10_1_NUM 1u 286 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 287 #define P10_2_PORT GPIO_PRT10 288 #define P10_2_PIN 2u 289 #define P10_2_NUM 2u 290 #define P10_2_AMUXSEGMENT AMUXBUS_SAR 291 #define P10_3_PORT GPIO_PRT10 292 #define P10_3_PIN 3u 293 #define P10_3_NUM 3u 294 #define P10_3_AMUXSEGMENT AMUXBUS_SAR 295 #define P10_4_PORT GPIO_PRT10 296 #define P10_4_PIN 4u 297 #define P10_4_NUM 4u 298 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 299 #define P10_5_PORT GPIO_PRT10 300 #define P10_5_PIN 5u 301 #define P10_5_NUM 5u 302 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 303 #define P10_6_PORT GPIO_PRT10 304 #define P10_6_PIN 6u 305 #define P10_6_NUM 6u 306 #define P10_6_AMUXSEGMENT AMUXBUS_SAR 307 #define P10_7_PORT GPIO_PRT10 308 #define P10_7_PIN 7u 309 #define P10_7_NUM 7u 310 #define P10_7_AMUXSEGMENT AMUXBUS_SAR 311 312 /* PORT 11 (GPIO) */ 313 #define P11_0_PORT GPIO_PRT11 314 #define P11_0_PIN 0u 315 #define P11_0_NUM 0u 316 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 317 #define P11_1_PORT GPIO_PRT11 318 #define P11_1_PIN 1u 319 #define P11_1_NUM 1u 320 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 321 #define P11_2_PORT GPIO_PRT11 322 #define P11_2_PIN 2u 323 #define P11_2_NUM 2u 324 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 325 #define P11_3_PORT GPIO_PRT11 326 #define P11_3_PIN 3u 327 #define P11_3_NUM 3u 328 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 329 #define P11_4_PORT GPIO_PRT11 330 #define P11_4_PIN 4u 331 #define P11_4_NUM 4u 332 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 333 #define P11_5_PORT GPIO_PRT11 334 #define P11_5_PIN 5u 335 #define P11_5_NUM 5u 336 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 337 #define P11_6_PORT GPIO_PRT11 338 #define P11_6_PIN 6u 339 #define P11_6_NUM 6u 340 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 341 #define P11_7_PORT GPIO_PRT11 342 #define P11_7_PIN 7u 343 #define P11_7_NUM 7u 344 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 345 346 /* PORT 12 (GPIO) */ 347 #define P12_0_PORT GPIO_PRT12 348 #define P12_0_PIN 0u 349 #define P12_0_NUM 0u 350 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 351 #define P12_1_PORT GPIO_PRT12 352 #define P12_1_PIN 1u 353 #define P12_1_NUM 1u 354 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 355 #define P12_2_PORT GPIO_PRT12 356 #define P12_2_PIN 2u 357 #define P12_2_NUM 2u 358 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 359 #define P12_3_PORT GPIO_PRT12 360 #define P12_3_PIN 3u 361 #define P12_3_NUM 3u 362 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 363 #define P12_4_PORT GPIO_PRT12 364 #define P12_4_PIN 4u 365 #define P12_4_NUM 4u 366 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 367 368 /* PORT 13 (GPIO) */ 369 #define P13_0_PORT GPIO_PRT13 370 #define P13_0_PIN 0u 371 #define P13_0_NUM 0u 372 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 373 #define P13_1_PORT GPIO_PRT13 374 #define P13_1_PIN 1u 375 #define P13_1_NUM 1u 376 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 377 378 /* Analog Connections */ 379 #define CSD_CMODPADD_PORT 7u 380 #define CSD_CMODPADD_PIN 1u 381 #define CSD_CMODPADS_PORT 7u 382 #define CSD_CMODPADS_PIN 1u 383 #define CSD_CSH_TANKPADD_PORT 7u 384 #define CSD_CSH_TANKPADD_PIN 2u 385 #define CSD_CSH_TANKPADS_PORT 7u 386 #define CSD_CSH_TANKPADS_PIN 2u 387 #define CSD_CSHIELDPADS_PORT 7u 388 #define CSD_CSHIELDPADS_PIN 7u 389 #define CSD_VREF_EXT_PORT 7u 390 #define CSD_VREF_EXT_PIN 3u 391 #define IOSS_ADFT0_NET_PORT 10u 392 #define IOSS_ADFT0_NET_PIN 0u 393 #define IOSS_ADFT1_NET_PORT 10u 394 #define IOSS_ADFT1_NET_PIN 1u 395 #define LPCOMP_INN_COMP0_PORT 5u 396 #define LPCOMP_INN_COMP0_PIN 7u 397 #define LPCOMP_INN_COMP1_PORT 6u 398 #define LPCOMP_INN_COMP1_PIN 3u 399 #define LPCOMP_INP_COMP0_PORT 5u 400 #define LPCOMP_INP_COMP0_PIN 6u 401 #define LPCOMP_INP_COMP1_PORT 6u 402 #define LPCOMP_INP_COMP1_PIN 2u 403 #define PASS_CTB_OA0_OUT_10X_PORT 9u 404 #define PASS_CTB_OA0_OUT_10X_PIN 2u 405 #define PASS_CTB_OA1_OUT_10X_PORT 9u 406 #define PASS_CTB_OA1_OUT_10X_PIN 3u 407 #define PASS_CTB_PADS0_PORT 9u 408 #define PASS_CTB_PADS0_PIN 0u 409 #define PASS_CTB_PADS1_PORT 9u 410 #define PASS_CTB_PADS1_PIN 1u 411 #define PASS_CTB_PADS2_PORT 9u 412 #define PASS_CTB_PADS2_PIN 2u 413 #define PASS_CTB_PADS3_PORT 9u 414 #define PASS_CTB_PADS3_PIN 3u 415 #define PASS_SARMUX_PADS0_PORT 10u 416 #define PASS_SARMUX_PADS0_PIN 0u 417 #define PASS_SARMUX_PADS1_PORT 10u 418 #define PASS_SARMUX_PADS1_PIN 1u 419 #define PASS_SARMUX_PADS2_PORT 10u 420 #define PASS_SARMUX_PADS2_PIN 2u 421 #define PASS_SARMUX_PADS3_PORT 10u 422 #define PASS_SARMUX_PADS3_PIN 3u 423 #define PASS_SARMUX_PADS4_PORT 10u 424 #define PASS_SARMUX_PADS4_PIN 4u 425 #define PASS_SARMUX_PADS5_PORT 10u 426 #define PASS_SARMUX_PADS5_PIN 5u 427 #define PASS_SARMUX_PADS6_PORT 10u 428 #define PASS_SARMUX_PADS6_PIN 6u 429 #define PASS_SARMUX_PADS7_PORT 10u 430 #define PASS_SARMUX_PADS7_PIN 7u 431 #define SRSS_ADFT_PIN0_PORT 10u 432 #define SRSS_ADFT_PIN0_PIN 0u 433 #define SRSS_ADFT_PIN1_PORT 10u 434 #define SRSS_ADFT_PIN1_PIN 1u 435 #define SRSS_WCO_IN_PORT 0u 436 #define SRSS_WCO_IN_PIN 0u 437 #define SRSS_WCO_OUT_PORT 0u 438 #define SRSS_WCO_OUT_PIN 1u 439 440 /* HSIOM Connections */ 441 typedef enum 442 { 443 /* Generic HSIOM connections */ 444 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 445 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 446 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 447 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 448 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 449 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 450 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 451 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 452 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 453 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 454 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 455 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 456 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 457 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 458 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 459 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 460 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 461 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 462 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 463 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 464 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 465 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 466 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 467 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 468 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 469 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 470 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 471 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 472 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 473 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 474 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 475 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 476 477 /* P0.0 */ 478 P0_0_GPIO = 0, /* GPIO controls 'out' */ 479 P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 480 P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 481 P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 482 P0_0_AMUXA = 4, /* Analog mux bus A */ 483 P0_0_AMUXB = 5, /* Analog mux bus B */ 484 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 485 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 486 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 487 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 488 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 489 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 490 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 491 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 492 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 493 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 494 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 495 496 /* P0.1 */ 497 P0_1_GPIO = 0, /* GPIO controls 'out' */ 498 P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 499 P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 500 P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 501 P0_1_AMUXA = 4, /* Analog mux bus A */ 502 P0_1_AMUXB = 5, /* Analog mux bus B */ 503 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 504 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 505 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 506 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 507 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 508 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 509 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 510 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 511 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 512 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 513 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 514 515 /* P0.2 */ 516 P0_2_GPIO = 0, /* GPIO controls 'out' */ 517 P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 518 P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 519 P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 520 P0_2_AMUXA = 4, /* Analog mux bus A */ 521 P0_2_AMUXB = 5, /* Analog mux bus B */ 522 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 523 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 524 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 525 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 526 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 527 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 528 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 529 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 530 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 531 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 532 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 533 534 /* P0.3 */ 535 P0_3_GPIO = 0, /* GPIO controls 'out' */ 536 P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 537 P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 538 P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 539 P0_3_AMUXA = 4, /* Analog mux bus A */ 540 P0_3_AMUXB = 5, /* Analog mux bus B */ 541 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 542 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 543 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 544 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 545 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 546 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 547 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 548 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 549 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 550 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 551 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 552 553 /* P0.4 */ 554 P0_4_GPIO = 0, /* GPIO controls 'out' */ 555 P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 556 P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 557 P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 558 P0_4_AMUXA = 4, /* Analog mux bus A */ 559 P0_4_AMUXB = 5, /* Analog mux bus B */ 560 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 561 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 562 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 563 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 564 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 565 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 566 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 567 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 568 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 569 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 570 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 571 572 /* P0.5 */ 573 P0_5_GPIO = 0, /* GPIO controls 'out' */ 574 P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 575 P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 576 P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 577 P0_5_AMUXA = 4, /* Analog mux bus A */ 578 P0_5_AMUXB = 5, /* Analog mux bus B */ 579 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 580 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 581 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 582 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 583 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 584 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 585 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 586 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 587 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 588 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 589 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 590 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 591 592 /* P1.0 */ 593 P1_0_GPIO = 0, /* GPIO controls 'out' */ 594 P1_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 595 P1_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 596 P1_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 597 P1_0_AMUXA = 4, /* Analog mux bus A */ 598 P1_0_AMUXB = 5, /* Analog mux bus B */ 599 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 600 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 601 P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 602 P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 603 P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 604 P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 605 P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 606 P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 607 P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ 608 P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ 609 P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ 610 P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 611 612 /* P1.1 */ 613 P1_1_GPIO = 0, /* GPIO controls 'out' */ 614 P1_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 615 P1_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 616 P1_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 617 P1_1_AMUXA = 4, /* Analog mux bus A */ 618 P1_1_AMUXB = 5, /* Analog mux bus B */ 619 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 620 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 621 P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 622 P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 623 P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 624 P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 625 P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 626 P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 627 P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ 628 P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ 629 P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ 630 P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 631 632 /* P1.3 */ 633 P1_3_GPIO = 0, /* GPIO controls 'out' */ 634 P1_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 635 P1_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 636 P1_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 637 P1_3_AMUXA = 4, /* Analog mux bus A */ 638 P1_3_AMUXB = 5, /* Analog mux bus B */ 639 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 640 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 641 P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */ 642 P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ 643 P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 644 P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 645 P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 646 P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 647 P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */ 648 P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */ 649 650 /* P1.4 */ 651 P1_4_GPIO = 0, /* GPIO controls 'out' */ 652 P1_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 653 P1_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 654 P1_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 655 P1_4_AMUXA = 4, /* Analog mux bus A */ 656 P1_4_AMUXB = 5, /* Analog mux bus B */ 657 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 658 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 659 P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ 660 P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ 661 P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 662 P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 663 P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 664 P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 665 P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ 666 667 /* P1.5 */ 668 P1_5_GPIO = 0, /* GPIO controls 'out' */ 669 P1_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 670 P1_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 671 P1_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 672 P1_5_AMUXA = 4, /* Analog mux bus A */ 673 P1_5_AMUXB = 5, /* Analog mux bus B */ 674 P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 675 P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 676 P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ 677 P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 678 P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 679 P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 680 P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 681 P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 682 P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ 683 684 /* P5.0 */ 685 P5_0_GPIO = 0, /* GPIO controls 'out' */ 686 P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 687 P5_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 688 P5_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 689 P5_0_AMUXA = 4, /* Analog mux bus A */ 690 P5_0_AMUXB = 5, /* Analog mux bus B */ 691 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 692 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 693 P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 694 P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 695 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 696 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 697 P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 698 P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 699 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 700 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 701 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 702 P5_0_AUDIOSS_CLK_I2S_IF = 22, /* Digital Active - audioss.clk_i2s_if */ 703 P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */ 704 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 705 706 /* P5.1 */ 707 P5_1_GPIO = 0, /* GPIO controls 'out' */ 708 P5_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 709 P5_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 710 P5_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 711 P5_1_AMUXA = 4, /* Analog mux bus A */ 712 P5_1_AMUXB = 5, /* Analog mux bus B */ 713 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 714 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 715 P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 716 P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 717 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 718 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 719 P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 720 P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 721 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 722 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 723 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 724 P5_1_AUDIOSS_TX_SCK = 22, /* Digital Active - audioss.tx_sck */ 725 P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */ 726 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 727 728 /* P5.2 */ 729 P5_2_GPIO = 0, /* GPIO controls 'out' */ 730 P5_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 731 P5_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 732 P5_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 733 P5_2_AMUXA = 4, /* Analog mux bus A */ 734 P5_2_AMUXB = 5, /* Analog mux bus B */ 735 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 736 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 737 P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 738 P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 739 P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 740 P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 741 P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 742 P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 743 P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 744 P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 745 P5_2_AUDIOSS_TX_WS = 22, /* Digital Active - audioss.tx_ws */ 746 P5_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:0 */ 747 748 /* P5.3 */ 749 P5_3_GPIO = 0, /* GPIO controls 'out' */ 750 P5_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 751 P5_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 752 P5_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 753 P5_3_AMUXA = 4, /* Analog mux bus A */ 754 P5_3_AMUXB = 5, /* Analog mux bus B */ 755 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 756 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 757 P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ 758 P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 759 P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 760 P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 761 P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ 762 P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ 763 P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 764 P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 765 P5_3_AUDIOSS_TX_SDO = 22, /* Digital Active - audioss.tx_sdo */ 766 P5_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:0 */ 767 768 /* P5.4 */ 769 P5_4_GPIO = 0, /* GPIO controls 'out' */ 770 P5_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 771 P5_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 772 P5_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 773 P5_4_AMUXA = 4, /* Analog mux bus A */ 774 P5_4_AMUXB = 5, /* Analog mux bus B */ 775 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 776 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 777 P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ 778 P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 779 P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ 780 P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ 781 P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ 782 P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ 783 P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 784 P5_4_AUDIOSS_RX_SCK = 22, /* Digital Active - audioss.rx_sck */ 785 P5_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:0 */ 786 787 /* P5.5 */ 788 P5_5_GPIO = 0, /* GPIO controls 'out' */ 789 P5_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 790 P5_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 791 P5_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 792 P5_5_AMUXA = 4, /* Analog mux bus A */ 793 P5_5_AMUXB = 5, /* Analog mux bus B */ 794 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 795 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 796 P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ 797 P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 798 P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 799 P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 800 P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 801 P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 802 P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 803 P5_5_AUDIOSS_RX_WS = 22, /* Digital Active - audioss.rx_ws */ 804 P5_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:0 */ 805 806 /* P5.6 */ 807 P5_6_GPIO = 0, /* GPIO controls 'out' */ 808 P5_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 809 P5_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 810 P5_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 811 P5_6_AMUXA = 4, /* Analog mux bus A */ 812 P5_6_AMUXB = 5, /* Analog mux bus B */ 813 P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 814 P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 815 P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 816 P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 817 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 818 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 819 P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 820 P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 821 P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 822 P5_6_AUDIOSS_RX_SDI = 22, /* Digital Active - audioss.rx_sdi */ 823 P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */ 824 825 /* P5.7 */ 826 P5_7_GPIO = 0, /* GPIO controls 'out' */ 827 P5_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 828 P5_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 829 P5_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 830 P5_7_AMUXA = 4, /* Analog mux bus A */ 831 P5_7_AMUXB = 5, /* Analog mux bus B */ 832 P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 833 P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 834 P5_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:0 */ 835 P5_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 836 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 837 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 838 P5_7_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 839 P5_7_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 840 P5_7_SCB3_SPI_SELECT3 = 20, /* Digital Active - scb[3].spi_select3:0 */ 841 842 /* P6.0 */ 843 P6_0_GPIO = 0, /* GPIO controls 'out' */ 844 P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 845 P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 846 P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 847 P6_0_AMUXA = 4, /* Analog mux bus A */ 848 P6_0_AMUXB = 5, /* Analog mux bus B */ 849 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 850 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 851 P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 852 P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ 853 P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 854 P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 855 P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ 856 P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ 857 P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ 858 P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 859 P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 860 P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ 861 P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 862 P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ 863 864 /* P6.1 */ 865 P6_1_GPIO = 0, /* GPIO controls 'out' */ 866 P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 867 P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 868 P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 869 P6_1_AMUXA = 4, /* Analog mux bus A */ 870 P6_1_AMUXB = 5, /* Analog mux bus B */ 871 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 872 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 873 P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 874 P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 875 P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 876 P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 877 P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ 878 P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ 879 P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ 880 P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 881 P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 882 P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ 883 P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 884 P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ 885 886 /* P6.2 */ 887 P6_2_GPIO = 0, /* GPIO controls 'out' */ 888 P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 889 P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 890 P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 891 P6_2_AMUXA = 4, /* Analog mux bus A */ 892 P6_2_AMUXB = 5, /* Analog mux bus B */ 893 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 894 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 895 P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 896 P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ 897 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 898 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 899 P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 900 P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 901 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 902 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 903 P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ 904 905 /* P6.3 */ 906 P6_3_GPIO = 0, /* GPIO controls 'out' */ 907 P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 908 P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 909 P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 910 P6_3_AMUXA = 4, /* Analog mux bus A */ 911 P6_3_AMUXB = 5, /* Analog mux bus B */ 912 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 913 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 914 P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 915 P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 916 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 917 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 918 P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 919 P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 920 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 921 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 922 P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ 923 924 /* P6.4 */ 925 P6_4_GPIO = 0, /* GPIO controls 'out' */ 926 P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 927 P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 928 P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 929 P6_4_AMUXA = 4, /* Analog mux bus A */ 930 P6_4_AMUXB = 5, /* Analog mux bus B */ 931 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 932 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 933 P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 934 P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ 935 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 936 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 937 P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 938 P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 939 P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ 940 P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ 941 P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ 942 P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ 943 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 944 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 945 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 946 P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ 947 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 948 949 /* P6.5 */ 950 P6_5_GPIO = 0, /* GPIO controls 'out' */ 951 P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 952 P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 953 P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 954 P6_5_AMUXA = 4, /* Analog mux bus A */ 955 P6_5_AMUXB = 5, /* Analog mux bus B */ 956 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 957 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 958 P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 959 P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 960 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 961 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 962 P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 963 P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 964 P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ 965 P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ 966 P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ 967 P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ 968 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 969 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 970 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 971 P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ 972 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 973 974 /* P6.6 */ 975 P6_6_GPIO = 0, /* GPIO controls 'out' */ 976 P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 977 P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 978 P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 979 P6_6_AMUXA = 4, /* Analog mux bus A */ 980 P6_6_AMUXB = 5, /* Analog mux bus B */ 981 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 982 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 983 P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 984 P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ 985 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 986 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 987 P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 988 P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 989 P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ 990 P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ 991 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 992 P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ 993 994 /* P6.7 */ 995 P6_7_GPIO = 0, /* GPIO controls 'out' */ 996 P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 997 P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 998 P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 999 P6_7_AMUXA = 4, /* Analog mux bus A */ 1000 P6_7_AMUXB = 5, /* Analog mux bus B */ 1001 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1002 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1003 P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 1004 P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 1005 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 1006 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 1007 P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 1008 P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 1009 P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ 1010 P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ 1011 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 1012 P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ 1013 1014 /* P7.0 */ 1015 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1016 P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1017 P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1018 P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1019 P7_0_AMUXA = 4, /* Analog mux bus A */ 1020 P7_0_AMUXB = 5, /* Analog mux bus B */ 1021 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1022 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1023 P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 1024 P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ 1025 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 1026 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 1027 P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 1028 P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 1029 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 1030 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 1031 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 1032 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 1033 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 1034 1035 /* P7.1 */ 1036 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1037 P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1038 P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1039 P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1040 P7_1_AMUXA = 4, /* Analog mux bus A */ 1041 P7_1_AMUXB = 5, /* Analog mux bus B */ 1042 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1043 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1044 P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 1045 P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1046 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1047 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1048 P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1049 P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1050 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 1051 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 1052 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 1053 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 1054 1055 /* P7.2 */ 1056 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1057 P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1058 P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1059 P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1060 P7_2_AMUXA = 4, /* Analog mux bus A */ 1061 P7_2_AMUXB = 5, /* Analog mux bus B */ 1062 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1063 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1064 P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 1065 P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ 1066 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1067 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1068 P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1069 P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1070 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 1071 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 1072 1073 /* P7.3 */ 1074 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1075 P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1076 P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1077 P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1078 P7_3_AMUXA = 4, /* Analog mux bus A */ 1079 P7_3_AMUXB = 5, /* Analog mux bus B */ 1080 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1081 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1082 P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 1083 P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1084 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1085 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1086 P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1087 P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1088 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 1089 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 1090 1091 /* P7.4 */ 1092 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1093 P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1094 P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1095 P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1096 P7_4_AMUXA = 4, /* Analog mux bus A */ 1097 P7_4_AMUXB = 5, /* Analog mux bus B */ 1098 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1099 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1100 P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 1101 P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ 1102 P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ 1103 P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ 1104 P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ 1105 P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ 1106 P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ 1107 P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */ 1108 P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 1109 1110 /* P7.5 */ 1111 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1112 P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1113 P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1114 P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1115 P7_5_AMUXA = 4, /* Analog mux bus A */ 1116 P7_5_AMUXB = 5, /* Analog mux bus B */ 1117 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1118 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1119 P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 1120 P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ 1121 P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ 1122 P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ 1123 P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ 1124 P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ 1125 P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ 1126 P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */ 1127 P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ 1128 1129 /* P7.6 */ 1130 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1131 P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1132 P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1133 P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1134 P7_6_AMUXA = 4, /* Analog mux bus A */ 1135 P7_6_AMUXB = 5, /* Analog mux bus B */ 1136 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1137 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1138 P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 1139 P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ 1140 P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 1141 P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 1142 P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ 1143 P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ 1144 P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ 1145 P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */ 1146 P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ 1147 1148 /* P7.7 */ 1149 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1150 P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1151 P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1152 P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1153 P7_7_AMUXA = 4, /* Analog mux bus A */ 1154 P7_7_AMUXB = 5, /* Analog mux bus B */ 1155 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1156 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1157 P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 1158 P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 1159 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1160 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1161 P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1162 P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1163 P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ 1164 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 1165 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 1166 1167 /* P8.0 */ 1168 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1169 P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1170 P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1171 P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1172 P8_0_AMUXA = 4, /* Analog mux bus A */ 1173 P8_0_AMUXB = 5, /* Analog mux bus B */ 1174 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1175 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1176 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 1177 P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ 1178 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1179 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1180 P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1181 P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1182 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 1183 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 1184 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 1185 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 1186 1187 /* P8.1 */ 1188 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1189 P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1190 P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1191 P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1192 P8_1_AMUXA = 4, /* Analog mux bus A */ 1193 P8_1_AMUXB = 5, /* Analog mux bus B */ 1194 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1195 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1196 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 1197 P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 1198 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1199 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1200 P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1201 P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1202 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 1203 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 1204 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 1205 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 1206 1207 /* P8.2 */ 1208 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1209 P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1210 P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1211 P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1212 P8_2_AMUXA = 4, /* Analog mux bus A */ 1213 P8_2_AMUXB = 5, /* Analog mux bus B */ 1214 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1215 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1216 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 1217 P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ 1218 P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1219 P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1220 P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1221 P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1222 P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 1223 P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 1224 P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 1225 1226 /* P8.3 */ 1227 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1228 P8_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1229 P8_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1230 P8_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1231 P8_3_AMUXA = 4, /* Analog mux bus A */ 1232 P8_3_AMUXB = 5, /* Analog mux bus B */ 1233 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1234 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1235 P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 1236 P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 1237 P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1238 P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1239 P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1240 P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1241 P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 1242 P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 1243 P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 1244 1245 /* P8.4 */ 1246 P8_4_GPIO = 0, /* GPIO controls 'out' */ 1247 P8_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1248 P8_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1249 P8_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1250 P8_4_AMUXA = 4, /* Analog mux bus A */ 1251 P8_4_AMUXB = 5, /* Analog mux bus B */ 1252 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1253 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1254 P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 1255 P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ 1256 P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1257 P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1258 P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1259 P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1260 P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ 1261 1262 /* P8.5 */ 1263 P8_5_GPIO = 0, /* GPIO controls 'out' */ 1264 P8_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1265 P8_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1266 P8_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1267 P8_5_AMUXA = 4, /* Analog mux bus A */ 1268 P8_5_AMUXB = 5, /* Analog mux bus B */ 1269 P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1270 P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1271 P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ 1272 P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ 1273 P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1274 P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1275 P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1276 P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1277 P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */ 1278 1279 /* P8.6 */ 1280 P8_6_GPIO = 0, /* GPIO controls 'out' */ 1281 P8_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1282 P8_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1283 P8_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1284 P8_6_AMUXA = 4, /* Analog mux bus A */ 1285 P8_6_AMUXB = 5, /* Analog mux bus B */ 1286 P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1287 P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1288 P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 1289 P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */ 1290 P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ 1291 P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ 1292 P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */ 1293 P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */ 1294 P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */ 1295 1296 /* P8.7 */ 1297 P8_7_GPIO = 0, /* GPIO controls 'out' */ 1298 P8_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1299 P8_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1300 P8_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1301 P8_7_AMUXA = 4, /* Analog mux bus A */ 1302 P8_7_AMUXB = 5, /* Analog mux bus B */ 1303 P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1304 P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1305 P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 1306 P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ 1307 P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ 1308 P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ 1309 P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */ 1310 P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */ 1311 P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */ 1312 1313 /* P9.0 */ 1314 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1315 P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1316 P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1317 P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1318 P9_0_AMUXA = 4, /* Analog mux bus A */ 1319 P9_0_AMUXB = 5, /* Analog mux bus B */ 1320 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1321 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1322 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ 1323 P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ 1324 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1325 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1326 P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 1327 P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 1328 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 1329 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 1330 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 1331 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 1332 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1333 1334 /* P9.1 */ 1335 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1336 P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1337 P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1338 P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1339 P9_1_AMUXA = 4, /* Analog mux bus A */ 1340 P9_1_AMUXB = 5, /* Analog mux bus B */ 1341 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1342 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1343 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ 1344 P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 1345 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1346 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1347 P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 1348 P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 1349 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 1350 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 1351 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 1352 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 1353 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1354 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1355 1356 /* P9.2 */ 1357 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1358 P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1359 P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1360 P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1361 P9_2_AMUXA = 4, /* Analog mux bus A */ 1362 P9_2_AMUXB = 5, /* Analog mux bus B */ 1363 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1364 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1365 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ 1366 P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ 1367 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ 1368 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ 1369 P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1370 P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1371 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 1372 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 1373 P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ 1374 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1375 1376 /* P9.3 */ 1377 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1378 P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1379 P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1380 P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1381 P9_3_AMUXA = 4, /* Analog mux bus A */ 1382 P9_3_AMUXB = 5, /* Analog mux bus B */ 1383 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1384 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1385 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ 1386 P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 1387 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ 1388 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ 1389 P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1390 P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1391 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1392 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1393 P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ 1394 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1395 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1396 1397 /* P10.0 */ 1398 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1399 P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1400 P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1401 P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1402 P10_0_AMUXA = 4, /* Analog mux bus A */ 1403 P10_0_AMUXB = 5, /* Analog mux bus B */ 1404 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1405 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1406 P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ 1407 P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ 1408 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ 1409 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ 1410 P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ 1411 P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ 1412 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 1413 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 1414 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 1415 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1416 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1417 1418 /* P10.1 */ 1419 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1420 P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1421 P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1422 P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1423 P10_1_AMUXA = 4, /* Analog mux bus A */ 1424 P10_1_AMUXB = 5, /* Analog mux bus B */ 1425 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1426 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1427 P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ 1428 P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 1429 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ 1430 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ 1431 P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ 1432 P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ 1433 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 1434 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 1435 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 1436 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1437 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1438 1439 /* P10.2 */ 1440 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1441 P10_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1442 P10_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1443 P10_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1444 P10_2_AMUXA = 4, /* Analog mux bus A */ 1445 P10_2_AMUXB = 5, /* Analog mux bus B */ 1446 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1447 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1448 P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ 1449 P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ 1450 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ 1451 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ 1452 P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ 1453 P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ 1454 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 1455 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 1456 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1457 1458 /* P10.3 */ 1459 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1460 P10_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1461 P10_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1462 P10_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1463 P10_3_AMUXA = 4, /* Analog mux bus A */ 1464 P10_3_AMUXB = 5, /* Analog mux bus B */ 1465 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1466 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1467 P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ 1468 P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 1469 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ 1470 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ 1471 P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ 1472 P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ 1473 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 1474 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 1475 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1476 1477 /* P10.4 */ 1478 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1479 P10_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1480 P10_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1481 P10_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1482 P10_4_AMUXA = 4, /* Analog mux bus A */ 1483 P10_4_AMUXB = 5, /* Analog mux bus B */ 1484 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1485 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1486 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 1487 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 1488 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ 1489 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ 1490 P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ 1491 P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ 1492 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 1493 P10_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:0 */ 1494 P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0:0 */ 1495 1496 /* P10.5 */ 1497 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1498 P10_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1499 P10_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1500 P10_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1501 P10_5_AMUXA = 4, /* Analog mux bus A */ 1502 P10_5_AMUXB = 5, /* Analog mux bus B */ 1503 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1504 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1505 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 1506 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1507 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ 1508 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ 1509 P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ 1510 P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ 1511 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 1512 P10_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:0 */ 1513 P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0:0 */ 1514 1515 /* P10.6 */ 1516 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1517 P10_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1518 P10_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1519 P10_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1520 P10_6_AMUXA = 4, /* Analog mux bus A */ 1521 P10_6_AMUXB = 5, /* Analog mux bus B */ 1522 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1523 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1524 P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ 1525 P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ 1526 P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */ 1527 P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */ 1528 P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */ 1529 P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */ 1530 P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 1531 1532 /* P10.7 */ 1533 P10_7_GPIO = 0, /* GPIO controls 'out' */ 1534 P10_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1535 P10_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1536 P10_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1537 P10_7_AMUXA = 4, /* Analog mux bus A */ 1538 P10_7_AMUXB = 5, /* Analog mux bus B */ 1539 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1540 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1541 P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ 1542 P10_7_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ 1543 P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:77 */ 1544 P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:77 */ 1545 P10_7_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:1 */ 1546 P10_7_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:1 */ 1547 1548 /* P11.0 */ 1549 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1550 P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1551 P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1552 P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1553 P11_0_AMUXA = 4, /* Analog mux bus A */ 1554 P11_0_AMUXB = 5, /* Analog mux bus B */ 1555 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1556 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1557 P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 1558 P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 1559 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ 1560 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ 1561 P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ 1562 P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ 1563 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1564 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 1565 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 1566 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 1567 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1568 1569 /* P11.1 */ 1570 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1571 P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1572 P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1573 P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1574 P11_1_AMUXA = 4, /* Analog mux bus A */ 1575 P11_1_AMUXB = 5, /* Analog mux bus B */ 1576 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1577 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1578 P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 1579 P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1580 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ 1581 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ 1582 P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ 1583 P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ 1584 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1585 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 1586 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 1587 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 1588 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1589 1590 /* P11.2 */ 1591 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1592 P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1593 P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1594 P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1595 P11_2_AMUXA = 4, /* Analog mux bus A */ 1596 P11_2_AMUXB = 5, /* Analog mux bus B */ 1597 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1598 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1599 P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 1600 P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 1601 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ 1602 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ 1603 P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ 1604 P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ 1605 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1606 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ 1607 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ 1608 1609 /* P11.3 */ 1610 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1611 P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1612 P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1613 P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1614 P11_3_AMUXA = 4, /* Analog mux bus A */ 1615 P11_3_AMUXB = 5, /* Analog mux bus B */ 1616 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1617 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1618 P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 1619 P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1620 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ 1621 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ 1622 P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ 1623 P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ 1624 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1625 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ 1626 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ 1627 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1628 1629 /* P11.4 */ 1630 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1631 P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1632 P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1633 P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1634 P11_4_AMUXA = 4, /* Analog mux bus A */ 1635 P11_4_AMUXB = 5, /* Analog mux bus B */ 1636 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1637 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1638 P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 1639 P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 1640 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ 1641 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ 1642 P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ 1643 P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ 1644 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1645 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ 1646 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1647 1648 /* P11.5 */ 1649 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1650 P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1651 P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1652 P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1653 P11_5_AMUXA = 4, /* Analog mux bus A */ 1654 P11_5_AMUXB = 5, /* Analog mux bus B */ 1655 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1656 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1657 P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 1658 P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1659 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ 1660 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ 1661 P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ 1662 P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ 1663 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1664 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ 1665 1666 /* P11.6 */ 1667 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1668 P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1669 P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1670 P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1671 P11_6_AMUXA = 4, /* Analog mux bus A */ 1672 P11_6_AMUXB = 5, /* Analog mux bus B */ 1673 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1674 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1675 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ 1676 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ 1677 P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ 1678 P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ 1679 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1680 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ 1681 1682 /* P11.7 */ 1683 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1684 P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1685 P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1686 P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1687 P11_7_AMUXA = 4, /* Analog mux bus A */ 1688 P11_7_AMUXB = 5, /* Analog mux bus B */ 1689 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1690 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1691 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1692 1693 /* P12.0 */ 1694 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1695 P12_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1696 P12_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1697 P12_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1698 P12_0_AMUXA = 4, /* Analog mux bus A */ 1699 P12_0_AMUXB = 5, /* Analog mux bus B */ 1700 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1701 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1702 P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ 1703 P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 1704 P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ 1705 P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ 1706 P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ 1707 P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ 1708 P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ 1709 P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ 1710 P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ 1711 P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ 1712 P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 1713 1714 /* P12.1 */ 1715 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1716 P12_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1717 P12_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1718 P12_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1719 P12_1_AMUXA = 4, /* Analog mux bus A */ 1720 P12_1_AMUXB = 5, /* Analog mux bus B */ 1721 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1722 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1723 P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ 1724 P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 1725 P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ 1726 P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ 1727 P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ 1728 P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ 1729 P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ 1730 P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ 1731 P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ 1732 P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ 1733 P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 1734 1735 /* P12.2 */ 1736 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1737 P12_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1738 P12_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1739 P12_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1740 P12_2_AMUXA = 4, /* Analog mux bus A */ 1741 P12_2_AMUXB = 5, /* Analog mux bus B */ 1742 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1743 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1744 P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ 1745 P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 1746 P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ 1747 P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ 1748 P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ 1749 P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ 1750 P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ 1751 P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ 1752 P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ 1753 1754 /* P12.3 */ 1755 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1756 P12_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1757 P12_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1758 P12_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1759 P12_3_AMUXA = 4, /* Analog mux bus A */ 1760 P12_3_AMUXB = 5, /* Analog mux bus B */ 1761 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1762 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1763 P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ 1764 P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 1765 P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ 1766 P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ 1767 P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ 1768 P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ 1769 P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ 1770 P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ 1771 P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ 1772 1773 /* P12.4 */ 1774 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1775 P12_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1776 P12_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1777 P12_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1778 P12_4_AMUXA = 4, /* Analog mux bus A */ 1779 P12_4_AMUXB = 5, /* Analog mux bus B */ 1780 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1781 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1782 P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ 1783 P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 1784 P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ 1785 P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ 1786 P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ 1787 P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ 1788 P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ 1789 P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ 1790 P12_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:1 */ 1791 P12_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:1:0 */ 1792 1793 /* P13.0 */ 1794 P13_0_GPIO = 0, /* GPIO controls 'out' */ 1795 P13_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1796 P13_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1797 P13_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1798 P13_0_AMUXA = 4, /* Analog mux bus A */ 1799 P13_0_AMUXB = 5, /* Analog mux bus B */ 1800 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1801 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1802 P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 1803 P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */ 1804 P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */ 1805 P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */ 1806 P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */ 1807 P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */ 1808 P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ 1809 P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ 1810 P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */ 1811 P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */ 1812 1813 /* P13.1 */ 1814 P13_1_GPIO = 0, /* GPIO controls 'out' */ 1815 P13_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1816 P13_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1817 P13_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1818 P13_1_AMUXA = 4, /* Analog mux bus A */ 1819 P13_1_AMUXB = 5, /* Analog mux bus B */ 1820 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1821 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1822 P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 1823 P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ 1824 P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */ 1825 P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */ 1826 P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */ 1827 P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */ 1828 P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ 1829 P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ 1830 P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ 1831 P13_1_PERI_TR_IO_INPUT27 = 24 /* Digital Active - peri.tr_io_input[27]:0 */ 1832 } en_hsiom_sel_t; 1833 1834 #endif /* _GPIO_PSOC6_01_104_M_CSP_BLE_H_ */ 1835 1836 1837 /* [] END OF FILE */ 1838
