1 /*
2 * Copyright (c) 2017, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_gpio
8
9 #include <errno.h>
10 #include <zephyr/device.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/irq.h>
13 #include <soc.h>
14 #include <fsl_common.h>
15 #include <fsl_gpio.h>
16
17 #include <zephyr/drivers/pinctrl.h>
18
19 #include <zephyr/drivers/gpio/gpio_utils.h>
20
21 struct gpio_pin_gaps {
22 uint8_t start;
23 uint8_t len;
24 };
25
26 struct mcux_igpio_config {
27 /* gpio_driver_config needs to be first */
28 struct gpio_driver_config common;
29 GPIO_Type *base;
30 const struct pinctrl_soc_pinmux *pin_muxes;
31 const struct gpio_pin_gaps *pin_gaps;
32 uint8_t mux_count;
33 uint8_t gap_count;
34 };
35
36 struct mcux_igpio_data {
37 /* gpio_driver_data needs to be first */
38 struct gpio_driver_data general;
39 /* port ISR callback routine address */
40 sys_slist_t callbacks;
41 };
42
mcux_igpio_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)43 static int mcux_igpio_configure(const struct device *dev,
44 gpio_pin_t pin, gpio_flags_t flags)
45 {
46 const struct mcux_igpio_config *config = dev->config;
47 GPIO_Type *base = config->base;
48
49 struct pinctrl_soc_pin pin_cfg;
50 int cfg_idx = pin, i;
51
52 /* Some SOCs have non-contiguous gpio pin layouts, account for this */
53 for (i = 0; i < config->gap_count; i++) {
54 if (pin >= config->pin_gaps[i].start) {
55 if (pin < (config->pin_gaps[i].start +
56 config->pin_gaps[i].len)) {
57 /* Pin is not connected to a mux */
58 return -ENOTSUP;
59 }
60 cfg_idx -= config->pin_gaps[i].len;
61 }
62 }
63
64 /* Init pin configuration struct, and use pinctrl api to apply settings */
65 if (cfg_idx >= config->mux_count) {
66 /* Pin is not connected to a mux */
67 return -ENOTSUP;
68 }
69
70 /* Set appropriate bits in pin configuration register */
71 volatile uint32_t *gpio_cfg_reg =
72 (volatile uint32_t *)config->pin_muxes[cfg_idx].config_register;
73 uint32_t reg = *gpio_cfg_reg;
74
75 #ifdef CONFIG_SOC_SERIES_IMX_RT10XX
76 if ((flags & GPIO_SINGLE_ENDED) != 0) {
77 /* Set ODE bit */
78 reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
79 } else {
80 reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
81 }
82 if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
83 reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
84 if (((flags & GPIO_PULL_UP) != 0)) {
85 /* Use 100K pullup */
86 reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(2);
87 } else {
88 /* 100K pulldown */
89 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
90 }
91 } else {
92 /* Set pin to keeper */
93 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
94 }
95 #elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
96 if (config->pin_muxes[pin].pue_mux) {
97 /* PUE type register layout (GPIO_AD pins) */
98 if ((flags & GPIO_SINGLE_ENDED) != 0) {
99 /* Set ODE bit */
100 reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
101 } else {
102 reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
103 }
104
105 if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
106 reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
107 if (((flags & GPIO_PULL_UP) != 0)) {
108 reg |= IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
109 } else {
110 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
111 }
112 } else {
113 /* Set pin to highz */
114 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
115 }
116 } else {
117 /* PDRV/SNVS/LPSR type register layout */
118 if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
119 reg &= ~IOMUXC_SW_PAD_CTL_PAD_PULL_MASK;
120 if (((flags & GPIO_PULL_UP) != 0)) {
121 reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x1U);
122 } else {
123 reg |= IOMUXC_SW_PAD_CTL_PAD_PULL(0x2U);
124 }
125 } else {
126 /* Set pin to no pull */
127 reg |= IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
128 }
129 /* PDRV/SNVS/LPSR reg have different ODE bits */
130 if (config->pin_muxes[cfg_idx].pdrv_mux) {
131 if ((flags & GPIO_SINGLE_ENDED) != 0) {
132 /* Set ODE bit */
133 reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
134 } else {
135 reg &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK;
136 }
137 } else if (config->pin_muxes[cfg_idx].lpsr_mux) {
138 if ((flags & GPIO_SINGLE_ENDED) != 0) {
139 /* Set ODE bit */
140 reg |= (IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 1);
141 } else {
142 reg &= ~(IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 1);
143 }
144 } else if (config->pin_muxes[cfg_idx].snvs_mux) {
145 if ((flags & GPIO_SINGLE_ENDED) != 0) {
146 /* Set ODE bit */
147 reg |= (IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 2);
148 } else {
149 reg &= ~(IOMUXC_SW_PAD_CTL_PAD_ODE_MASK << 2);
150 }
151 }
152
153
154 }
155 #elif defined(CONFIG_SOC_SERIES_IMX8MQ_M4)
156 if ((flags & GPIO_SINGLE_ENDED) != 0) {
157 /* Set ODE bit */
158 reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
159 } else {
160 reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
161 }
162 if ((flags & GPIO_PULL_UP) != 0) {
163 reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
164 }
165 if ((flag & GPIO_PULL_DOWN) != 0) {
166 return -ENOTSUP;
167 }
168 #else
169 /* Default flags, should work for most SOCs */
170 if ((flags & GPIO_SINGLE_ENDED) != 0) {
171 /* Set ODE bit */
172 reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
173 } else {
174 reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
175 }
176 if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
177 reg |= (0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT);
178 if (((flags & GPIO_PULL_UP) != 0)) {
179 reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
180 } else {
181 reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
182 }
183 } else {
184 /* Set pin to highz */
185 reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT);
186 }
187 #endif /* CONFIG_SOC_SERIES_IMX_RT10XX */
188
189 memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg.pinmux));
190 /* cfg register will be set by pinctrl_configure_pins */
191 pin_cfg.pin_ctrl_flags = reg;
192 pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE);
193
194 if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
195 return -ENOTSUP;
196 }
197
198 if (flags & GPIO_OUTPUT_INIT_HIGH) {
199 GPIO_WritePinOutput(base, pin, 1);
200 }
201
202 if (flags & GPIO_OUTPUT_INIT_LOW) {
203 GPIO_WritePinOutput(base, pin, 0);
204 }
205
206 WRITE_BIT(base->GDIR, pin, flags & GPIO_OUTPUT);
207
208 return 0;
209 }
210
mcux_igpio_port_get_raw(const struct device * dev,uint32_t * value)211 static int mcux_igpio_port_get_raw(const struct device *dev, uint32_t *value)
212 {
213 const struct mcux_igpio_config *config = dev->config;
214 GPIO_Type *base = config->base;
215
216 *value = base->DR;
217
218 return 0;
219 }
220
mcux_igpio_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)221 static int mcux_igpio_port_set_masked_raw(const struct device *dev,
222 uint32_t mask,
223 uint32_t value)
224 {
225 const struct mcux_igpio_config *config = dev->config;
226 GPIO_Type *base = config->base;
227
228 base->DR = (base->DR & ~mask) | (mask & value);
229
230 return 0;
231 }
232
mcux_igpio_port_set_bits_raw(const struct device * dev,uint32_t mask)233 static int mcux_igpio_port_set_bits_raw(const struct device *dev,
234 uint32_t mask)
235 {
236 const struct mcux_igpio_config *config = dev->config;
237 GPIO_Type *base = config->base;
238
239 GPIO_PortSet(base, mask);
240
241 return 0;
242 }
243
mcux_igpio_port_clear_bits_raw(const struct device * dev,uint32_t mask)244 static int mcux_igpio_port_clear_bits_raw(const struct device *dev,
245 uint32_t mask)
246 {
247 const struct mcux_igpio_config *config = dev->config;
248 GPIO_Type *base = config->base;
249
250 GPIO_PortClear(base, mask);
251
252 return 0;
253 }
254
mcux_igpio_port_toggle_bits(const struct device * dev,uint32_t mask)255 static int mcux_igpio_port_toggle_bits(const struct device *dev,
256 uint32_t mask)
257 {
258 const struct mcux_igpio_config *config = dev->config;
259 GPIO_Type *base = config->base;
260
261 GPIO_PortToggle(base, mask);
262
263 return 0;
264 }
265
mcux_igpio_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)266 static int mcux_igpio_pin_interrupt_configure(const struct device *dev,
267 gpio_pin_t pin,
268 enum gpio_int_mode mode,
269 enum gpio_int_trig trig)
270 {
271 const struct mcux_igpio_config *config = dev->config;
272 GPIO_Type *base = config->base;
273 unsigned int key;
274 uint8_t icr;
275 int shift;
276
277 if (mode == GPIO_INT_MODE_DISABLED) {
278 key = irq_lock();
279
280 WRITE_BIT(base->IMR, pin, 0);
281
282 irq_unlock(key);
283
284 return 0;
285 }
286
287 if ((mode == GPIO_INT_MODE_EDGE) && (trig == GPIO_INT_TRIG_LOW)) {
288 icr = 3;
289 } else if ((mode == GPIO_INT_MODE_EDGE) &&
290 (trig == GPIO_INT_TRIG_HIGH)) {
291 icr = 2;
292 } else if ((mode == GPIO_INT_MODE_LEVEL) &&
293 (trig == GPIO_INT_TRIG_HIGH)) {
294 icr = 1;
295 } else {
296 icr = 0;
297 }
298
299 if (pin < 16) {
300 shift = 2 * pin;
301 base->ICR1 = (base->ICR1 & ~(3 << shift)) | (icr << shift);
302 } else if (pin < 32) {
303 shift = 2 * (pin - 16);
304 base->ICR2 = (base->ICR2 & ~(3 << shift)) | (icr << shift);
305 } else {
306 return -EINVAL;
307 }
308
309 key = irq_lock();
310
311 WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH);
312 WRITE_BIT(base->ISR, pin, 1);
313 WRITE_BIT(base->IMR, pin, 1);
314
315 irq_unlock(key);
316
317 return 0;
318 }
319
mcux_igpio_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)320 static int mcux_igpio_manage_callback(const struct device *dev,
321 struct gpio_callback *callback,
322 bool set)
323 {
324 struct mcux_igpio_data *data = dev->data;
325
326 return gpio_manage_callback(&data->callbacks, callback, set);
327 }
328
mcux_igpio_port_isr(const struct device * dev)329 static void mcux_igpio_port_isr(const struct device *dev)
330 {
331 const struct mcux_igpio_config *config = dev->config;
332 struct mcux_igpio_data *data = dev->data;
333 GPIO_Type *base = config->base;
334 uint32_t int_flags;
335
336 int_flags = base->ISR;
337 base->ISR = int_flags;
338
339 gpio_fire_callbacks(&data->callbacks, dev, int_flags);
340 }
341
342 static const struct gpio_driver_api mcux_igpio_driver_api = {
343 .pin_configure = mcux_igpio_configure,
344 .port_get_raw = mcux_igpio_port_get_raw,
345 .port_set_masked_raw = mcux_igpio_port_set_masked_raw,
346 .port_set_bits_raw = mcux_igpio_port_set_bits_raw,
347 .port_clear_bits_raw = mcux_igpio_port_clear_bits_raw,
348 .port_toggle_bits = mcux_igpio_port_toggle_bits,
349 .pin_interrupt_configure = mcux_igpio_pin_interrupt_configure,
350 .manage_callback = mcux_igpio_manage_callback,
351 };
352
353
354 /* These macros will declare an array of pinctrl_soc_pinmux types */
355 #define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
356 #define MCUX_IGPIO_PIN_DECLARE(n) \
357 const struct pinctrl_soc_pinmux mcux_igpio_pinmux_##n[] = { \
358 DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), pinmux, PINMUX_INIT) \
359 }; \
360 const uint8_t mcux_igpio_pin_gaps_##n[] = \
361 DT_INST_PROP_OR(n, gpio_reserved_ranges, {});
362 #define MCUX_IGPIO_PIN_INIT(n) \
363 .pin_muxes = mcux_igpio_pinmux_##n, \
364 .pin_gaps = (const struct gpio_pin_gaps *)mcux_igpio_pin_gaps_##n, \
365 .mux_count = DT_PROP_LEN(DT_DRV_INST(n), pinmux), \
366 .gap_count = (ARRAY_SIZE(mcux_igpio_pin_gaps_##n) / 2)
367
368 #define MCUX_IGPIO_IRQ_INIT(n, i) \
369 do { \
370 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, i, irq), \
371 DT_INST_IRQ_BY_IDX(n, i, priority), \
372 mcux_igpio_port_isr, \
373 DEVICE_DT_INST_GET(n), 0); \
374 \
375 irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
376 } while (false)
377
378 #define MCUX_IGPIO_INIT(n) \
379 MCUX_IGPIO_PIN_DECLARE(n) \
380 static int mcux_igpio_##n##_init(const struct device *dev); \
381 \
382 static const struct mcux_igpio_config mcux_igpio_##n##_config = {\
383 .common = { \
384 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
385 }, \
386 .base = (GPIO_Type *)DT_INST_REG_ADDR(n), \
387 MCUX_IGPIO_PIN_INIT(n) \
388 }; \
389 \
390 static struct mcux_igpio_data mcux_igpio_##n##_data; \
391 \
392 DEVICE_DT_INST_DEFINE(n, \
393 mcux_igpio_##n##_init, \
394 NULL, \
395 &mcux_igpio_##n##_data, \
396 &mcux_igpio_##n##_config, \
397 POST_KERNEL, \
398 CONFIG_GPIO_INIT_PRIORITY, \
399 &mcux_igpio_driver_api); \
400 \
401 static int mcux_igpio_##n##_init(const struct device *dev) \
402 { \
403 IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
404 (MCUX_IGPIO_IRQ_INIT(n, 0);)) \
405 \
406 IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1), \
407 (MCUX_IGPIO_IRQ_INIT(n, 1);)) \
408 \
409 return 0; \
410 }
411
412 DT_INST_FOREACH_STATUS_OKAY(MCUX_IGPIO_INIT)
413
