1 /*
2 * Copyright (c) 2016 Freescale Semiconductor, Inc.
3 * Copyright (c) 2017, NXP
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT nxp_kinetis_gpio
9
10 #include <errno.h>
11 #include <zephyr/device.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/dt-bindings/gpio/nxp-kinetis-gpio.h>
14 #include <zephyr/irq.h>
15 #include <soc.h>
16 #include <fsl_common.h>
17
18 #include <zephyr/drivers/gpio/gpio_utils.h>
19
20 struct gpio_mcux_config {
21 /* gpio_driver_config needs to be first */
22 struct gpio_driver_config common;
23 GPIO_Type *gpio_base;
24 PORT_Type *port_base;
25 unsigned int flags;
26 };
27
28 struct gpio_mcux_data {
29 /* gpio_driver_data needs to be first */
30 struct gpio_driver_data common;
31 /* port ISR callback routine address */
32 sys_slist_t callbacks;
33 };
34
gpio_mcux_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)35 static int gpio_mcux_configure(const struct device *dev,
36 gpio_pin_t pin, gpio_flags_t flags)
37 {
38 const struct gpio_mcux_config *config = dev->config;
39 GPIO_Type *gpio_base = config->gpio_base;
40 PORT_Type *port_base = config->port_base;
41 uint32_t mask = 0U;
42 uint32_t pcr = 0U;
43
44 /* Check for an invalid pin number */
45 if (pin >= ARRAY_SIZE(port_base->PCR)) {
46 return -EINVAL;
47 }
48
49 if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
50 return -ENOTSUP;
51 }
52
53 if ((flags & GPIO_SINGLE_ENDED) != 0) {
54 return -ENOTSUP;
55 }
56
57 /* The flags contain options that require touching registers in the
58 * GPIO module and the corresponding PORT module.
59 *
60 * Start with the GPIO module and set up the pin direction register.
61 * 0 - pin is input, 1 - pin is output
62 */
63
64 switch (flags & GPIO_DIR_MASK) {
65 case GPIO_INPUT:
66 gpio_base->PDDR &= ~BIT(pin);
67 break;
68 case GPIO_OUTPUT:
69 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
70 gpio_base->PSOR = BIT(pin);
71 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
72 gpio_base->PCOR = BIT(pin);
73 }
74 gpio_base->PDDR |= BIT(pin);
75 break;
76 default:
77 return -ENOTSUP;
78 }
79
80 /* Set PCR mux to GPIO for the pin we are configuring */
81 mask |= PORT_PCR_MUX_MASK;
82 pcr |= PORT_PCR_MUX(PORT_MUX_GPIO);
83
84 #if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
85 /* Enable digital input buffer */
86 pcr |= PORT_PCR_IBE_MASK;
87 #endif
88
89 /* Now do the PORT module. Figure out the pullup/pulldown
90 * configuration, but don't write it to the PCR register yet.
91 */
92 mask |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
93
94 if ((flags & GPIO_PULL_UP) != 0) {
95 /* Enable the pull and select the pullup resistor. */
96 pcr |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
97
98 } else if ((flags & GPIO_PULL_DOWN) != 0) {
99 /* Enable the pull and select the pulldown resistor (deselect
100 * the pullup resistor.
101 */
102 pcr |= PORT_PCR_PE_MASK;
103 }
104
105 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
106 /* Determine the drive strength */
107 switch (flags & KINETIS_GPIO_DS_MASK) {
108 case KINETIS_GPIO_DS_DFLT:
109 /* Default is low drive strength */
110 mask |= PORT_PCR_DSE_MASK;
111 break;
112 case KINETIS_GPIO_DS_ALT:
113 /* Alternate is high drive strength */
114 pcr |= PORT_PCR_DSE_MASK;
115 break;
116 default:
117 return -ENOTSUP;
118 }
119 #endif /* defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
120
121 /* Accessing by pin, we only need to write one PCR register. */
122 port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
123
124 return 0;
125 }
126
gpio_mcux_port_get_raw(const struct device * dev,uint32_t * value)127 static int gpio_mcux_port_get_raw(const struct device *dev, uint32_t *value)
128 {
129 const struct gpio_mcux_config *config = dev->config;
130 GPIO_Type *gpio_base = config->gpio_base;
131
132 *value = gpio_base->PDIR;
133
134 return 0;
135 }
136
gpio_mcux_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)137 static int gpio_mcux_port_set_masked_raw(const struct device *dev,
138 uint32_t mask,
139 uint32_t value)
140 {
141 const struct gpio_mcux_config *config = dev->config;
142 GPIO_Type *gpio_base = config->gpio_base;
143
144 gpio_base->PDOR = (gpio_base->PDOR & ~mask) | (mask & value);
145
146 return 0;
147 }
148
gpio_mcux_port_set_bits_raw(const struct device * dev,uint32_t mask)149 static int gpio_mcux_port_set_bits_raw(const struct device *dev,
150 uint32_t mask)
151 {
152 const struct gpio_mcux_config *config = dev->config;
153 GPIO_Type *gpio_base = config->gpio_base;
154
155 gpio_base->PSOR = mask;
156
157 return 0;
158 }
159
gpio_mcux_port_clear_bits_raw(const struct device * dev,uint32_t mask)160 static int gpio_mcux_port_clear_bits_raw(const struct device *dev,
161 uint32_t mask)
162 {
163 const struct gpio_mcux_config *config = dev->config;
164 GPIO_Type *gpio_base = config->gpio_base;
165
166 gpio_base->PCOR = mask;
167
168 return 0;
169 }
170
gpio_mcux_port_toggle_bits(const struct device * dev,uint32_t mask)171 static int gpio_mcux_port_toggle_bits(const struct device *dev, uint32_t mask)
172 {
173 const struct gpio_mcux_config *config = dev->config;
174 GPIO_Type *gpio_base = config->gpio_base;
175
176 gpio_base->PTOR = mask;
177
178 return 0;
179 }
180
get_port_pcr_irqc_value_from_flags(const struct device * dev,uint32_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)181 static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev,
182 uint32_t pin,
183 enum gpio_int_mode mode,
184 enum gpio_int_trig trig)
185 {
186 port_interrupt_t port_interrupt = 0;
187
188 if (mode == GPIO_INT_MODE_DISABLED) {
189 port_interrupt = kPORT_InterruptOrDMADisabled;
190 } else {
191 if (mode == GPIO_INT_MODE_LEVEL) {
192 if (trig == GPIO_INT_TRIG_LOW) {
193 port_interrupt = kPORT_InterruptLogicZero;
194 } else {
195 port_interrupt = kPORT_InterruptLogicOne;
196 }
197 } else {
198 switch (trig) {
199 case GPIO_INT_TRIG_LOW:
200 port_interrupt = kPORT_InterruptFallingEdge;
201 break;
202 case GPIO_INT_TRIG_HIGH:
203 port_interrupt = kPORT_InterruptRisingEdge;
204 break;
205 case GPIO_INT_TRIG_BOTH:
206 port_interrupt = kPORT_InterruptEitherEdge;
207 break;
208 }
209 }
210 }
211
212 return PORT_PCR_IRQC(port_interrupt);
213 }
214
gpio_mcux_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)215 static int gpio_mcux_pin_interrupt_configure(const struct device *dev,
216 gpio_pin_t pin, enum gpio_int_mode mode,
217 enum gpio_int_trig trig)
218 {
219 const struct gpio_mcux_config *config = dev->config;
220 GPIO_Type *gpio_base = config->gpio_base;
221 PORT_Type *port_base = config->port_base;
222
223 /* Check for an invalid pin number */
224 if (pin >= ARRAY_SIZE(port_base->PCR)) {
225 return -EINVAL;
226 }
227
228 /* Check for an invalid pin configuration */
229 if ((mode != GPIO_INT_MODE_DISABLED) &&
230 ((gpio_base->PDDR & BIT(pin)) != 0)) {
231 return -EINVAL;
232 }
233
234 /* Check if GPIO port supports interrupts */
235 if ((mode != GPIO_INT_MODE_DISABLED) &&
236 ((config->flags & GPIO_INT_ENABLE) == 0U)) {
237 return -ENOTSUP;
238 }
239
240 uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig);
241
242 port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr;
243
244 return 0;
245 }
246
gpio_mcux_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)247 static int gpio_mcux_manage_callback(const struct device *dev,
248 struct gpio_callback *callback, bool set)
249 {
250 struct gpio_mcux_data *data = dev->data;
251
252 return gpio_manage_callback(&data->callbacks, callback, set);
253 }
254
gpio_mcux_port_isr(const struct device * dev)255 static void gpio_mcux_port_isr(const struct device *dev)
256 {
257 const struct gpio_mcux_config *config = dev->config;
258 struct gpio_mcux_data *data = dev->data;
259 uint32_t int_status;
260
261 int_status = config->port_base->ISFR;
262
263 /* Clear the port interrupts */
264 config->port_base->ISFR = int_status;
265
266 gpio_fire_callbacks(&data->callbacks, dev, int_status);
267 }
268
269 #ifdef CONFIG_GPIO_GET_DIRECTION
gpio_mcux_port_get_direction(const struct device * dev,gpio_port_pins_t map,gpio_port_pins_t * inputs,gpio_port_pins_t * outputs)270 static int gpio_mcux_port_get_direction(const struct device *dev, gpio_port_pins_t map,
271 gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
272 {
273 const struct gpio_mcux_config *config = dev->config;
274 GPIO_Type *gpio_base = config->gpio_base;
275
276 map &= config->common.port_pin_mask;
277
278 if (inputs != NULL) {
279 *inputs = map & (~gpio_base->PDDR);
280 }
281
282 if (outputs != NULL) {
283 *outputs = map & gpio_base->PDDR;
284 }
285
286 return 0;
287 }
288 #endif /* CONFIG_GPIO_GET_DIRECTION */
289
290 static const struct gpio_driver_api gpio_mcux_driver_api = {
291 .pin_configure = gpio_mcux_configure,
292 .port_get_raw = gpio_mcux_port_get_raw,
293 .port_set_masked_raw = gpio_mcux_port_set_masked_raw,
294 .port_set_bits_raw = gpio_mcux_port_set_bits_raw,
295 .port_clear_bits_raw = gpio_mcux_port_clear_bits_raw,
296 .port_toggle_bits = gpio_mcux_port_toggle_bits,
297 .pin_interrupt_configure = gpio_mcux_pin_interrupt_configure,
298 .manage_callback = gpio_mcux_manage_callback,
299 #ifdef CONFIG_GPIO_GET_DIRECTION
300 .port_get_direction = gpio_mcux_port_get_direction,
301 #endif /* CONFIG_GPIO_GET_DIRECTION */
302 };
303
304 #define GPIO_MCUX_IRQ_INIT(n) \
305 do { \
306 IRQ_CONNECT(DT_INST_IRQN(n), \
307 DT_INST_IRQ(n, priority), \
308 gpio_mcux_port_isr, \
309 DEVICE_DT_INST_GET(n), 0); \
310 \
311 irq_enable(DT_INST_IRQN(n)); \
312 } while (false)
313
314 #define GPIO_PORT_BASE_ADDR(n) DT_REG_ADDR(DT_INST_PHANDLE(n, nxp_kinetis_port))
315
316 #define GPIO_DEVICE_INIT_MCUX(n) \
317 static int gpio_mcux_port## n ## _init(const struct device *dev); \
318 \
319 static const struct gpio_mcux_config gpio_mcux_port## n ## _config = {\
320 .common = { \
321 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
322 }, \
323 .gpio_base = (GPIO_Type *) DT_INST_REG_ADDR(n), \
324 .port_base = (PORT_Type *) GPIO_PORT_BASE_ADDR(n), \
325 .flags = UTIL_AND(DT_INST_IRQ_HAS_IDX(n, 0), GPIO_INT_ENABLE),\
326 }; \
327 \
328 static struct gpio_mcux_data gpio_mcux_port## n ##_data; \
329 \
330 DEVICE_DT_INST_DEFINE(n, \
331 gpio_mcux_port## n ##_init, \
332 NULL, \
333 &gpio_mcux_port## n ##_data, \
334 &gpio_mcux_port## n##_config, \
335 POST_KERNEL, \
336 CONFIG_GPIO_INIT_PRIORITY, \
337 &gpio_mcux_driver_api); \
338 \
339 static int gpio_mcux_port## n ##_init(const struct device *dev) \
340 { \
341 IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
342 (GPIO_MCUX_IRQ_INIT(n);)) \
343 return 0; \
344 }
345
346 DT_INST_FOREACH_STATUS_OKAY(GPIO_DEVICE_INIT_MCUX)
347
