1 /*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT microchip_xec_gpio_v2
8
9 #include <errno.h>
10 #include <zephyr/arch/cpu.h>
11 #include <zephyr/device.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
15 #include <soc.h>
16 #include <zephyr/irq.h>
17
18 #include <zephyr/drivers/gpio/gpio_utils.h>
19
20 #define XEC_GPIO_EDGE_DLY_COUNT 4
21
22 static const uint32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
23 (MCHP_GPIO_PORT_A_BITMAP),
24 (MCHP_GPIO_PORT_B_BITMAP),
25 (MCHP_GPIO_PORT_C_BITMAP),
26 (MCHP_GPIO_PORT_D_BITMAP),
27 (MCHP_GPIO_PORT_E_BITMAP),
28 (MCHP_GPIO_PORT_F_BITMAP),
29 };
30
31 struct gpio_xec_data {
32 /* gpio_driver_data needs to be first */
33 struct gpio_driver_data common;
34 /* port ISR callback routine address */
35 sys_slist_t callbacks;
36 };
37
38 struct gpio_xec_config {
39 /* gpio_driver_config needs to be first */
40 struct gpio_driver_config common;
41 uintptr_t pcr1_base;
42 uintptr_t parin_addr;
43 uintptr_t parout_addr;
44 uint8_t girq_id;
45 uint8_t port_num;
46 uint32_t flags;
47 };
48
49 /* Each GPIO pin 32-bit control register located consecutively in memory */
pin_ctrl_addr(const struct device * dev,gpio_pin_t pin)50 static inline uintptr_t pin_ctrl_addr(const struct device *dev, gpio_pin_t pin)
51 {
52 const struct gpio_xec_config *config = dev->config;
53
54 return config->pcr1_base + ((uintptr_t)pin * 4u);
55 }
56
57 /* GPIO Parallel input is a single 32-bit register per bank of 32 pins */
pin_parin_addr(const struct device * dev)58 static inline uintptr_t pin_parin_addr(const struct device *dev)
59 {
60 const struct gpio_xec_config *config = dev->config;
61
62 return config->parin_addr;
63 }
64
65 /* GPIO Parallel output is a single 32-bit register per bank of 32 pins */
pin_parout_addr(const struct device * dev)66 static inline uintptr_t pin_parout_addr(const struct device *dev)
67 {
68 const struct gpio_xec_config *config = dev->config;
69
70 return config->parout_addr;
71 }
72
73 /*
74 * Use Zephyr system API to implement
75 * reg32(addr) = (reg32(addr) & ~mask) | (val & mask)
76 */
xec_mask_write32(uintptr_t addr,uint32_t mask,uint32_t val)77 static inline void xec_mask_write32(uintptr_t addr, uint32_t mask, uint32_t val)
78 {
79 uint32_t r = (sys_read32(addr) & ~mask) | (val & mask);
80
81 sys_write32(r, addr);
82 }
83
84 /*
85 * NOTE: gpio_flags_t b[15:0] are defined in the dt-binding gpio header.
86 * b[31:16] are defined in the driver gpio header.
87 * Hardware only supports push-pull or open-drain.
88 */
gpio_xec_validate_flags(gpio_flags_t flags)89 static int gpio_xec_validate_flags(gpio_flags_t flags)
90 {
91 if ((flags & (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN))
92 == (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)) {
93 return -ENOTSUP;
94 }
95
96 if ((flags & (GPIO_INPUT | GPIO_OUTPUT))
97 == (GPIO_INPUT | GPIO_OUTPUT)) {
98 return -ENOTSUP;
99 }
100
101 if ((flags & GPIO_OUTPUT_INIT_LOW) && (flags & GPIO_OUTPUT_INIT_HIGH)) {
102 return -EINVAL;
103 }
104
105 return 0;
106 }
107
108 /*
109 * Each GPIO pin has two 32-bit control registers. Control 1 configures pin
110 * features except for drive strength and slew rate in Control 2.
111 * A pin's input and output state can be read/written from either the Control 1
112 * register or from corresponding bits in the GPIO parallel input/output registers.
113 * The parallel input and output registers group 32 pins into each register.
114 * The GPIO hardware restricts the pin output state to Control 1 or the parallel bit.
115 * Both output bits reflect each other on read and writes but only one is writable
116 * selected by the output control select bit in Control 1. In the configuration API
117 * we use Control 1 to configure all pin features and output state. Before exiting,
118 * we set the output select for parallel mode enabling writes to the parallel output bit.
119 */
gpio_xec_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)120 static int gpio_xec_configure(const struct device *dev,
121 gpio_pin_t pin, gpio_flags_t flags)
122 {
123 const struct gpio_xec_config *config = dev->config;
124 uintptr_t pcr1_addr = 0u;
125 uint32_t pcr1 = 0u, pcr1_new = 0u;
126 uint32_t msk = (MCHP_GPIO_CTRL_PWRG_MASK
127 | MCHP_GPIO_CTRL_BUFT_MASK | MCHP_GPIO_CTRL_DIR_MASK
128 | MCHP_GPIO_CTRL_AOD_MASK | BIT(MCHP_GPIO_CTRL_POL_POS)
129 | MCHP_GPIO_CTRL_MUX_MASK | MCHP_GPIO_CTRL_INPAD_DIS_MASK);
130
131 if (!(valid_ctrl_masks[config->port_num] & BIT(pin))) {
132 return -EINVAL;
133 }
134
135 int ret = gpio_xec_validate_flags(flags);
136
137 if (ret) {
138 return ret;
139 }
140
141 pcr1_addr = pin_ctrl_addr(dev, pin);
142 pcr1 = sys_read32(pcr1_addr);
143
144 if (flags == GPIO_DISCONNECTED) {
145 pcr1 = (pcr1 & ~MCHP_GPIO_CTRL_PWRG_MASK) | MCHP_GPIO_CTRL_PWRG_OFF;
146 sys_write32(pcr1, pcr1_addr);
147 return 0;
148 }
149
150 /* final pin state will be powered */
151 pcr1_new = MCHP_GPIO_CTRL_PWRG_VTR_IO;
152
153 /* always enable input pad */
154 if (pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)) {
155 pcr1 &= ~BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS);
156 sys_write32(pcr1, pcr1_addr);
157 }
158
159 if (flags & GPIO_OUTPUT) {
160 pcr1_new |= BIT(MCHP_GPIO_CTRL_DIR_POS);
161 msk |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
162 if (flags & GPIO_OUTPUT_INIT_HIGH) {
163 pcr1_new |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
164 } else if (flags & GPIO_OUTPUT_INIT_LOW) {
165 pcr1_new &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
166 } else { /* copy current input state to output state */
167 if ((pcr1 & MCHP_GPIO_CTRL_PWRG_MASK) == MCHP_GPIO_CTRL_PWRG_OFF) {
168 pcr1 &= ~(MCHP_GPIO_CTRL_PWRG_MASK);
169 pcr1 |= MCHP_GPIO_CTRL_PWRG_VTR_IO;
170 sys_write32(pcr1, pcr1_addr);
171 }
172 pcr1 = sys_read32(pcr1_addr);
173 if (pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) {
174 pcr1_new |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
175 } else {
176 pcr1_new &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
177 }
178 }
179 if (flags & GPIO_LINE_OPEN_DRAIN) {
180 pcr1_new |= BIT(MCHP_GPIO_CTRL_BUFT_POS);
181 }
182 }
183
184 if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
185 msk |= MCHP_GPIO_CTRL_PUD_MASK;
186 /* both bits specifies repeater mode */
187 if (flags & GPIO_PULL_UP) {
188 pcr1_new |= MCHP_GPIO_CTRL_PUD_PU;
189 }
190 if (flags & GPIO_PULL_DOWN) {
191 pcr1_new |= MCHP_GPIO_CTRL_PUD_PD;
192 }
193 }
194
195 /*
196 * Problem, if pin was power gated off we can't read input.
197 * How to turn on pin to read input but not glitch it?
198 */
199 pcr1 = (pcr1 & ~msk) | (pcr1_new & msk);
200 sys_write32(pcr1, pcr1_addr); /* configuration. may generate a single edge */
201 /* Control output bit becomes read-only and parallel out register bit becomes r/w */
202 sys_write32(pcr1 | BIT(MCHP_GPIO_CTRL_AOD_POS), pcr1_addr);
203
204 return 0;
205 }
206
gen_gpio_ctrl_icfg(enum gpio_int_mode mode,enum gpio_int_trig trig,uint32_t * pin_ctr1)207 static int gen_gpio_ctrl_icfg(enum gpio_int_mode mode, enum gpio_int_trig trig,
208 uint32_t *pin_ctr1)
209 {
210 if (!pin_ctr1) {
211 return -EINVAL;
212 }
213
214 if (mode == GPIO_INT_MODE_DISABLED) {
215 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_DISABLE;
216 } else {
217 if (mode == GPIO_INT_MODE_LEVEL) {
218 if (trig == GPIO_INT_TRIG_HIGH) {
219 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_LVL_HI;
220 } else {
221 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_LVL_LO;
222 }
223 } else {
224 switch (trig) {
225 case GPIO_INT_TRIG_LOW:
226 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_FEDGE;
227 break;
228 case GPIO_INT_TRIG_HIGH:
229 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_REDGE;
230 break;
231 case GPIO_INT_TRIG_BOTH:
232 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_BEDGE;
233 break;
234 default:
235 return -EINVAL;
236 }
237 }
238 }
239
240 return 0;
241 }
242
gpio_xec_intr_en(gpio_pin_t pin,enum gpio_int_mode mode,uint8_t girq_id)243 static void gpio_xec_intr_en(gpio_pin_t pin, enum gpio_int_mode mode,
244 uint8_t girq_id)
245 {
246 if (mode != GPIO_INT_MODE_DISABLED) {
247 /* Enable interrupt to propagate via its GIRQ to the NVIC */
248 mchp_soc_ecia_girq_src_en(girq_id, pin);
249 }
250 }
251
gpio_xec_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)252 static int gpio_xec_pin_interrupt_configure(const struct device *dev,
253 gpio_pin_t pin,
254 enum gpio_int_mode mode,
255 enum gpio_int_trig trig)
256 {
257 const struct gpio_xec_config *config = dev->config;
258 uintptr_t pcr1_addr = pin_ctrl_addr(dev, pin);
259 uint32_t pcr1 = 0u;
260 uint32_t pcr1_req = 0u;
261
262 /* Validate pin number range in terms of current port */
263 if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {
264 return -EINVAL;
265 }
266
267 /* Check if GPIO port supports interrupts */
268 if ((mode != GPIO_INT_MODE_DISABLED) &&
269 ((config->flags & GPIO_INT_ENABLE) == 0)) {
270 return -ENOTSUP;
271 }
272
273 pcr1_req = MCHP_GPIO_CTRL_IDET_DISABLE;
274 if (gen_gpio_ctrl_icfg(mode, trig, &pcr1_req)) {
275 return -EINVAL;
276 }
277
278 /* Disable interrupt in the EC aggregator */
279 mchp_soc_ecia_girq_src_dis(config->girq_id, pin);
280
281 /* pin configuration matches requested detection mode? */
282 pcr1 = sys_read32(pcr1_addr);
283 /* HW detects interrupt on input. Make sure input pad disable is cleared */
284 pcr1 &= ~BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS);
285
286 if ((pcr1 & MCHP_GPIO_CTRL_IDET_MASK) == pcr1_req) {
287 gpio_xec_intr_en(pin, mode, config->girq_id);
288 return 0;
289 }
290
291 pcr1 &= ~MCHP_GPIO_CTRL_IDET_MASK;
292
293 if (mode == GPIO_INT_MODE_LEVEL) {
294 if (trig == GPIO_INT_TRIG_HIGH) {
295 pcr1 |= MCHP_GPIO_CTRL_IDET_LVL_HI;
296 } else {
297 pcr1 |= MCHP_GPIO_CTRL_IDET_LVL_LO;
298 }
299 } else if (mode == GPIO_INT_MODE_EDGE) {
300 if (trig == GPIO_INT_TRIG_LOW) {
301 pcr1 |= MCHP_GPIO_CTRL_IDET_FEDGE;
302 } else if (trig == GPIO_INT_TRIG_HIGH) {
303 pcr1 |= MCHP_GPIO_CTRL_IDET_REDGE;
304 } else if (trig == GPIO_INT_TRIG_BOTH) {
305 pcr1 |= MCHP_GPIO_CTRL_IDET_BEDGE;
306 }
307 } else {
308 pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
309 }
310
311 sys_write32(pcr1, pcr1_addr);
312 /* delay for HW to synchronize after it ungates its clock */
313 for (int i = 0; i < XEC_GPIO_EDGE_DLY_COUNT; i++) {
314 sys_read32(pcr1_addr);
315 }
316
317 mchp_soc_ecia_girq_src_clr(config->girq_id, pin);
318
319 gpio_xec_intr_en(pin, mode, config->girq_id);
320
321 return 0;
322 }
323
gpio_xec_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)324 static int gpio_xec_port_set_masked_raw(const struct device *dev,
325 uint32_t mask,
326 uint32_t value)
327 {
328 uintptr_t pout_addr = pin_parout_addr(dev);
329
330 xec_mask_write32(pout_addr, mask, value);
331
332 return 0;
333 }
334
gpio_xec_port_set_bits_raw(const struct device * dev,uint32_t mask)335 static int gpio_xec_port_set_bits_raw(const struct device *dev, uint32_t mask)
336 {
337 uintptr_t pout_addr = pin_parout_addr(dev);
338
339 sys_write32(sys_read32(pout_addr) | mask, pout_addr);
340
341 return 0;
342 }
343
gpio_xec_port_clear_bits_raw(const struct device * dev,uint32_t mask)344 static int gpio_xec_port_clear_bits_raw(const struct device *dev,
345 uint32_t mask)
346 {
347 uintptr_t pout_addr = pin_parout_addr(dev);
348
349 sys_write32(sys_read32(pout_addr) & ~mask, pout_addr);
350
351 return 0;
352 }
353
gpio_xec_port_toggle_bits(const struct device * dev,uint32_t mask)354 static int gpio_xec_port_toggle_bits(const struct device *dev, uint32_t mask)
355 {
356 uintptr_t pout_addr = pin_parout_addr(dev);
357
358 sys_write32(sys_read32(pout_addr) ^ mask, pout_addr);
359
360 return 0;
361 }
362
gpio_xec_port_get_raw(const struct device * dev,uint32_t * value)363 static int gpio_xec_port_get_raw(const struct device *dev, uint32_t *value)
364 {
365 uintptr_t pin_addr = pin_parin_addr(dev);
366
367 *value = sys_read32(pin_addr);
368
369 return 0;
370 }
371
gpio_xec_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)372 static int gpio_xec_manage_callback(const struct device *dev,
373 struct gpio_callback *callback, bool set)
374 {
375 struct gpio_xec_data *data = dev->data;
376
377 gpio_manage_callback(&data->callbacks, callback, set);
378
379 return 0;
380 }
381
382 #ifdef CONFIG_GPIO_GET_DIRECTION
gpio_xec_get_direction(const struct device * port,gpio_port_pins_t map,gpio_port_pins_t * inputs,gpio_port_pins_t * outputs)383 static int gpio_xec_get_direction(const struct device *port, gpio_port_pins_t map,
384 gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
385 {
386 if (!port) {
387 return -EINVAL;
388 }
389
390 const struct gpio_xec_config *config = port->config;
391 uint32_t valid_msk = valid_ctrl_masks[config->port_num];
392
393 *inputs = 0u;
394 *outputs = 0u;
395 for (uint8_t pin = 0; pin < 32; pin++) {
396 if (!map) {
397 break;
398 }
399 if ((map & BIT(pin)) && (valid_msk & BIT(pin))) {
400 uintptr_t pcr1_addr = pin_ctrl_addr(port, pin);
401 uint32_t pcr1 = sys_read32(pcr1_addr);
402
403 if (!((pcr1 & MCHP_GPIO_CTRL_PWRG_MASK) == MCHP_GPIO_CTRL_PWRG_OFF)) {
404 if (outputs && (pcr1 & BIT(MCHP_GPIO_CTRL_DIR_POS))) {
405 *outputs |= BIT(pin);
406 } else if (inputs && !(pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS))) {
407 *inputs |= BIT(pin);
408 }
409 }
410
411 map &= ~BIT(pin);
412 }
413 }
414
415 return 0;
416 }
417 #endif
418
419 #ifdef CONFIG_GPIO_GET_CONFIG
gpio_xec_get_config(const struct device * port,gpio_pin_t pin,gpio_flags_t * flags)420 int gpio_xec_get_config(const struct device *port, gpio_pin_t pin, gpio_flags_t *flags)
421 {
422 if (!port || !flags) {
423 return -EINVAL;
424 }
425
426 const struct gpio_xec_config *config = port->config;
427 uint32_t valid_msk = valid_ctrl_masks[config->port_num];
428
429 if (!(valid_msk & BIT(pin))) {
430 return -EINVAL;
431 /* Or should we set *flags = GPIO_DISCONNECTED and return success? */
432 }
433
434 uintptr_t pcr1_addr = pin_ctrl_addr(port, pin);
435 uint32_t pcr1 = sys_read32(pcr1_addr);
436 uint32_t pin_flags = 0u;
437
438 if (pcr1 & BIT(MCHP_GPIO_CTRL_DIR_POS)) {
439 pin_flags |= GPIO_OUTPUT;
440 if (pcr1 & BIT(MCHP_GPIO_CTRL_OUTVAL_POS)) {
441 pin_flags |= GPIO_OUTPUT_INIT_HIGH;
442 } else {
443 pin_flags |= GPIO_OUTPUT_INIT_LOW;
444 }
445
446 if (pcr1 & BIT(MCHP_GPIO_CTRL_BUFT_POS)) {
447 pin_flags |= GPIO_OPEN_DRAIN;
448 }
449 } else if (!(pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS))) {
450 pin_flags |= GPIO_INPUT;
451 }
452
453 if (pin_flags) {
454 *flags = pin_flags;
455 } else {
456 *flags = GPIO_DISCONNECTED;
457 }
458
459 return 0;
460 }
461 #endif
462
gpio_gpio_xec_port_isr(const struct device * dev)463 static void gpio_gpio_xec_port_isr(const struct device *dev)
464 {
465 const struct gpio_xec_config *config = dev->config;
466 struct gpio_xec_data *data = dev->data;
467 uint32_t girq_result;
468
469 /*
470 * Figure out which interrupts have been triggered from the EC
471 * aggregator result register
472 */
473 girq_result = mchp_soc_ecia_girq_result(config->girq_id);
474
475 /* Clear source register in aggregator before firing callbacks */
476 mchp_soc_ecia_girq_src_clr_bitmap(config->girq_id, girq_result);
477
478 gpio_fire_callbacks(&data->callbacks, dev, girq_result);
479 }
480
481 /* GPIO driver official API table */
482 static const struct gpio_driver_api gpio_xec_driver_api = {
483 .pin_configure = gpio_xec_configure,
484 .port_get_raw = gpio_xec_port_get_raw,
485 .port_set_masked_raw = gpio_xec_port_set_masked_raw,
486 .port_set_bits_raw = gpio_xec_port_set_bits_raw,
487 .port_clear_bits_raw = gpio_xec_port_clear_bits_raw,
488 .port_toggle_bits = gpio_xec_port_toggle_bits,
489 .pin_interrupt_configure = gpio_xec_pin_interrupt_configure,
490 .manage_callback = gpio_xec_manage_callback,
491 #ifdef CONFIG_GPIO_GET_DIRECTION
492 .port_get_direction = gpio_xec_get_direction,
493 #endif
494 #ifdef CONFIG_GPIO_GET_CONFIG
495 .pin_get_config = gpio_xec_get_config,
496 #endif
497 };
498
499 #define XEC_GPIO_PORT_FLAGS(n) \
500 ((DT_INST_IRQ_HAS_CELL(n, irq)) ? GPIO_INT_ENABLE : 0)
501
502 #define XEC_GPIO_PORT(n) \
503 static int gpio_xec_port_init_##n(const struct device *dev) \
504 { \
505 if (!(DT_INST_IRQ_HAS_CELL(n, irq))) { \
506 return 0; \
507 } \
508 \
509 const struct gpio_xec_config *config = dev->config; \
510 \
511 mchp_soc_ecia_girq_aggr_en(config->girq_id, 1); \
512 \
513 IRQ_CONNECT(DT_INST_IRQN(n), \
514 DT_INST_IRQ(n, priority), \
515 gpio_gpio_xec_port_isr, \
516 DEVICE_DT_INST_GET(n), 0U); \
517 \
518 irq_enable(DT_INST_IRQN(n)); \
519 \
520 return 0; \
521 } \
522 \
523 static struct gpio_xec_data gpio_xec_port_data_##n; \
524 \
525 static const struct gpio_xec_config xec_gpio_config_##n = { \
526 .common = { \
527 .port_pin_mask = \
528 GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
529 }, \
530 .pcr1_base = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 0), \
531 .parin_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 1), \
532 .parout_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 2),\
533 .port_num = DT_INST_PROP(n, port_id), \
534 .girq_id = DT_INST_PROP_OR(n, girq_id, 0), \
535 .flags = XEC_GPIO_PORT_FLAGS(n), \
536 }; \
537 \
538 DEVICE_DT_INST_DEFINE(n, gpio_xec_port_init_##n, NULL, \
539 &gpio_xec_port_data_##n, &xec_gpio_config_##n, \
540 PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
541 &gpio_xec_driver_api);
542
543 DT_INST_FOREACH_STATUS_OKAY(XEC_GPIO_PORT)
544
