1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7 #include <errno.h>
8 #include <zephyr/device.h>
9 #include <zephyr/devicetree.h>
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
13 #include <zephyr/init.h>
14 #include <zephyr/irq.h>
15 #include <zephyr/types.h>
16 #include <zephyr/sys/util.h>
17 #include <string.h>
18 #include <zephyr/logging/log.h>
19 #include <zephyr/drivers/gpio/gpio_utils.h>
20
21 #include <chip_chipregs.h>
22 #include <soc_common.h>
23
24 LOG_MODULE_REGISTER(gpio_it8xxx2, LOG_LEVEL_ERR);
25
26 #define DT_DRV_COMPAT ite_it8xxx2_gpio
27
28 /*
29 * Structure gpio_ite_cfg is about the setting of gpio
30 * this config will be used at initial time
31 */
32 struct gpio_ite_cfg {
33 /* gpio_driver_config needs to be first */
34 struct gpio_driver_config common;
35 /* gpio port data register (bit mapping to pin) */
36 uintptr_t reg_gpdr;
37 /* gpio port control register (byte mapping to pin) */
38 uintptr_t reg_gpcr;
39 /* gpio port data mirror register (bit mapping to pin) */
40 uintptr_t reg_gpdmr;
41 /* gpio port output type register (bit mapping to pin) */
42 uintptr_t reg_gpotr;
43 /* Index in gpio_1p8v for voltage level control register element. */
44 uint8_t index;
45 /* gpio's irq */
46 uint8_t gpio_irq[8];
47 };
48
49 /* Structure gpio_ite_data is about callback function */
50 struct gpio_ite_data {
51 struct gpio_driver_data common;
52 sys_slist_t callbacks;
53 };
54
55 /* dev macros for GPIO */
56 #define DEV_GPIO_DATA(dev) \
57 ((struct gpio_ite_data *)(dev)->data)
58
59 #define DEV_GPIO_CFG(dev) \
60 ((const struct gpio_ite_cfg *)(dev)->config)
61
62 /**
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
64 * sense register (WUESR). Return pointer to the register.
65 *
66 * @param grp WUC group.
67 *
68 * @return Pointer to corresponding WUESR register.
69 */
wuesr(uint8_t grp)70 static volatile uint8_t *wuesr(uint8_t grp)
71 {
72 /*
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on
74 * the address increases by fours.
75 */
76 return (grp <= 4) ?
77 (volatile uint8_t *)(IT8XXX2_WUC_WUESR1 + grp-1) :
78 (volatile uint8_t *)(IT8XXX2_WUC_WUESR5 + 4*(grp-5));
79 }
80
81 /**
82 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
83 * mode register (WUEMR). Return pointer to the register.
84 *
85 * @param grp WUC group.
86 *
87 * @return Pointer to corresponding WUEMR register.
88 */
wuemr(uint8_t grp)89 static volatile uint8_t *wuemr(uint8_t grp)
90 {
91 /*
92 * From WUEMR1-WUEMR4, the address increases by ones. From WUEMR5 on
93 * the address increases by fours.
94 */
95 return (grp <= 4) ?
96 (volatile uint8_t *)(IT8XXX2_WUC_WUEMR1 + grp-1) :
97 (volatile uint8_t *)(IT8XXX2_WUC_WUEMR5 + 4*(grp-5));
98 }
99
100 /**
101 * Convert wake-up controller (WUC) group to the corresponding wake-up both edge
102 * mode register (WUBEMR). Return pointer to the register.
103 *
104 * @param grp WUC group.
105 *
106 * @return Pointer to corresponding WUBEMR register.
107 */
wubemr(uint8_t grp)108 static volatile uint8_t *wubemr(uint8_t grp)
109 {
110 /*
111 * From WUBEMR1-WUBEMR4, the address increases by ones. From WUBEMR5 on
112 * the address increases by fours.
113 */
114 return (grp <= 4) ?
115 (volatile uint8_t *)(IT8XXX2_WUC_WUBEMR1 + grp-1) :
116 (volatile uint8_t *)(IT8XXX2_WUC_WUBEMR5 + 4*(grp-5));
117 }
118
119 /*
120 * Array to store the corresponding GPIO WUC group and mask
121 * for each WUC interrupt. This allows GPIO interrupts coming in through WUC
122 * to easily identify which pin caused the interrupt.
123 */
124 static const struct {
125 uint8_t gpio_mask;
126 uint8_t wuc_group;
127 uint8_t wuc_mask;
128 } gpio_irqs[] = {
129 /* irq gpio_mask, wuc_group, wuc_mask */
130 [IT8XXX2_IRQ_WU20] = {BIT(0), 2, BIT(0)},
131 [IT8XXX2_IRQ_WU21] = {BIT(1), 2, BIT(1)},
132 [IT8XXX2_IRQ_WU22] = {BIT(4), 2, BIT(2)},
133 [IT8XXX2_IRQ_WU23] = {BIT(6), 2, BIT(3)},
134 [IT8XXX2_IRQ_WU24] = {BIT(2), 2, BIT(4)},
135 [IT8XXX2_IRQ_WU40] = {BIT(5), 4, BIT(0)},
136 [IT8XXX2_IRQ_WU45] = {BIT(6), 4, BIT(5)},
137 [IT8XXX2_IRQ_WU46] = {BIT(7), 4, BIT(6)},
138 [IT8XXX2_IRQ_WU50] = {BIT(0), 5, BIT(0)},
139 [IT8XXX2_IRQ_WU51] = {BIT(1), 5, BIT(1)},
140 [IT8XXX2_IRQ_WU52] = {BIT(2), 5, BIT(2)},
141 [IT8XXX2_IRQ_WU53] = {BIT(3), 5, BIT(3)},
142 [IT8XXX2_IRQ_WU54] = {BIT(4), 5, BIT(4)},
143 [IT8XXX2_IRQ_WU55] = {BIT(5), 5, BIT(5)},
144 [IT8XXX2_IRQ_WU56] = {BIT(6), 5, BIT(6)},
145 [IT8XXX2_IRQ_WU57] = {BIT(7), 5, BIT(7)},
146 [IT8XXX2_IRQ_WU60] = {BIT(0), 6, BIT(0)},
147 [IT8XXX2_IRQ_WU61] = {BIT(1), 6, BIT(1)},
148 [IT8XXX2_IRQ_WU62] = {BIT(2), 6, BIT(2)},
149 [IT8XXX2_IRQ_WU63] = {BIT(3), 6, BIT(3)},
150 [IT8XXX2_IRQ_WU64] = {BIT(4), 6, BIT(4)},
151 [IT8XXX2_IRQ_WU65] = {BIT(5), 6, BIT(5)},
152 [IT8XXX2_IRQ_WU66] = {BIT(6), 6, BIT(6)},
153 [IT8XXX2_IRQ_WU67] = {BIT(7), 6, BIT(7)},
154 [IT8XXX2_IRQ_WU70] = {BIT(0), 7, BIT(0)},
155 [IT8XXX2_IRQ_WU71] = {BIT(1), 7, BIT(1)},
156 [IT8XXX2_IRQ_WU72] = {BIT(2), 7, BIT(2)},
157 [IT8XXX2_IRQ_WU73] = {BIT(3), 7, BIT(3)},
158 [IT8XXX2_IRQ_WU74] = {BIT(4), 7, BIT(4)},
159 [IT8XXX2_IRQ_WU75] = {BIT(5), 7, BIT(5)},
160 [IT8XXX2_IRQ_WU76] = {BIT(6), 7, BIT(6)},
161 [IT8XXX2_IRQ_WU77] = {BIT(7), 7, BIT(7)},
162 [IT8XXX2_IRQ_WU80] = {BIT(3), 8, BIT(0)},
163 [IT8XXX2_IRQ_WU81] = {BIT(4), 8, BIT(1)},
164 [IT8XXX2_IRQ_WU82] = {BIT(5), 8, BIT(2)},
165 [IT8XXX2_IRQ_WU83] = {BIT(6), 8, BIT(3)},
166 [IT8XXX2_IRQ_WU84] = {BIT(2), 8, BIT(4)},
167 [IT8XXX2_IRQ_WU85] = {BIT(0), 8, BIT(5)},
168 [IT8XXX2_IRQ_WU86] = {BIT(7), 8, BIT(6)},
169 [IT8XXX2_IRQ_WU87] = {BIT(7), 8, BIT(7)},
170 [IT8XXX2_IRQ_WU88] = {BIT(4), 9, BIT(0)},
171 [IT8XXX2_IRQ_WU89] = {BIT(5), 9, BIT(1)},
172 [IT8XXX2_IRQ_WU90] = {BIT(6), 9, BIT(2)},
173 [IT8XXX2_IRQ_WU91] = {BIT(0), 9, BIT(3)},
174 [IT8XXX2_IRQ_WU92] = {BIT(1), 9, BIT(4)},
175 [IT8XXX2_IRQ_WU93] = {BIT(2), 9, BIT(5)},
176 [IT8XXX2_IRQ_WU94] = {BIT(4), 9, BIT(6)},
177 [IT8XXX2_IRQ_WU95] = {BIT(2), 9, BIT(7)},
178 [IT8XXX2_IRQ_WU96] = {BIT(0), 10, BIT(0)},
179 [IT8XXX2_IRQ_WU97] = {BIT(1), 10, BIT(1)},
180 [IT8XXX2_IRQ_WU98] = {BIT(2), 10, BIT(2)},
181 [IT8XXX2_IRQ_WU99] = {BIT(3), 10, BIT(3)},
182 [IT8XXX2_IRQ_WU100] = {BIT(7), 10, BIT(4)},
183 [IT8XXX2_IRQ_WU101] = {BIT(0), 10, BIT(5)},
184 [IT8XXX2_IRQ_WU102] = {BIT(1), 10, BIT(6)},
185 [IT8XXX2_IRQ_WU103] = {BIT(3), 10, BIT(7)},
186 [IT8XXX2_IRQ_WU104] = {BIT(5), 11, BIT(0)},
187 [IT8XXX2_IRQ_WU105] = {BIT(6), 11, BIT(1)},
188 [IT8XXX2_IRQ_WU106] = {BIT(7), 11, BIT(2)},
189 [IT8XXX2_IRQ_WU107] = {BIT(1), 11, BIT(3)},
190 [IT8XXX2_IRQ_WU108] = {BIT(3), 11, BIT(4)},
191 [IT8XXX2_IRQ_WU109] = {BIT(5), 11, BIT(5)},
192 [IT8XXX2_IRQ_WU110] = {BIT(3), 11, BIT(6)},
193 [IT8XXX2_IRQ_WU111] = {BIT(4), 11, BIT(7)},
194 [IT8XXX2_IRQ_WU112] = {BIT(5), 12, BIT(0)},
195 [IT8XXX2_IRQ_WU113] = {BIT(6), 12, BIT(1)},
196 [IT8XXX2_IRQ_WU114] = {BIT(4), 12, BIT(2)},
197 [IT8XXX2_IRQ_WU115] = {BIT(0), 12, BIT(3)},
198 [IT8XXX2_IRQ_WU116] = {BIT(1), 12, BIT(4)},
199 [IT8XXX2_IRQ_WU117] = {BIT(2), 12, BIT(5)},
200 [IT8XXX2_IRQ_WU118] = {BIT(6), 12, BIT(6)},
201 [IT8XXX2_IRQ_WU119] = {BIT(0), 12, BIT(7)},
202 [IT8XXX2_IRQ_WU120] = {BIT(1), 13, BIT(0)},
203 [IT8XXX2_IRQ_WU121] = {BIT(2), 13, BIT(1)},
204 [IT8XXX2_IRQ_WU122] = {BIT(3), 13, BIT(2)},
205 [IT8XXX2_IRQ_WU123] = {BIT(3), 13, BIT(3)},
206 [IT8XXX2_IRQ_WU124] = {BIT(4), 13, BIT(4)},
207 [IT8XXX2_IRQ_WU125] = {BIT(5), 13, BIT(5)},
208 [IT8XXX2_IRQ_WU126] = {BIT(7), 13, BIT(6)},
209 [IT8XXX2_IRQ_WU128] = {BIT(0), 14, BIT(0)},
210 [IT8XXX2_IRQ_WU129] = {BIT(1), 14, BIT(1)},
211 [IT8XXX2_IRQ_WU130] = {BIT(2), 14, BIT(2)},
212 [IT8XXX2_IRQ_WU131] = {BIT(3), 14, BIT(3)},
213 [IT8XXX2_IRQ_WU132] = {BIT(4), 14, BIT(4)},
214 [IT8XXX2_IRQ_WU133] = {BIT(5), 14, BIT(5)},
215 [IT8XXX2_IRQ_WU134] = {BIT(6), 14, BIT(6)},
216 [IT8XXX2_IRQ_WU135] = {BIT(7), 14, BIT(7)},
217 [IT8XXX2_IRQ_WU136] = {BIT(0), 15, BIT(0)},
218 [IT8XXX2_IRQ_WU137] = {BIT(1), 15, BIT(1)},
219 [IT8XXX2_IRQ_WU138] = {BIT(2), 15, BIT(2)},
220 [IT8XXX2_IRQ_WU139] = {BIT(3), 15, BIT(3)},
221 [IT8XXX2_IRQ_WU140] = {BIT(4), 15, BIT(4)},
222 [IT8XXX2_IRQ_WU141] = {BIT(5), 15, BIT(5)},
223 [IT8XXX2_IRQ_WU142] = {BIT(6), 15, BIT(6)},
224 [IT8XXX2_IRQ_WU143] = {BIT(7), 15, BIT(7)},
225 [IT8XXX2_IRQ_WU144] = {BIT(0), 16, BIT(0)},
226 [IT8XXX2_IRQ_WU145] = {BIT(1), 16, BIT(1)},
227 [IT8XXX2_IRQ_WU146] = {BIT(2), 16, BIT(2)},
228 [IT8XXX2_IRQ_WU147] = {BIT(3), 16, BIT(3)},
229 [IT8XXX2_IRQ_WU148] = {BIT(4), 16, BIT(4)},
230 [IT8XXX2_IRQ_WU149] = {BIT(5), 16, BIT(5)},
231 [IT8XXX2_IRQ_WU150] = {BIT(6), 16, BIT(6)},
232 [IT8XXX2_IRQ_COUNT] = { 0, 0, 0},
233 };
234 BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT8XXX2_IRQ_COUNT + 1);
235
236 /* 1.8v gpio group a, b, c, d, e, f, g, h, i, j, k, l, and m */
237 #define GPIO_GROUP_COUNT 13
238 #define GPIO_GROUP_INDEX(label) \
239 (uint8_t)(DT_REG_ADDR(DT_NODELABEL(label)) - \
240 DT_REG_ADDR(DT_NODELABEL(gpioa)))
241
242 /* general control registers for selecting 1.8V/3.3V */
243 static const struct {
244 uint8_t offset;
245 uint8_t mask_1p8v;
246 } gpio_1p8v[GPIO_GROUP_COUNT][8] = {
247 [GPIO_GROUP_INDEX(gpioa)] = {
248 [4] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(0)},
249 [5] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(1)},
250 [6] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(5)},
251 [7] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(6)} },
252 [GPIO_GROUP_INDEX(gpiob)] = {
253 [3] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(1)},
254 [4] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(0)},
255 [5] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(7)},
256 [6] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(6)},
257 [7] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(4)} },
258 [GPIO_GROUP_INDEX(gpioc)] = {
259 [0] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(7)},
260 [1] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(5)},
261 [2] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(4)},
262 [4] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(2)},
263 [6] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(3)},
264 [7] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(3)} },
265 [GPIO_GROUP_INDEX(gpiod)] = {
266 [0] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(2)},
267 [1] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(1)},
268 [2] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(0)},
269 [3] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(7)},
270 [4] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(6)},
271 [5] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(4)},
272 [6] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(5)},
273 [7] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(6)} },
274 [GPIO_GROUP_INDEX(gpioe)] = {
275 [0] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(5)},
276 [1] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(6)},
277 [2] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(7)},
278 [4] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(2)},
279 [5] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(3)},
280 [6] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(4)},
281 [7] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(3)} },
282 [GPIO_GROUP_INDEX(gpiof)] = {
283 [0] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(4)},
284 [1] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(5)},
285 [2] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(2)},
286 [3] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(1)},
287 [4] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(0)},
288 [5] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(7)},
289 [6] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(6)},
290 [7] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(5)} },
291 [GPIO_GROUP_INDEX(gpiog)] = {
292 [0] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(2)},
293 [1] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(4)},
294 [2] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(3)},
295 [6] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(3)} },
296 [GPIO_GROUP_INDEX(gpioh)] = {
297 [0] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(2)},
298 [1] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(1)},
299 [2] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(0)},
300 [5] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(7)},
301 [6] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(0)} },
302 [GPIO_GROUP_INDEX(gpioi)] = {
303 [0] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(3)},
304 [1] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(4)},
305 [2] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(5)},
306 [3] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(6)},
307 [4] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(7)},
308 [5] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(4)},
309 [6] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(5)},
310 [7] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(6)} },
311 [GPIO_GROUP_INDEX(gpioj)] = {
312 [0] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(0)},
313 [1] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(1)},
314 [2] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(2)},
315 [3] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(3)},
316 [4] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(0)},
317 [5] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(1)},
318 [6] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(2)},
319 [7] = {IT8XXX2_GPIO_GCR33_OFFSET, BIT(2)} },
320 [GPIO_GROUP_INDEX(gpiok)] = {
321 [0] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(0)},
322 [1] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(1)},
323 [2] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(2)},
324 [3] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(3)},
325 [4] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(4)},
326 [5] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(5)},
327 [6] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(6)},
328 [7] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(7)} },
329 [GPIO_GROUP_INDEX(gpiol)] = {
330 [0] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(0)},
331 [1] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(1)},
332 [2] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(2)},
333 [3] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(3)},
334 [4] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(4)},
335 [5] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(5)},
336 [6] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(6)},
337 [7] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(7)} },
338 /*
339 * M group's voltage level is according to chip's VCC is connected
340 * to 1.8V or 3.3V.
341 */
342 [GPIO_GROUP_INDEX(gpiom)] = {
343 [0] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
344 [1] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
345 [2] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
346 [3] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
347 [4] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
348 [5] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
349 [6] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)} },
350 };
351
352 /**
353 * Driver functions
354 */
gpio_ite_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)355 static int gpio_ite_configure(const struct device *dev,
356 gpio_pin_t pin,
357 gpio_flags_t flags)
358 {
359 const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
360
361 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
362 volatile uint8_t *reg_gpcr = (uint8_t *)(gpio_config->reg_gpcr + pin);
363 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
364 volatile uint8_t *reg_1p8v;
365 volatile uint8_t mask_1p8v;
366 uint8_t mask = BIT(pin);
367
368 __ASSERT(gpio_config->index < GPIO_GROUP_COUNT,
369 "Invalid GPIO group index");
370
371 /* Don't support "open source" mode */
372 if (((flags & GPIO_SINGLE_ENDED) != 0) &&
373 ((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
374 return -ENOTSUP;
375 }
376
377 if (flags == GPIO_DISCONNECTED) {
378 *reg_gpcr = GPCR_PORT_PIN_MODE_TRISTATE;
379 /*
380 * Since not all GPIOs can be to configured as tri-state,
381 * prompt error if pin doesn't support the flag.
382 */
383 if (*reg_gpcr != GPCR_PORT_PIN_MODE_TRISTATE) {
384 /* Go back to default setting (input) */
385 *reg_gpcr = GPCR_PORT_PIN_MODE_INPUT;
386 LOG_ERR("Cannot config GPIO-%c%d as tri-state",
387 (gpio_config->index + 'A'), pin);
388 return -ENOTSUP;
389 }
390 /*
391 * The following configuration isn't necessary because the pin
392 * was configured as disconnected.
393 */
394 return 0;
395 }
396
397 /*
398 * Select open drain first, so that we don't glitch the signal
399 * when changing the line to an output.
400 */
401 if (flags & GPIO_OPEN_DRAIN) {
402 *reg_gpotr |= mask;
403 } else {
404 *reg_gpotr &= ~mask;
405 }
406
407 /* 1.8V or 3.3V */
408 reg_1p8v = &IT8XXX2_GPIO_GCRX(
409 gpio_1p8v[gpio_config->index][pin].offset);
410 mask_1p8v = gpio_1p8v[gpio_config->index][pin].mask_1p8v;
411 if (reg_1p8v != &IT8XXX2_GPIO_GCRX(0)) {
412 gpio_flags_t volt = flags & IT8XXX2_GPIO_VOLTAGE_MASK;
413
414 if (volt == IT8XXX2_GPIO_VOLTAGE_1P8) {
415 __ASSERT(!(flags & GPIO_PULL_UP),
416 "Don't enable internal pullup if 1.8V voltage is used");
417 *reg_1p8v |= mask_1p8v;
418 } else if (volt == IT8XXX2_GPIO_VOLTAGE_3P3 ||
419 volt == IT8XXX2_GPIO_VOLTAGE_DEFAULT) {
420 *reg_1p8v &= ~mask_1p8v;
421 } else {
422 return -EINVAL;
423 }
424 }
425
426 /* If output, set level before changing type to an output. */
427 if (flags & GPIO_OUTPUT) {
428 if (flags & GPIO_OUTPUT_INIT_HIGH) {
429 *reg_gpdr |= mask;
430 } else if (flags & GPIO_OUTPUT_INIT_LOW) {
431 *reg_gpdr &= ~mask;
432 }
433 }
434
435 /* Set input or output. */
436 if (flags & GPIO_OUTPUT)
437 *reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_OUTPUT) &
438 ~GPCR_PORT_PIN_MODE_INPUT;
439 else
440 *reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
441 ~GPCR_PORT_PIN_MODE_OUTPUT;
442
443 /* Handle pullup / pulldown */
444 if (flags & GPIO_PULL_UP) {
445 *reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
446 ~GPCR_PORT_PIN_MODE_PULLDOWN;
447 } else if (flags & GPIO_PULL_DOWN) {
448 *reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) &
449 ~GPCR_PORT_PIN_MODE_PULLUP;
450 } else {
451 /* No pull up/down */
452 *reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
453 GPCR_PORT_PIN_MODE_PULLDOWN);
454 }
455
456 return 0;
457 }
458
459 #ifdef CONFIG_GPIO_GET_CONFIG
gpio_ite_get_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t * out_flags)460 static int gpio_ite_get_config(const struct device *dev,
461 gpio_pin_t pin,
462 gpio_flags_t *out_flags)
463 {
464 const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
465
466 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
467 volatile uint8_t *reg_gpcr = (uint8_t *)(gpio_config->reg_gpcr + pin);
468 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
469 volatile uint8_t *reg_1p8v;
470 volatile uint8_t mask_1p8v;
471 uint8_t mask = BIT(pin);
472 gpio_flags_t flags = 0;
473
474 __ASSERT(gpio_config->index < GPIO_GROUP_COUNT,
475 "Invalid GPIO group index");
476
477 /* push-pull or open-drain */
478 if (*reg_gpotr & mask)
479 flags |= GPIO_OPEN_DRAIN;
480
481 /* 1.8V or 3.3V */
482 reg_1p8v = &IT8XXX2_GPIO_GCRX(
483 gpio_1p8v[gpio_config->index][pin].offset);
484 /*
485 * Since not all GPIOs support voltage selection, voltage flag
486 * is only set if voltage selection register is present.
487 */
488 if (reg_1p8v != &IT8XXX2_GPIO_GCRX(0)) {
489 mask_1p8v = gpio_1p8v[gpio_config->index][pin].mask_1p8v;
490 if (*reg_1p8v & mask_1p8v) {
491 flags |= IT8XXX2_GPIO_VOLTAGE_1P8;
492 } else {
493 flags |= IT8XXX2_GPIO_VOLTAGE_3P3;
494 }
495 }
496
497 /* set input or output. */
498 if (*reg_gpcr & GPCR_PORT_PIN_MODE_OUTPUT) {
499 flags |= GPIO_OUTPUT;
500
501 /* set level */
502 if (*reg_gpdr & mask) {
503 flags |= GPIO_OUTPUT_HIGH;
504 } else {
505 flags |= GPIO_OUTPUT_LOW;
506 }
507 }
508
509 if (*reg_gpcr & GPCR_PORT_PIN_MODE_INPUT) {
510 flags |= GPIO_INPUT;
511
512 /* pullup / pulldown */
513 if (*reg_gpcr & GPCR_PORT_PIN_MODE_PULLUP) {
514 flags |= GPIO_PULL_UP;
515 }
516
517 if (*reg_gpcr & GPCR_PORT_PIN_MODE_PULLDOWN) {
518 flags |= GPIO_PULL_DOWN;
519 }
520 }
521
522 *out_flags = flags;
523
524 return 0;
525 }
526 #endif
527
gpio_ite_port_get_raw(const struct device * dev,gpio_port_value_t * value)528 static int gpio_ite_port_get_raw(const struct device *dev,
529 gpio_port_value_t *value)
530 {
531 const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
532 volatile uint8_t *reg_gpdmr = (uint8_t *)gpio_config->reg_gpdmr;
533
534 /* Get raw bits of GPIO mirror register */
535 *value = *reg_gpdmr;
536
537 return 0;
538 }
539
gpio_ite_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)540 static int gpio_ite_port_set_masked_raw(const struct device *dev,
541 gpio_port_pins_t mask,
542 gpio_port_value_t value)
543 {
544 const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
545 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
546 uint8_t out = *reg_gpdr;
547
548 *reg_gpdr = ((out & ~mask) | (value & mask));
549
550 return 0;
551 }
552
gpio_ite_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)553 static int gpio_ite_port_set_bits_raw(const struct device *dev,
554 gpio_port_pins_t pins)
555 {
556 const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
557 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
558
559 /* Set raw bits of GPIO data register */
560 *reg_gpdr |= pins;
561
562 return 0;
563 }
564
gpio_ite_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)565 static int gpio_ite_port_clear_bits_raw(const struct device *dev,
566 gpio_port_pins_t pins)
567 {
568 const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
569 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
570
571 /* Clear raw bits of GPIO data register */
572 *reg_gpdr &= ~pins;
573
574 return 0;
575 }
576
gpio_ite_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)577 static int gpio_ite_port_toggle_bits(const struct device *dev,
578 gpio_port_pins_t pins)
579 {
580 const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
581 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
582
583 /* Toggle raw bits of GPIO data register */
584 *reg_gpdr ^= pins;
585
586 return 0;
587 }
588
gpio_ite_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)589 static int gpio_ite_manage_callback(const struct device *dev,
590 struct gpio_callback *callback,
591 bool set)
592 {
593 struct gpio_ite_data *data = DEV_GPIO_DATA(dev);
594
595 return gpio_manage_callback(&data->callbacks, callback, set);
596 }
597
gpio_ite_isr(const void * arg)598 static void gpio_ite_isr(const void *arg)
599 {
600 uint8_t irq = ite_intc_get_irq_num();
601 const struct device *dev = arg;
602 struct gpio_ite_data *data = DEV_GPIO_DATA(dev);
603 uint8_t gpio_mask = gpio_irqs[irq].gpio_mask;
604
605 if (gpio_irqs[irq].wuc_group) {
606 /* Clear the WUC status register. */
607 *(wuesr(gpio_irqs[irq].wuc_group)) = gpio_irqs[irq].wuc_mask;
608 gpio_fire_callbacks(&data->callbacks, dev, gpio_mask);
609 }
610 }
611
gpio_ite_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)612 static int gpio_ite_pin_interrupt_configure(const struct device *dev,
613 gpio_pin_t pin,
614 enum gpio_int_mode mode,
615 enum gpio_int_trig trig)
616 {
617 const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
618 uint8_t gpio_irq = gpio_config->gpio_irq[pin];
619
620 #ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
621 if (mode == GPIO_INT_MODE_DISABLED || mode == GPIO_INT_MODE_DISABLE_ONLY) {
622 #else
623 if (mode == GPIO_INT_MODE_DISABLED) {
624 #endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
625 /* Disable GPIO interrupt */
626 irq_disable(gpio_irq);
627 return 0;
628 #ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
629 } else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
630 /* Only enable GPIO interrupt */
631 irq_enable(gpio_irq);
632 return 0;
633 #endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
634 }
635
636 if (mode == GPIO_INT_MODE_LEVEL) {
637 LOG_ERR("Level trigger mode not supported");
638 return -ENOTSUP;
639 }
640
641 /* Disable irq before configuring it */
642 irq_disable(gpio_irq);
643
644 if (trig & GPIO_INT_TRIG_BOTH) {
645 uint8_t wuc_group = gpio_irqs[gpio_irq].wuc_group;
646 uint8_t wuc_mask = gpio_irqs[gpio_irq].wuc_mask;
647
648 /* Set both edges interrupt. */
649 if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH) {
650 *(wubemr(wuc_group)) |= wuc_mask;
651 } else {
652 *(wubemr(wuc_group)) &= ~wuc_mask;
653 }
654
655 if (trig & GPIO_INT_TRIG_LOW) {
656 *(wuemr(wuc_group)) |= wuc_mask;
657 } else {
658 *(wuemr(wuc_group)) &= ~wuc_mask;
659 }
660 /*
661 * Always write 1 to clear the WUC status register after
662 * modifying edge mode selection register (WUBEMR and WUEMR).
663 */
664 *(wuesr(wuc_group)) = wuc_mask;
665 }
666
667 /* Enable GPIO interrupt */
668 irq_connect_dynamic(gpio_irq, 0, gpio_ite_isr, dev, 0);
669 irq_enable(gpio_irq);
670
671 return 0;
672 }
673
674 static const struct gpio_driver_api gpio_ite_driver_api = {
675 .pin_configure = gpio_ite_configure,
676 #ifdef CONFIG_GPIO_GET_CONFIG
677 .pin_get_config = gpio_ite_get_config,
678 #endif
679 .port_get_raw = gpio_ite_port_get_raw,
680 .port_set_masked_raw = gpio_ite_port_set_masked_raw,
681 .port_set_bits_raw = gpio_ite_port_set_bits_raw,
682 .port_clear_bits_raw = gpio_ite_port_clear_bits_raw,
683 .port_toggle_bits = gpio_ite_port_toggle_bits,
684 .pin_interrupt_configure = gpio_ite_pin_interrupt_configure,
685 .manage_callback = gpio_ite_manage_callback,
686 };
687
688 #define GPIO_ITE_DEV_CFG_DATA(inst) \
689 static struct gpio_ite_data gpio_ite_data_##inst; \
690 static const struct gpio_ite_cfg gpio_ite_cfg_##inst = { \
691 .common = { \
692 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS( \
693 DT_INST_PROP(inst, ngpios)) \
694 }, \
695 .reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
696 .reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
697 .reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
698 .reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
699 .index = (uint8_t)(DT_INST_REG_ADDR(inst) - \
700 DT_REG_ADDR(DT_NODELABEL(gpioa))), \
701 .gpio_irq[0] = DT_INST_IRQ_BY_IDX(inst, 0, irq), \
702 .gpio_irq[1] = DT_INST_IRQ_BY_IDX(inst, 1, irq), \
703 .gpio_irq[2] = DT_INST_IRQ_BY_IDX(inst, 2, irq), \
704 .gpio_irq[3] = DT_INST_IRQ_BY_IDX(inst, 3, irq), \
705 .gpio_irq[4] = DT_INST_IRQ_BY_IDX(inst, 4, irq), \
706 .gpio_irq[5] = DT_INST_IRQ_BY_IDX(inst, 5, irq), \
707 .gpio_irq[6] = DT_INST_IRQ_BY_IDX(inst, 6, irq), \
708 .gpio_irq[7] = DT_INST_IRQ_BY_IDX(inst, 7, irq), \
709 }; \
710 DEVICE_DT_INST_DEFINE(inst, \
711 NULL, \
712 NULL, \
713 &gpio_ite_data_##inst, \
714 &gpio_ite_cfg_##inst, \
715 PRE_KERNEL_1, \
716 CONFIG_GPIO_INIT_PRIORITY, \
717 &gpio_ite_driver_api);
718
719 DT_INST_FOREACH_STATUS_OKAY(GPIO_ITE_DEV_CFG_DATA)
720
721 static int gpio_it8xxx2_init_set(void)
722 {
723
724 if (IS_ENABLED(CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN)) {
725 const struct device *const gpiok = DEVICE_DT_GET(DT_NODELABEL(gpiok));
726 const struct device *const gpiol = DEVICE_DT_GET(DT_NODELABEL(gpiol));
727
728 for (int i = 0; i < 8; i++) {
729 gpio_pin_configure(gpiok, i, GPIO_INPUT | GPIO_PULL_DOWN);
730 gpio_pin_configure(gpiol, i, GPIO_INPUT | GPIO_PULL_DOWN);
731 }
732 }
733
734 if (IS_ENABLED(CONFIG_SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW)) {
735 const struct device *const gpioh = DEVICE_DT_GET(DT_NODELABEL(gpioh));
736
737 gpio_pin_configure(gpioh, 7, GPIO_OUTPUT_LOW);
738 }
739
740 return 0;
741 }
742 SYS_INIT(gpio_it8xxx2_init_set, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY);
743
