1 /*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 /**
9 * @brief GPIO driver for Infineon CAT1 MCU family.
10 *
11 * Note:
12 * - Trigger detection on pin rising or falling edge (GPIO_INT_TRIG_BOTH)
13 * is not supported in current version of GPIO CAT1 driver.
14 */
15
16 #define DT_DRV_COMPAT infineon_cat1_gpio
17
18 #include <zephyr/drivers/gpio.h>
19 #include <zephyr/drivers/gpio/gpio_utils.h>
20
21 #include <cyhal_gpio.h>
22 #include <cyhal_hwmgr.h>
23 #include <cy_gpio.h>
24
25 #include <zephyr/logging/log.h>
26 LOG_MODULE_REGISTER(gpio_cat1, CONFIG_GPIO_LOG_LEVEL);
27
28 /* Device config structure */
29 struct gpio_cat1_config {
30 /* gpio_driver_config needs to be first */
31 struct gpio_driver_config common;
32 cyhal_gpio_callback_data_t *cb_data_ptr;
33 GPIO_PRT_Type *regs;
34 uint8_t ngpios;
35 uint8_t intr_priority;
36 };
37
38 /* Data structure */
39 struct gpio_cat1_data {
40 /* gpio_driver_data needs to be first */
41 struct gpio_driver_data common;
42
43 /* device's owner of this data */
44 const struct device *dev;
45
46 /* callbacks list */
47 sys_slist_t callbacks;
48 };
49
50 /* Get port number by calculation difference from current port address minus
51 * GPIO base address divided by GPIO structure size.
52 */
53 #define GET_PORT_NUM(dev) \
54 (((uint32_t) ((const struct gpio_cat1_config *const) \
55 (dev)->config)->regs - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE)
56
57 #define GET_DEV_OBJ_FROM_LIST(i, _) \
58 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio_prt##i))
59
60 /* Map port number to device object */
61 static const struct device *const port_dev_obj[IOSS_GPIO_GPIO_PORT_NR] = {
62 LISTIFY(15, GET_DEV_OBJ_FROM_LIST, (,))
63 };
64
gpio_cat1_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)65 static int gpio_cat1_configure(const struct device *dev,
66 gpio_pin_t pin, gpio_flags_t flags)
67 {
68 cy_rslt_t status;
69 cyhal_gpio_t gpio_pin = CYHAL_GET_GPIO(GET_PORT_NUM(dev), pin);
70 cyhal_gpio_drive_mode_t gpio_mode = CYHAL_GPIO_DRIVE_NONE;
71 cyhal_gpio_direction_t gpio_dir = CYHAL_GPIO_DIR_INPUT;
72 bool pin_val = false;
73
74 switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) {
75 case GPIO_INPUT:
76 gpio_dir = CYHAL_GPIO_DIR_INPUT;
77
78 if ((flags & GPIO_PULL_UP) && (flags & GPIO_PULL_DOWN)) {
79 gpio_mode = CYHAL_GPIO_DRIVE_PULLUPDOWN;
80 } else if (flags & GPIO_PULL_UP) {
81 gpio_mode = CYHAL_GPIO_DRIVE_PULLUP;
82 pin_val = true;
83 } else if (flags & GPIO_PULL_DOWN) {
84 gpio_mode = CYHAL_GPIO_DRIVE_PULLDOWN;
85 } else {
86 gpio_mode = CYHAL_GPIO_DRIVE_NONE;
87 }
88 break;
89
90 case GPIO_OUTPUT:
91 gpio_dir = CYHAL_GPIO_DIR_OUTPUT;
92 if (flags & GPIO_SINGLE_ENDED) {
93 if (flags & GPIO_LINE_OPEN_DRAIN) {
94 gpio_mode = CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW;
95 pin_val = true;
96 } else {
97 gpio_mode = CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH;
98 pin_val = false;
99 }
100 } else {
101 gpio_mode = CYHAL_GPIO_DRIVE_STRONG;
102 pin_val = (flags & GPIO_OUTPUT_INIT_HIGH) ? true : false;
103 }
104 break;
105
106 case GPIO_DISCONNECTED:
107 /* Handle this after calling cyhal_gpio_init(), otherwise it will cause an assert
108 * from HAL for freeing an uninitialized pin
109 */
110 break;
111
112 default:
113 return -ENOTSUP;
114 }
115
116 status = cyhal_gpio_init(gpio_pin, gpio_dir, gpio_mode, pin_val);
117
118 /* If the gpio requested resource is already in use, try to free and
119 * initialize again
120 */
121 if (status == CYHAL_HWMGR_RSLT_ERR_INUSE) {
122 cyhal_gpio_free(gpio_pin);
123 status = cyhal_gpio_init(gpio_pin, gpio_dir, gpio_mode, pin_val);
124 }
125
126 if (flags & GPIO_DISCONNECTED) {
127 cyhal_gpio_free(gpio_pin);
128 }
129
130 return (status == CY_RSLT_SUCCESS) ? 0 : -EIO;
131
132 }
133
gpio_cat1_port_get_raw(const struct device * dev,uint32_t * value)134 static int gpio_cat1_port_get_raw(const struct device *dev,
135 uint32_t *value)
136 {
137 const struct gpio_cat1_config *const cfg = dev->config;
138 GPIO_PRT_Type *const base = cfg->regs;
139
140 *value = GPIO_PRT_IN(base);
141
142 return 0;
143 }
144
gpio_cat1_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)145 static int gpio_cat1_port_set_masked_raw(const struct device *dev,
146 uint32_t mask, uint32_t value)
147 {
148 const struct gpio_cat1_config *const cfg = dev->config;
149 GPIO_PRT_Type *const base = cfg->regs;
150
151 GPIO_PRT_OUT(base) = (GPIO_PRT_OUT(base) & ~mask) | (mask & value);
152
153 return 0;
154 }
155
gpio_cat1_port_set_bits_raw(const struct device * dev,uint32_t mask)156 static int gpio_cat1_port_set_bits_raw(const struct device *dev,
157 uint32_t mask)
158 {
159 const struct gpio_cat1_config *const cfg = dev->config;
160 GPIO_PRT_Type *const base = cfg->regs;
161
162 GPIO_PRT_OUT_SET(base) = mask;
163
164 return 0;
165 }
166
gpio_cat1_port_clear_bits_raw(const struct device * dev,uint32_t mask)167 static int gpio_cat1_port_clear_bits_raw(const struct device *dev,
168 uint32_t mask)
169 {
170 const struct gpio_cat1_config *const cfg = dev->config;
171 GPIO_PRT_Type *const base = cfg->regs;
172
173 GPIO_PRT_OUT_CLR(base) = mask;
174
175 return 0;
176 }
177
gpio_cat1_port_toggle_bits(const struct device * dev,uint32_t mask)178 static int gpio_cat1_port_toggle_bits(const struct device *dev,
179 uint32_t mask)
180 {
181 const struct gpio_cat1_config *const cfg = dev->config;
182 GPIO_PRT_Type *const base = cfg->regs;
183
184 GPIO_PRT_OUT_INV(base) = mask;
185
186 return 0;
187 }
188
gpio_cat1_get_pending_int(const struct device * dev)189 static uint32_t gpio_cat1_get_pending_int(const struct device *dev)
190 {
191 const struct gpio_cat1_config *const cfg = dev->config;
192 GPIO_PRT_Type *const base = cfg->regs;
193
194 return GPIO_PRT_INTR_MASKED(base);
195 }
196
gpio_event_callback(void * callback_arg,cyhal_gpio_event_t event)197 static void gpio_event_callback(void *callback_arg, cyhal_gpio_event_t event)
198 {
199 ARG_UNUSED(event);
200 uint32_t port_num = CYHAL_GET_PORT((uint32_t) callback_arg);
201 uint32_t pin_num = CYHAL_GET_PIN((uint32_t) callback_arg);
202 const struct device *dev = port_dev_obj[port_num];
203
204 /* Goes through and fires callback from a callback list */
205 if (dev) {
206 gpio_fire_callbacks(&((struct gpio_cat1_data *const)(dev)->data)->callbacks,
207 dev, 1 << pin_num);
208 }
209 /* NOTE: cyhal gpio handles cleaning of interrupts */
210 }
211
gpio_cat1_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)212 static int gpio_cat1_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
213 enum gpio_int_mode mode, enum gpio_int_trig trig)
214 {
215 const struct gpio_cat1_config *const cfg = dev->config;
216 cyhal_gpio_callback_data_t *cb_data_ptr = cfg->cb_data_ptr;
217 cyhal_gpio_event_t event = CYHAL_GPIO_IRQ_NONE;
218
219 /* Level interrupts (GPIO_INT_MODE_LEVEL) is not supported */
220 if (mode == GPIO_INT_MODE_LEVEL) {
221 return -ENOTSUP;
222 }
223
224 switch (trig) {
225 case GPIO_INT_TRIG_LOW:
226 event = CYHAL_GPIO_IRQ_FALL;
227 break;
228
229 case GPIO_INT_TRIG_HIGH:
230 event = CYHAL_GPIO_IRQ_RISE;
231 break;
232
233 case GPIO_INT_TRIG_BOTH:
234 /* Trigger detection on pin rising or falling edge (GPIO_INT_TRIG_BOTH)
235 * is not supported. Refer to SWINTEGRATION-696
236 */
237 /* event = CYHAL_GPIO_IRQ_BOTH; */
238 return -ENOTSUP;
239
240 default:
241 return -ENOTSUP;
242 }
243
244 cyhal_gpio_t gpio_pin = CYHAL_GET_GPIO(GET_PORT_NUM(dev), pin);
245
246 /* Find index of free callback data structure */
247 uint32_t index;
248
249 for (index = 0u; index < cfg->ngpios; index++) {
250 if ((cb_data_ptr[index].callback == NULL) || (cb_data_ptr[index].pin == gpio_pin)) {
251 break;
252 }
253 }
254
255 if (index != cfg->ngpios) {
256 /* Store callback data: gpio callback and gpio device driver handle */
257 cb_data_ptr[index].callback = &gpio_event_callback;
258 cb_data_ptr[index].callback_arg = (void *)(gpio_pin);
259
260 /* Register/clear a callback handler for pin events */
261 cyhal_gpio_register_callback(gpio_pin, (mode == GPIO_INT_MODE_DISABLED) ?
262 NULL : &cb_data_ptr[index]);
263
264 /* Enable/disable the specified GPIO event */
265 cyhal_gpio_enable_event(gpio_pin, event, cfg->intr_priority,
266 (mode == GPIO_INT_MODE_DISABLED) ? false : true);
267 return 0;
268 } else {
269 return -EINVAL;
270 }
271 }
272
gpio_cat1_manage_callback(const struct device * port,struct gpio_callback * callback,bool set)273 static int gpio_cat1_manage_callback(const struct device *port,
274 struct gpio_callback *callback,
275 bool set)
276 {
277 return gpio_manage_callback(&((struct gpio_cat1_data *const)(port)->data)->callbacks,
278 callback, set);
279 }
280
281 static const struct gpio_driver_api gpio_cat1_api = {
282 .pin_configure = gpio_cat1_configure,
283 .port_get_raw = gpio_cat1_port_get_raw,
284 .port_set_masked_raw = gpio_cat1_port_set_masked_raw,
285 .port_set_bits_raw = gpio_cat1_port_set_bits_raw,
286 .port_clear_bits_raw = gpio_cat1_port_clear_bits_raw,
287 .port_toggle_bits = gpio_cat1_port_toggle_bits,
288 .pin_interrupt_configure = gpio_cat1_pin_interrupt_configure,
289 .manage_callback = gpio_cat1_manage_callback,
290 .get_pending_int = gpio_cat1_get_pending_int,
291 };
292
293 #define GPIO_CAT1_INIT(n) \
294 \
295 cyhal_gpio_callback_data_t \
296 _cat1_gpio##n##_cb_data[DT_INST_PROP(n, ngpios)]; \
297 \
298 static const struct gpio_cat1_config _cat1_gpio##n##_config = { \
299 .common = { \
300 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
301 }, \
302 .intr_priority = DT_INST_IRQ_BY_IDX(n, 0, priority), \
303 .cb_data_ptr = _cat1_gpio##n##_cb_data, \
304 .ngpios = DT_INST_PROP(n, ngpios), \
305 .regs = (GPIO_PRT_Type *)DT_INST_REG_ADDR(n), \
306 }; \
307 \
308 static struct gpio_cat1_data _cat1_gpio##n##_data; \
309 \
310 DEVICE_DT_INST_DEFINE(n, NULL, NULL, &_cat1_gpio##n##_data, \
311 &_cat1_gpio##n##_config, POST_KERNEL, \
312 CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
313 &gpio_cat1_api);
314
315 DT_INST_FOREACH_STATUS_OKAY(GPIO_CAT1_INIT)
316
