1 /***************************************************************************//** 2 * \file gpio_fx3g2_104_lga.h 3 * 4 * \brief 5 * FX3G2 device GPIO header for 104-LGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_FX3G2_104_LGA_H_ 28 #define _GPIO_FX3G2_104_LGA_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_LGA, 36 CY_GPIO_PACKAGE_CSP, 37 CY_GPIO_PACKAGE_WLCSP, 38 CY_GPIO_PACKAGE_LQFP, 39 CY_GPIO_PACKAGE_TQFP, 40 CY_GPIO_PACKAGE_TEQFP, 41 CY_GPIO_PACKAGE_SMT, 42 }; 43 44 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_LGA 45 #define CY_GPIO_PIN_COUNT 104u 46 47 /* AMUXBUS Segments */ 48 enum 49 { 50 AMUXBUS_FLASH, 51 AMUXBUS_LVDS, 52 AMUXBUS_MAIN, 53 AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, 54 AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, 55 }; 56 57 /* AMUX Splitter Controls */ 58 typedef enum 59 { 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_LVDS */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_FLASH; Right = AMUXBUS_MAIN */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 1 (GPIO) */ 66 #define P1_0_PORT GPIO_PRT1 67 #define P1_0_PIN 0u 68 #define P1_0_NUM 0u 69 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 70 #define P1_1_PORT GPIO_PRT1 71 #define P1_1_PIN 1u 72 #define P1_1_NUM 1u 73 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 74 75 /* PORT 4 (GPIO) */ 76 #define P4_0_PORT GPIO_PRT4 77 #define P4_0_PIN 0u 78 #define P4_0_NUM 0u 79 #define P4_3_PORT GPIO_PRT4 80 #define P4_3_PIN 3u 81 #define P4_3_NUM 3u 82 #define P4_4_PORT GPIO_PRT4 83 #define P4_4_PIN 4u 84 #define P4_4_NUM 4u 85 86 /* PORT 5 (GPIO) */ 87 #define P5_0_PORT GPIO_PRT5 88 #define P5_0_PIN 0u 89 #define P5_0_NUM 0u 90 #define P5_1_PORT GPIO_PRT5 91 #define P5_1_PIN 1u 92 #define P5_1_NUM 1u 93 94 /* PORT 6 (GPIO) */ 95 #define P6_0_PORT GPIO_PRT6 96 #define P6_0_PIN 0u 97 #define P6_0_NUM 0u 98 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 99 #define P6_1_PORT GPIO_PRT6 100 #define P6_1_PIN 1u 101 #define P6_1_NUM 1u 102 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 103 #define P6_2_PORT GPIO_PRT6 104 #define P6_2_PIN 2u 105 #define P6_2_NUM 2u 106 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 107 108 /* PORT 7 (GPIO) */ 109 #define P7_0_PORT GPIO_PRT7 110 #define P7_0_PIN 0u 111 #define P7_0_NUM 0u 112 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 113 #define P7_1_PORT GPIO_PRT7 114 #define P7_1_PIN 1u 115 #define P7_1_NUM 1u 116 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 117 #define P7_2_PORT GPIO_PRT7 118 #define P7_2_PIN 2u 119 #define P7_2_NUM 2u 120 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 121 #define P7_3_PORT GPIO_PRT7 122 #define P7_3_PIN 3u 123 #define P7_3_NUM 3u 124 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 125 #define P7_4_PORT GPIO_PRT7 126 #define P7_4_PIN 4u 127 #define P7_4_NUM 4u 128 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 129 #define P7_5_PORT GPIO_PRT7 130 #define P7_5_PIN 5u 131 #define P7_5_NUM 5u 132 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 133 #define P7_6_PORT GPIO_PRT7 134 #define P7_6_PIN 6u 135 #define P7_6_NUM 6u 136 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 137 #define P7_7_PORT GPIO_PRT7 138 #define P7_7_PIN 7u 139 #define P7_7_NUM 7u 140 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 141 142 /* PORT 8 (GPIO) */ 143 #define P8_0_PORT GPIO_PRT8 144 #define P8_0_PIN 0u 145 #define P8_0_NUM 0u 146 #define P8_1_PORT GPIO_PRT8 147 #define P8_1_PIN 1u 148 #define P8_1_NUM 1u 149 #define P8_2_PORT GPIO_PRT8 150 #define P8_2_PIN 2u 151 #define P8_2_NUM 2u 152 #define P8_3_PORT GPIO_PRT8 153 #define P8_3_PIN 3u 154 #define P8_3_NUM 3u 155 #define P8_4_PORT GPIO_PRT8 156 #define P8_4_PIN 4u 157 #define P8_4_NUM 4u 158 #define P8_5_PORT GPIO_PRT8 159 #define P8_5_PIN 5u 160 #define P8_5_NUM 5u 161 162 /* PORT 9 (GPIO) */ 163 #define P9_0_PORT GPIO_PRT9 164 #define P9_0_PIN 0u 165 #define P9_0_NUM 0u 166 #define P9_1_PORT GPIO_PRT9 167 #define P9_1_PIN 1u 168 #define P9_1_NUM 1u 169 #define P9_2_PORT GPIO_PRT9 170 #define P9_2_PIN 2u 171 #define P9_2_NUM 2u 172 #define P9_3_PORT GPIO_PRT9 173 #define P9_3_PIN 3u 174 #define P9_3_NUM 3u 175 #define P9_4_PORT GPIO_PRT9 176 #define P9_4_PIN 4u 177 #define P9_4_NUM 4u 178 #define P9_5_PORT GPIO_PRT9 179 #define P9_5_PIN 5u 180 #define P9_5_NUM 5u 181 #define P9_6_PORT GPIO_PRT9 182 #define P9_6_PIN 6u 183 #define P9_6_NUM 6u 184 #define P9_7_PORT GPIO_PRT9 185 #define P9_7_PIN 7u 186 #define P9_7_NUM 7u 187 188 /* PORT 10 (GPIO_OVT) */ 189 #define P10_0_PORT GPIO_PRT10 190 #define P10_0_PIN 0u 191 #define P10_0_NUM 0u 192 #define P10_1_PORT GPIO_PRT10 193 #define P10_1_PIN 1u 194 #define P10_1_NUM 1u 195 196 /* PORT 11 (GPIO) */ 197 #define P11_0_PORT GPIO_PRT11 198 #define P11_0_PIN 0u 199 #define P11_0_NUM 0u 200 #define P11_1_PORT GPIO_PRT11 201 #define P11_1_PIN 1u 202 #define P11_1_NUM 1u 203 #define P11_2_PORT GPIO_PRT11 204 #define P11_2_PIN 2u 205 #define P11_2_NUM 2u 206 #define P11_3_PORT GPIO_PRT11 207 #define P11_3_PIN 3u 208 #define P11_3_NUM 3u 209 #define P11_4_PORT GPIO_PRT11 210 #define P11_4_PIN 4u 211 #define P11_4_NUM 4u 212 213 /* PORT 12 (AUX) */ 214 #define USBDM_PORT GPIO_PRT12 215 #define USBDM_PIN 0u 216 #define USBDM_NUM 0u 217 #define P12_0_PORT GPIO_PRT12 218 #define P12_0_PIN 0u 219 #define P12_0_NUM 0u 220 #define USBDP_PORT GPIO_PRT12 221 #define USBDP_PIN 1u 222 #define USBDP_NUM 1u 223 #define P12_1_PORT GPIO_PRT12 224 #define P12_1_PIN 1u 225 #define P12_1_NUM 1u 226 227 /* PORT 13 (GPIO) */ 228 #define P13_0_PORT GPIO_PRT13 229 #define P13_0_PIN 0u 230 #define P13_0_NUM 0u 231 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 232 #define P13_1_PORT GPIO_PRT13 233 #define P13_1_PIN 1u 234 #define P13_1_NUM 1u 235 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 236 237 /* Analog Connections */ 238 #define LVDS2USB32SS_ADC_A_IN0_PORT 1u 239 #define LVDS2USB32SS_ADC_A_IN0_PIN 0u 240 #define LVDS2USB32SS_ADC_A_IN1_PORT 1u 241 #define LVDS2USB32SS_ADC_A_IN1_PIN 1u 242 #define SRSS_ADFT_PIN0_PORT 13u 243 #define SRSS_ADFT_PIN0_PIN 0u 244 #define SRSS_ADFT_PIN1_PORT 13u 245 #define SRSS_ADFT_PIN1_PIN 1u 246 #define SRSS_ECO_IN_PORT 5u 247 #define SRSS_ECO_IN_PIN 0u 248 #define SRSS_ECO_OUT_PORT 5u 249 #define SRSS_ECO_OUT_PIN 1u 250 251 /* HSIOM Connections */ 252 typedef enum 253 { 254 /* Generic HSIOM connections */ 255 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 256 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 257 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 258 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 259 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 260 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 261 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 262 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 263 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 264 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 265 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 266 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 267 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 268 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 269 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 270 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 271 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 272 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 273 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 274 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 275 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 276 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 277 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 278 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 279 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 280 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 281 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 282 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 283 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 284 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 285 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 286 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 287 288 /* P1.0 */ 289 P1_0_GPIO = 0, /* GPIO controls 'out' */ 290 P1_0_AMUXA = 4, /* Analog mux bus A */ 291 P1_0_AMUXB = 5, /* Analog mux bus B */ 292 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 293 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 294 P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3] */ 295 P1_0_TDM_TDM_RX_FSYNC = 16, /* Digital Active - tdm.tdm_rx_fsync:1 */ 296 P1_0_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 297 P1_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 298 P1_0_USBHSDEV_GPIO_DDFT0 = 23, /* Digital Active - usbhsdev.gpio_ddft0 */ 299 P1_0_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:2 */ 300 301 /* P1.1 */ 302 P1_1_GPIO = 0, /* GPIO controls 'out' */ 303 P1_1_AMUXA = 4, /* Analog mux bus A */ 304 P1_1_AMUXB = 5, /* Analog mux bus B */ 305 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 306 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 307 P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3] */ 308 P1_1_TDM_TDM_RX_MCK = 16, /* Digital Active - tdm.tdm_rx_mck:1 */ 309 P1_1_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 310 P1_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 311 P1_1_USBHSDEV_GPIO_DDFT1 = 23, /* Digital Active - usbhsdev.gpio_ddft1 */ 312 P1_1_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:2 */ 313 314 /* P4.0 */ 315 P4_0_GPIO = 0, /* GPIO controls 'out' */ 316 P4_0_AMUXA = 4, /* Analog mux bus A */ 317 P4_0_AMUXB = 5, /* Analog mux bus B */ 318 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 319 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 320 P4_0_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 321 P4_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 322 P4_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 323 P4_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 324 325 /* P4.3 */ 326 P4_3_GPIO = 0, /* GPIO controls 'out' */ 327 P4_3_AMUXA = 4, /* Analog mux bus A */ 328 P4_3_AMUXB = 5, /* Analog mux bus B */ 329 P4_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 330 P4_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 331 P4_3_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 332 P4_3_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 333 P4_3_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk */ 334 P4_3_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 335 P4_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:0 */ 336 P4_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 337 P4_3_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 338 339 /* P4.4 */ 340 P4_4_GPIO = 0, /* GPIO controls 'out' */ 341 P4_4_AMUXA = 4, /* Analog mux bus A */ 342 P4_4_AMUXB = 5, /* Analog mux bus B */ 343 P4_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 344 P4_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 345 P4_4_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 346 P4_4_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 347 P4_4_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0 */ 348 P4_4_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 349 P4_4_CANFD0_TTCAN_RX = 22, /* Digital Active - canfd[0].ttcan_rx:1 */ 350 P4_4_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock:0 */ 351 P4_4_LVDS2USB32SS_LNK0_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk0_l3_entry_gpio_i:3 */ 352 P4_4_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 353 354 /* P5.0 */ 355 P5_0_GPIO = 0, /* GPIO controls 'out' */ 356 P5_0_AMUXA = 4, /* Analog mux bus A */ 357 P5_0_AMUXB = 5, /* Analog mux bus B */ 358 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 359 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 360 P5_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 361 362 /* P5.1 */ 363 P5_1_GPIO = 0, /* GPIO controls 'out' */ 364 P5_1_AMUXA = 4, /* Analog mux bus A */ 365 P5_1_AMUXB = 5, /* Analog mux bus B */ 366 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 367 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 368 P5_1_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 369 P5_1_USBHSDEV_TEST_PLL_REFCLK_I = 18, /* Digital Active - usbhsdev.test_pll_refclk_i */ 370 371 /* P6.0 */ 372 P6_0_GPIO = 0, /* GPIO controls 'out' */ 373 P6_0_AMUXA = 4, /* Analog mux bus A */ 374 P6_0_AMUXB = 5, /* Analog mux bus B */ 375 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 376 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 377 P6_0_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 378 P6_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ 379 P6_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ 380 P6_0_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk */ 381 P6_0_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 382 P6_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 383 P6_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:4 */ 384 385 /* P6.1 */ 386 P6_1_GPIO = 0, /* GPIO controls 'out' */ 387 P6_1_AMUXA = 4, /* Analog mux bus A */ 388 P6_1_AMUXB = 5, /* Analog mux bus B */ 389 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 390 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 391 P6_1_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 392 P6_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ 393 P6_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ 394 P6_1_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0 */ 395 P6_1_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 396 P6_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 397 P6_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:4 */ 398 399 /* P6.2 */ 400 P6_2_GPIO = 0, /* GPIO controls 'out' */ 401 P6_2_AMUXA = 4, /* Analog mux bus A */ 402 P6_2_AMUXB = 5, /* Analog mux bus B */ 403 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 404 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 405 P6_2_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 406 P6_2_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi */ 407 P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:1 */ 408 P6_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:4 */ 409 410 /* P7.0 */ 411 P7_0_GPIO = 0, /* GPIO controls 'out' */ 412 P7_0_SCB0_I2C_SCL = 13, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 413 P7_0_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 414 P7_0_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:1 */ 415 P7_0_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk */ 416 417 /* P7.1 */ 418 P7_1_GPIO = 0, /* GPIO controls 'out' */ 419 P7_1_AMUXA = 4, /* Analog mux bus A */ 420 P7_1_AMUXB = 5, /* Analog mux bus B */ 421 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 422 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 423 P7_1_SCB0_I2C_SDA = 13, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 424 P7_1_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 425 P7_1_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:1 */ 426 P7_1_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0 */ 427 P7_1_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 428 P7_1_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 429 430 /* P7.2 */ 431 P7_2_GPIO = 0, /* GPIO controls 'out' */ 432 P7_2_AMUXA = 4, /* Analog mux bus A */ 433 P7_2_AMUXB = 5, /* Analog mux bus B */ 434 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 435 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 436 P7_2_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 437 P7_2_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 438 P7_2_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi */ 439 P7_2_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 440 P7_2_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 441 442 /* P7.3 */ 443 P7_3_GPIO = 0, /* GPIO controls 'out' */ 444 P7_3_AMUXA = 4, /* Analog mux bus A */ 445 P7_3_AMUXB = 5, /* Analog mux bus B */ 446 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 447 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 448 P7_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 449 P7_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 450 P7_3_SCB0_UART_RTS = 19, /* Digital Active - scb[0].uart_rts:0 */ 451 P7_3_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso */ 452 P7_3_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 453 P7_3_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:2 */ 454 455 /* P7.4 */ 456 P7_4_GPIO = 0, /* GPIO controls 'out' */ 457 P7_4_AMUXA = 4, /* Analog mux bus A */ 458 P7_4_AMUXB = 5, /* Analog mux bus B */ 459 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 460 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 461 P7_4_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ 462 P7_4_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 463 P7_4_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 464 P7_4_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:2 */ 465 466 /* P7.5 */ 467 P7_5_GPIO = 0, /* GPIO controls 'out' */ 468 P7_5_AMUXA = 4, /* Analog mux bus A */ 469 P7_5_AMUXB = 5, /* Analog mux bus B */ 470 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 471 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 472 P7_5_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ 473 474 /* P7.6 */ 475 P7_6_GPIO = 0, /* GPIO controls 'out' */ 476 P7_6_AMUXA = 4, /* Analog mux bus A */ 477 P7_6_AMUXB = 5, /* Analog mux bus B */ 478 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 479 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 480 P7_6_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ 481 P7_6_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 482 P7_6_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 483 484 /* P7.7 */ 485 P7_7_GPIO = 0, /* GPIO controls 'out' */ 486 P7_7_AMUXA = 4, /* Analog mux bus A */ 487 P7_7_AMUXB = 5, /* Analog mux bus B */ 488 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 489 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 490 P7_7_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ 491 P7_7_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 492 P7_7_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 493 494 /* P8.0 */ 495 P8_0_GPIO = 0, /* GPIO controls 'out' */ 496 P8_0_AMUXA = 4, /* Analog mux bus A */ 497 P8_0_AMUXB = 5, /* Analog mux bus B */ 498 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 499 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 500 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0] */ 501 P8_0_TDM_TDM_TX_SCK = 16, /* Digital Active - tdm.tdm_tx_sck:1 */ 502 P8_0_PDM0_PDM_CLK0 = 17, /* Digital Active - pdm[0].pdm_clk[0]:1 */ 503 P8_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 504 P8_0_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 505 P8_0_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 506 P8_0_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 507 P8_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:3 */ 508 P8_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 509 510 /* P8.1 */ 511 P8_1_GPIO = 0, /* GPIO controls 'out' */ 512 P8_1_AMUXA = 4, /* Analog mux bus A */ 513 P8_1_AMUXB = 5, /* Analog mux bus B */ 514 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 515 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 516 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0] */ 517 P8_1_TDM_TDM_RX_SCK = 16, /* Digital Active - tdm.tdm_rx_sck:1 */ 518 P8_1_PDM0_PDM_DATA0 = 17, /* Digital Active - pdm[0].pdm_data[0]:1 */ 519 P8_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 520 P8_1_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 521 P8_1_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 522 P8_1_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 523 P8_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:3 */ 524 P8_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 525 526 /* P8.2 */ 527 P8_2_GPIO = 0, /* GPIO controls 'out' */ 528 P8_2_AMUXA = 4, /* Analog mux bus A */ 529 P8_2_AMUXB = 5, /* Analog mux bus B */ 530 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 531 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 532 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1] */ 533 P8_2_TDM_TDM_TX_FSYNC = 16, /* Digital Active - tdm.tdm_tx_fsync:1 */ 534 P8_2_PDM0_PDM_CLK1 = 17, /* Digital Active - pdm[0].pdm_clk[1]:1 */ 535 P8_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 536 P8_2_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 537 P8_2_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 538 P8_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:3 */ 539 P8_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 540 P8_2_LVDS2USB32SS_LNK0_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk0_l3_entry_gpio_i:2 */ 541 542 /* P8.3 */ 543 P8_3_GPIO = 0, /* GPIO controls 'out' */ 544 P8_3_AMUXA = 4, /* Analog mux bus A */ 545 P8_3_AMUXB = 5, /* Analog mux bus B */ 546 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 547 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 548 P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1] */ 549 P8_3_TDM_TDM_TX_MCK = 16, /* Digital Active - tdm.tdm_tx_mck:1 */ 550 P8_3_PDM0_PDM_DATA1 = 17, /* Digital Active - pdm[0].pdm_data[1]:1 */ 551 P8_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 552 P8_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 553 P8_3_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 554 P8_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:3 */ 555 P8_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 556 P8_3_LVDS2USB32SS_LNK1_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk1_l3_entry_gpio_i:2 */ 557 558 /* P8.4 */ 559 P8_4_GPIO = 0, /* GPIO controls 'out' */ 560 P8_4_AMUXA = 4, /* Analog mux bus A */ 561 P8_4_AMUXB = 5, /* Analog mux bus B */ 562 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 563 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 564 P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2] */ 565 P8_4_TDM_TDM_RX_SD = 16, /* Digital Active - tdm.tdm_rx_sd:1 */ 566 P8_4_PDM0_PDM_CLK1 = 17, /* Digital Active - pdm[0].pdm_clk[1]:0 */ 567 P8_4_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 568 P8_4_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 569 P8_4_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 570 P8_4_CANFD0_TTCAN_RX = 22, /* Digital Active - canfd[0].ttcan_rx:0 */ 571 P8_4_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 572 P8_4_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock:1 */ 573 574 /* P8.5 */ 575 P8_5_GPIO = 0, /* GPIO controls 'out' */ 576 P8_5_AMUXA = 4, /* Analog mux bus A */ 577 P8_5_AMUXB = 5, /* Analog mux bus B */ 578 P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 579 P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 580 P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2] */ 581 P8_5_TDM_TDM_TX_SD = 16, /* Digital Active - tdm.tdm_tx_sd:1 */ 582 P8_5_PDM0_PDM_DATA1 = 17, /* Digital Active - pdm[0].pdm_data[1]:0 */ 583 P8_5_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 584 P8_5_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 585 P8_5_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 586 P8_5_CANFD0_TTCAN_TX = 22, /* Digital Active - canfd[0].ttcan_tx:0 */ 587 588 /* P9.0 */ 589 P9_0_GPIO = 0, /* GPIO controls 'out' */ 590 P9_0_AMUXA = 4, /* Analog mux bus A */ 591 P9_0_AMUXB = 5, /* Analog mux bus B */ 592 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 593 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 594 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4] */ 595 P9_0_TDM_TDM_TX_SCK = 16, /* Digital Active - tdm.tdm_tx_sck:0 */ 596 P9_0_PDM0_PDM_CLK0 = 17, /* Digital Active - pdm[0].pdm_clk[0]:2 */ 597 P9_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ 598 P9_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ 599 P9_0_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ 600 P9_0_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 601 P9_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:4 */ 602 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 603 P9_0_LVDS2USB32SS_LNK0_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk0_l3_entry_gpio_i:1 */ 604 605 /* P9.1 */ 606 P9_1_GPIO = 0, /* GPIO controls 'out' */ 607 P9_1_AMUXA = 4, /* Analog mux bus A */ 608 P9_1_AMUXB = 5, /* Analog mux bus B */ 609 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 610 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 611 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4] */ 612 P9_1_TDM_TDM_RX_SCK = 16, /* Digital Active - tdm.tdm_rx_sck:0 */ 613 P9_1_PDM0_PDM_DATA0 = 17, /* Digital Active - pdm[0].pdm_data[0]:2 */ 614 P9_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ 615 P9_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ 616 P9_1_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ 617 P9_1_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 618 P9_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:4 */ 619 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ 620 P9_1_LVDS2USB32SS_LNK1_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk1_l3_entry_gpio_i:1 */ 621 622 /* P9.2 */ 623 P9_2_GPIO = 0, /* GPIO controls 'out' */ 624 P9_2_AMUXA = 4, /* Analog mux bus A */ 625 P9_2_AMUXB = 5, /* Analog mux bus B */ 626 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 627 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 628 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5] */ 629 P9_2_TDM_TDM_TX_FSYNC = 16, /* Digital Active - tdm.tdm_tx_fsync:0 */ 630 P9_2_PDM0_PDM_CLK1 = 17, /* Digital Active - pdm[0].pdm_clk[1]:2 */ 631 P9_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ 632 P9_2_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ 633 P9_2_LVDS2USB32SS_USB32_GPIO_DDFT_O0 = 23, /* Digital Active - lvds2usb32ss.usb32_gpio_ddft_o[0] */ 634 P9_2_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 635 P9_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:4 */ 636 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ 637 638 /* P9.3 */ 639 P9_3_GPIO = 0, /* GPIO controls 'out' */ 640 P9_3_AMUXA = 4, /* Analog mux bus A */ 641 P9_3_AMUXB = 5, /* Analog mux bus B */ 642 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 643 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 644 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5] */ 645 P9_3_TDM_TDM_TX_MCK = 16, /* Digital Active - tdm.tdm_tx_mck:0 */ 646 P9_3_PDM0_PDM_DATA1 = 17, /* Digital Active - pdm[0].pdm_data[1]:2 */ 647 P9_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ 648 P9_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ 649 P9_3_LVDS2USB32SS_USB32_GPIO_DDFT_O1 = 23, /* Digital Active - lvds2usb32ss.usb32_gpio_ddft_o[1] */ 650 P9_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:4 */ 651 P9_3_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock:2 */ 652 653 /* P9.4 */ 654 P9_4_GPIO = 0, /* GPIO controls 'out' */ 655 P9_4_AMUXA = 4, /* Analog mux bus A */ 656 P9_4_AMUXB = 5, /* Analog mux bus B */ 657 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 658 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 659 P9_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6] */ 660 P9_4_TDM_TDM_RX_SD = 16, /* Digital Active - tdm.tdm_rx_sd:0 */ 661 P9_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ 662 P9_4_LVDS2USB32SS_LVDS_GPIO_DDFT_O0 = 23, /* Digital Active - lvds2usb32ss.lvds_gpio_ddft_o[0] */ 663 P9_4_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 664 P9_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 665 666 /* P9.5 */ 667 P9_5_GPIO = 0, /* GPIO controls 'out' */ 668 P9_5_AMUXA = 4, /* Analog mux bus A */ 669 P9_5_AMUXB = 5, /* Analog mux bus B */ 670 P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 671 P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 672 P9_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6] */ 673 P9_5_TDM_TDM_TX_SD = 16, /* Digital Active - tdm.tdm_tx_sd:0 */ 674 P9_5_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 675 P9_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ 676 P9_5_CANFD0_TTCAN_RX = 22, /* Digital Active - canfd[0].ttcan_rx:2 */ 677 P9_5_LVDS2USB32SS_LVDS_GPIO_DDFT_O1 = 23, /* Digital Active - lvds2usb32ss.lvds_gpio_ddft_o[1] */ 678 P9_5_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 679 680 /* P9.6 */ 681 P9_6_GPIO = 0, /* GPIO controls 'out' */ 682 P9_6_AMUXA = 4, /* Analog mux bus A */ 683 P9_6_AMUXB = 5, /* Analog mux bus B */ 684 P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 685 P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 686 P9_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7] */ 687 P9_6_TDM_TDM_RX_FSYNC = 16, /* Digital Active - tdm.tdm_rx_fsync:0 */ 688 P9_6_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 689 P9_6_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 690 P9_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 691 P9_6_CANFD0_TTCAN_TX = 22, /* Digital Active - canfd[0].ttcan_tx:2 */ 692 693 /* P9.7 */ 694 P9_7_GPIO = 0, /* GPIO controls 'out' */ 695 P9_7_AMUXA = 4, /* Analog mux bus A */ 696 P9_7_AMUXB = 5, /* Analog mux bus B */ 697 P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 698 P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 699 P9_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7] */ 700 P9_7_TDM_TDM_RX_MCK = 16, /* Digital Active - tdm.tdm_rx_mck:0 */ 701 P9_7_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 702 P9_7_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 703 704 /* P10.0 */ 705 P10_0_GPIO = 0, /* GPIO controls 'out' */ 706 P10_0_AMUXA = 4, /* Analog mux bus A */ 707 P10_0_AMUXB = 5, /* Analog mux bus B */ 708 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 709 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 710 P10_0_SCB0_I2C_SCL = 13, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 711 P10_0_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 712 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 713 P10_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:5 */ 714 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:3 */ 715 716 /* P10.1 */ 717 P10_1_GPIO = 0, /* GPIO controls 'out' */ 718 P10_1_AMUXA = 4, /* Analog mux bus A */ 719 P10_1_AMUXB = 5, /* Analog mux bus B */ 720 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 721 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 722 P10_1_SCB0_I2C_SDA = 13, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 723 P10_1_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 724 P10_1_LVDS2USB32SS_LVDS_USEC_PULSE_O = 23, /* Digital Active - lvds2usb32ss.lvds_usec_pulse_o:1 */ 725 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 726 P10_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:5 */ 727 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:3 */ 728 729 /* P11.0 */ 730 P11_0_GPIO = 0, /* GPIO controls 'out' */ 731 P11_0_AMUXA = 4, /* Analog mux bus A */ 732 P11_0_AMUXB = 5, /* Analog mux bus B */ 733 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 734 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 735 P11_0_PDM0_PDM_CLK0 = 17, /* Digital Active - pdm[0].pdm_clk[0]:3 */ 736 P11_0_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 737 P11_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 738 P11_0_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 739 P11_0_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 740 P11_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:6 */ 741 P11_0_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:3 */ 742 P11_0_LVDS2USB32SS_LNK0_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk0_l3_entry_gpio_i:0 */ 743 P11_0_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 744 P11_0_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 745 746 /* P11.1 */ 747 P11_1_GPIO = 0, /* GPIO controls 'out' */ 748 P11_1_AMUXA = 4, /* Analog mux bus A */ 749 P11_1_AMUXB = 5, /* Analog mux bus B */ 750 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 751 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 752 P11_1_PDM0_PDM_DATA0 = 17, /* Digital Active - pdm[0].pdm_data[0]:3 */ 753 P11_1_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 754 P11_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 755 P11_1_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 756 P11_1_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 757 P11_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:6 */ 758 P11_1_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:3 */ 759 P11_1_LVDS2USB32SS_LNK1_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk1_l3_entry_gpio_i:0 */ 760 P11_1_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 761 P11_1_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 762 763 /* P11.2 */ 764 P11_2_GPIO = 0, /* GPIO controls 'out' */ 765 P11_2_AMUXA = 4, /* Analog mux bus A */ 766 P11_2_AMUXB = 5, /* Analog mux bus B */ 767 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 768 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 769 P11_2_PDM0_PDM_CLK1 = 17, /* Digital Active - pdm[0].pdm_clk[1]:3 */ 770 P11_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 771 P11_2_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 772 P11_2_LVDS2USB32SS_LVDS_USEC_PULSE_O = 23, /* Digital Active - lvds2usb32ss.lvds_usec_pulse_o:0 */ 773 P11_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:5 */ 774 P11_2_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 775 776 /* P11.3 */ 777 P11_3_GPIO = 0, /* GPIO controls 'out' */ 778 P11_3_AMUXA = 4, /* Analog mux bus A */ 779 P11_3_AMUXB = 5, /* Analog mux bus B */ 780 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 781 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 782 P11_3_PDM0_PDM_DATA1 = 17, /* Digital Active - pdm[0].pdm_data[1]:3 */ 783 P11_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 784 P11_3_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 785 P11_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:5 */ 786 P11_3_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 787 788 /* P11.4 */ 789 P11_4_GPIO = 0, /* GPIO controls 'out' */ 790 P11_4_AMUXA = 4, /* Analog mux bus A */ 791 P11_4_AMUXB = 5, /* Analog mux bus B */ 792 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 793 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 794 P11_4_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 795 P11_4_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 796 P11_4_CANFD0_TTCAN_RX = 22, /* Digital Active - canfd[0].ttcan_rx:3 */ 797 P11_4_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 798 799 /* USBDM */ 800 USBDM_AMUXA = 4, /* Analog mux bus A */ 801 USBDM_AMUXB = 5, /* Analog mux bus B */ 802 USBDM_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 803 USBDM_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 804 805 /* USBDP */ 806 USBDP_AMUXA = 4, /* Analog mux bus A */ 807 USBDP_AMUXB = 5, /* Analog mux bus B */ 808 USBDP_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 809 USBDP_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 810 811 /* P13.0 */ 812 P13_0_GPIO = 0, /* GPIO controls 'out' */ 813 P13_0_AMUXA = 4, /* Analog mux bus A */ 814 P13_0_AMUXB = 5, /* Analog mux bus B */ 815 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 816 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 817 P13_0_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 818 P13_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi */ 819 P13_0_CANFD0_TTCAN_TX = 22, /* Digital Active - canfd[0].ttcan_tx:1 */ 820 821 /* P13.1 */ 822 P13_1_GPIO = 0, /* GPIO controls 'out' */ 823 P13_1_AMUXA = 4, /* Analog mux bus A */ 824 P13_1_AMUXB = 5, /* Analog mux bus B */ 825 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 826 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 827 P13_1_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 828 P13_1_SCB5_SPI_MISO = 20 /* Digital Active - scb[5].spi_miso */ 829 } en_hsiom_sel_t; 830 831 #endif /* _GPIO_FX3G2_104_LGA_H_ */ 832 833 834 /* [] END OF FILE */ 835
