1 /***************************************************************************//** 2 * \file gpio_cyw20829b0_56_qfn.h 3 * 4 * \brief 5 * CYW20829 device GPIO header for 56-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_CYW20829B0_56_QFN_H_ 28 #define _GPIO_CYW20829B0_56_QFN_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_SMT, 40 CY_GPIO_PACKAGE_VQFN, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN 44 #define CY_GPIO_PIN_COUNT 56u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_MAIN, 50 }; 51 52 /* AMUX Splitter Controls */ 53 typedef enum 54 { 55 AMUX_SPLIT_CTL_NONE = 0x0000u /* Device doesn't have AMux bus splitter cells */ 56 } cy_en_amux_split_t; 57 58 /* Port List */ 59 /* PORT 0 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 60 #define P0_0_PORT GPIO_PRT0 61 #define P0_0_PIN 0u 62 #define P0_0_NUM 0u 63 #define P0_1_PORT GPIO_PRT0 64 #define P0_1_PIN 1u 65 #define P0_1_NUM 1u 66 #define P0_2_PORT GPIO_PRT0 67 #define P0_2_PIN 2u 68 #define P0_2_NUM 2u 69 #define P0_3_PORT GPIO_PRT0 70 #define P0_3_PIN 3u 71 #define P0_3_NUM 3u 72 #define P0_4_PORT GPIO_PRT0 73 #define P0_4_PIN 4u 74 #define P0_4_NUM 4u 75 #define P0_5_PORT GPIO_PRT0 76 #define P0_5_PIN 5u 77 #define P0_5_NUM 5u 78 79 /* PORT 1 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 80 #define P1_0_PORT GPIO_PRT1 81 #define P1_0_PIN 0u 82 #define P1_0_NUM 0u 83 #define P1_1_PORT GPIO_PRT1 84 #define P1_1_PIN 1u 85 #define P1_1_NUM 1u 86 #define P1_2_PORT GPIO_PRT1 87 #define P1_2_PIN 2u 88 #define P1_2_NUM 2u 89 #define P1_3_PORT GPIO_PRT1 90 #define P1_3_PIN 3u 91 #define P1_3_NUM 3u 92 #define P1_4_PORT GPIO_PRT1 93 #define P1_4_PIN 4u 94 #define P1_4_NUM 4u 95 #define P1_5_PORT GPIO_PRT1 96 #define P1_5_PIN 5u 97 #define P1_5_NUM 5u 98 #define P1_6_PORT GPIO_PRT1 99 #define P1_6_PIN 6u 100 #define P1_6_NUM 6u 101 102 /* PORT 2 (HSIO, SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 103 #define P2_0_PORT GPIO_PRT2 104 #define P2_0_PIN 0u 105 #define P2_0_NUM 0u 106 #define P2_1_PORT GPIO_PRT2 107 #define P2_1_PIN 1u 108 #define P2_1_NUM 1u 109 #define P2_2_PORT GPIO_PRT2 110 #define P2_2_PIN 2u 111 #define P2_2_NUM 2u 112 #define P2_3_PORT GPIO_PRT2 113 #define P2_3_PIN 3u 114 #define P2_3_NUM 3u 115 #define P2_4_PORT GPIO_PRT2 116 #define P2_4_PIN 4u 117 #define P2_4_NUM 4u 118 #define P2_5_PORT GPIO_PRT2 119 #define P2_5_PIN 5u 120 #define P2_5_NUM 5u 121 122 /* PORT 3 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 123 #define P3_0_PORT GPIO_PRT3 124 #define P3_0_PIN 0u 125 #define P3_0_NUM 0u 126 #define P3_1_PORT GPIO_PRT3 127 #define P3_1_PIN 1u 128 #define P3_1_NUM 1u 129 #define P3_2_PORT GPIO_PRT3 130 #define P3_2_PIN 2u 131 #define P3_2_NUM 2u 132 #define P3_3_PORT GPIO_PRT3 133 #define P3_3_PIN 3u 134 #define P3_3_NUM 3u 135 #define P3_4_PORT GPIO_PRT3 136 #define P3_4_PIN 4u 137 #define P3_4_NUM 4u 138 #define P3_5_PORT GPIO_PRT3 139 #define P3_5_PIN 5u 140 #define P3_5_NUM 5u 141 #define P3_6_PORT GPIO_PRT3 142 #define P3_6_PIN 6u 143 #define P3_6_NUM 6u 144 #define P3_7_PORT GPIO_PRT3 145 #define P3_7_PIN 7u 146 #define P3_7_NUM 7u 147 148 /* PORT 4 (GPIO_OVT, SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 149 #define P4_0_PORT GPIO_PRT4 150 #define P4_0_PIN 0u 151 #define P4_0_NUM 0u 152 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 153 #define P4_1_PORT GPIO_PRT4 154 #define P4_1_PIN 1u 155 #define P4_1_NUM 1u 156 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 157 158 /* PORT 5 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 159 #define P5_0_PORT GPIO_PRT5 160 #define P5_0_PIN 0u 161 #define P5_0_NUM 0u 162 #define P5_1_PORT GPIO_PRT5 163 #define P5_1_PIN 1u 164 #define P5_1_NUM 1u 165 #define P5_2_PORT GPIO_PRT5 166 #define P5_2_PIN 2u 167 #define P5_2_NUM 2u 168 169 /* Analog Connections */ 170 #define ADCMIC_GPIO_ADC_IN0_PORT 3u 171 #define ADCMIC_GPIO_ADC_IN0_PIN 0u 172 #define ADCMIC_GPIO_ADC_IN1_PORT 3u 173 #define ADCMIC_GPIO_ADC_IN1_PIN 1u 174 #define ADCMIC_GPIO_ADC_IN2_PORT 3u 175 #define ADCMIC_GPIO_ADC_IN2_PIN 2u 176 #define ADCMIC_GPIO_ADC_IN3_PORT 3u 177 #define ADCMIC_GPIO_ADC_IN3_PIN 3u 178 #define ADCMIC_GPIO_ADC_IN4_PORT 3u 179 #define ADCMIC_GPIO_ADC_IN4_PIN 4u 180 #define ADCMIC_GPIO_ADC_IN5_PORT 3u 181 #define ADCMIC_GPIO_ADC_IN5_PIN 5u 182 #define ADCMIC_GPIO_ADC_IN6_PORT 3u 183 #define ADCMIC_GPIO_ADC_IN6_PIN 6u 184 #define ADCMIC_GPIO_ADC_IN7_PORT 3u 185 #define ADCMIC_GPIO_ADC_IN7_PIN 7u 186 #define SRSS_WCO_IN_PORT 5u 187 #define SRSS_WCO_IN_PIN 0u 188 #define SRSS_WCO_OUT_PORT 5u 189 #define SRSS_WCO_OUT_PIN 1u 190 191 /* HSIOM Connections */ 192 typedef enum 193 { 194 /* Generic HSIOM connections */ 195 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 196 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 197 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 198 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 199 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 200 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 201 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 202 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 203 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 204 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 205 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 206 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 207 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 208 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 209 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 210 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 211 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 212 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 213 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 214 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 215 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 216 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 217 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 218 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 219 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 220 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 221 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 222 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 223 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 224 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 225 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 226 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 227 228 /* P0.0 */ 229 P0_0_GPIO = 0, /* GPIO controls 'out' */ 230 P0_0_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 231 P0_0_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 232 P0_0_KEYSCAN_KS_COL3 = 14, /* Digital Deep Sleep - keyscan.ks_col[3] */ 233 P0_0_PDM_PDM_CLK1 = 21, /* Digital Active - pdm.pdm_clk[1]:0 */ 234 P0_0_TDM_TDM_RX_MCK0 = 24, /* Digital Active - tdm.tdm_rx_mck[0]:0 */ 235 P0_0_BTSS_DEBUG12 = 26, /* Digital Active - btss.debug[12] */ 236 P0_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 237 238 /* P0.1 */ 239 P0_1_GPIO = 0, /* GPIO controls 'out' */ 240 P0_1_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 241 P0_1_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ 242 P0_1_KEYSCAN_KS_COL4 = 14, /* Digital Deep Sleep - keyscan.ks_col[4] */ 243 P0_1_PDM_PDM_DATA1 = 21, /* Digital Active - pdm.pdm_data[1]:0 */ 244 P0_1_TDM_TDM_RX_SCK0 = 24, /* Digital Active - tdm.tdm_rx_sck[0]:0 */ 245 P0_1_BTSS_DEBUG13 = 26, /* Digital Active - btss.debug[13] */ 246 P0_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 247 248 /* P0.2 */ 249 P0_2_GPIO = 0, /* GPIO controls 'out' */ 250 P0_2_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 251 P0_2_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ 252 P0_2_KEYSCAN_KS_COL11 = 14, /* Digital Deep Sleep - keyscan.ks_col[11] */ 253 P0_2_SCB0_I2C_SCL = 15, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 254 P0_2_PERI_TR_IO_INPUT4 = 22, /* Digital Active - peri.tr_io_input[4]:0 */ 255 P0_2_TDM_TDM_RX_FSYNC0 = 24, /* Digital Active - tdm.tdm_rx_fsync[0]:0 */ 256 P0_2_BTSS_DEBUG14 = 26, /* Digital Active - btss.debug[14] */ 257 P0_2_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 258 259 /* P0.3 */ 260 P0_3_GPIO = 0, /* GPIO controls 'out' */ 261 P0_3_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 262 P0_3_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ 263 P0_3_KEYSCAN_KS_COL12 = 14, /* Digital Deep Sleep - keyscan.ks_col[12] */ 264 P0_3_SCB0_I2C_SDA = 15, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 265 P0_3_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 266 P0_3_PERI_TR_IO_INPUT5 = 22, /* Digital Active - peri.tr_io_input[5]:0 */ 267 P0_3_TDM_TDM_RX_SD0 = 24, /* Digital Active - tdm.tdm_rx_sd[0]:0 */ 268 P0_3_BTSS_DEBUG15 = 26, /* Digital Active - btss.debug[15] */ 269 P0_3_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 270 271 /* P0.4 */ 272 P0_4_GPIO = 0, /* GPIO controls 'out' */ 273 P0_4_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 274 P0_4_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ 275 P0_4_BTSS_GPIO5 = 10, /* Digital Active - btss.gpio[5]:0 */ 276 P0_4_BTSS_TXD_PYLD_MOD_TEST1 = 11, /* Digital Active - btss.txd_pyld_mod_test[1] */ 277 P0_4_KEYSCAN_KS_ROW0 = 14, /* Digital Deep Sleep - keyscan.ks_row[0] */ 278 P0_4_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 279 P0_4_CPUSS_TRACE_DATA3 = 17, /* Digital Active - cpuss.trace_data[3]:1 */ 280 P0_4_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 281 P0_4_PERI_TR_IO_INPUT0 = 22, /* Digital Active - peri.tr_io_input[0]:0 */ 282 P0_4_TDM_TDM_TX_MCK0 = 24, /* Digital Active - tdm.tdm_tx_mck[0]:0 */ 283 P0_4_BTSS_DEBUG3 = 26, /* Digital Active - btss.debug[3]:0 */ 284 P0_4_BTSS_SPI_CLK = 27, /* Digital Active - btss.spi_clk:0 */ 285 P0_4_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 286 P0_4_IOSS_DDFT_PIN1 = 31, /* Digital Deep Sleep - ioss.ddft_pin[1]:0 */ 287 288 /* P0.5 */ 289 P0_5_GPIO = 0, /* GPIO controls 'out' */ 290 P0_5_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 291 P0_5_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ 292 P0_5_BTSS_ANTENNA_SWITCH_CTRL0 = 10, /* Digital Active - btss.antenna_switch_ctrl[0] */ 293 P0_5_BTSS_TX_ST_TEST = 11, /* Digital Active - btss.tx_st_test */ 294 P0_5_KEYSCAN_KS_ROW1 = 14, /* Digital Deep Sleep - keyscan.ks_row[1] */ 295 P0_5_CPUSS_TRACE_DATA2 = 17, /* Digital Active - cpuss.trace_data[2]:1 */ 296 P0_5_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 297 P0_5_PERI_TR_IO_INPUT1 = 22, /* Digital Active - peri.tr_io_input[1]:0 */ 298 P0_5_TDM_TDM_TX_SCK0 = 24, /* Digital Active - tdm.tdm_tx_sck[0]:0 */ 299 P0_5_BTSS_GCI_GPIO0 = 25, /* Digital Active - btss.gci_gpio[0] */ 300 P0_5_BTSS_DEBUG4 = 26, /* Digital Active - btss.debug[4] */ 301 P0_5_SMIF_SPIHB_SELECT1 = 27, /* Digital Active - smif.spihb_select1 */ 302 303 /* P1.0 */ 304 P1_0_GPIO = 0, /* GPIO controls 'out' */ 305 P1_0_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 306 P1_0_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ 307 P1_0_BTSS_ANTENNA_SWITCH_CTRL1 = 10, /* Digital Active - btss.antenna_switch_ctrl[1] */ 308 P1_0_BTSS_RPU_TDO = 11, /* Digital Active - btss.rpu_tdo */ 309 P1_0_KEYSCAN_KS_ROW5 = 14, /* Digital Deep Sleep - keyscan.ks_row[5] */ 310 P1_0_CPUSS_TRACE_DATA1 = 17, /* Digital Active - cpuss.trace_data[1]:1 */ 311 P1_0_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 312 P1_0_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 313 P1_0_PDM_PDM_CLK1 = 21, /* Digital Active - pdm.pdm_clk[1]:1 */ 314 P1_0_PERI_TR_IO_OUTPUT0 = 23, /* Digital Active - peri.tr_io_output[0]:0 */ 315 P1_0_TDM_TDM_TX_FSYNC0 = 24, /* Digital Active - tdm.tdm_tx_fsync[0]:0 */ 316 P1_0_BTSS_GCI_GPIO1 = 25, /* Digital Active - btss.gci_gpio[1] */ 317 P1_0_BTSS_DEBUG5 = 26, /* Digital Active - btss.debug[5] */ 318 P1_0_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 319 320 /* P1.1 */ 321 P1_1_GPIO = 0, /* GPIO controls 'out' */ 322 P1_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 323 P1_1_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ 324 P1_1_BTSS_ANTENNA_SWITCH_CTRL2 = 10, /* Digital Active - btss.antenna_switch_ctrl[2] */ 325 P1_1_BTSS_RPU_TDI = 11, /* Digital Active - btss.rpu_tdi */ 326 P1_1_KEYSCAN_KS_ROW6 = 14, /* Digital Deep Sleep - keyscan.ks_row[6] */ 327 P1_1_CPUSS_TRACE_DATA0 = 17, /* Digital Active - cpuss.trace_data[0]:1 */ 328 P1_1_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 329 P1_1_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 330 P1_1_PDM_PDM_DATA1 = 21, /* Digital Active - pdm.pdm_data[1]:1 */ 331 P1_1_PERI_TR_IO_OUTPUT1 = 23, /* Digital Active - peri.tr_io_output[1]:0 */ 332 P1_1_TDM_TDM_TX_SD0 = 24, /* Digital Active - tdm.tdm_tx_sd[0]:0 */ 333 P1_1_BTSS_GCI_GPIO2 = 25, /* Digital Active - btss.gci_gpio[2]:0 */ 334 P1_1_BTSS_DEBUG6 = 26, /* Digital Active - btss.debug[6] */ 335 P1_1_BTSS_UART_TXD = 27, /* Digital Active - btss.uart_txd:2 */ 336 P1_1_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 337 P1_1_IOSS_DDFT_PIN0 = 31, /* Digital Deep Sleep - ioss.ddft_pin[0]:0 */ 338 339 /* P1.2 */ 340 P1_2_GPIO = 0, /* GPIO controls 'out' */ 341 P1_2_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 342 P1_2_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ 343 P1_2_BTSS_GPIO0 = 10, /* Digital Active - btss.gpio[0]:0 */ 344 P1_2_BTSS_RPU_SWD = 11, /* Digital Active - btss.rpu_swd */ 345 P1_2_KEYSCAN_KS_COL17 = 15, /* Digital Deep Sleep - keyscan.ks_col[17]:0 */ 346 P1_2_CPUSS_TRACE_CLOCK = 17, /* Digital Active - cpuss.trace_clock:1 */ 347 P1_2_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 348 P1_2_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 349 P1_2_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 350 P1_2_PERI_TR_IO_INPUT2 = 22, /* Digital Active - peri.tr_io_input[2]:0 */ 351 P1_2_BTSS_GCI_GPIO3 = 25, /* Digital Active - btss.gci_gpio[3] */ 352 P1_2_BTSS_DEBUG7 = 26, /* Digital Active - btss.debug[7]:0 */ 353 P1_2_BTSS_SPI_MOSI = 27, /* Digital Active - btss.spi_mosi:1 */ 354 P1_2_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 355 356 /* P1.3 */ 357 P1_3_GPIO = 0, /* GPIO controls 'out' */ 358 P1_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 359 P1_3_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ 360 P1_3_BTSS_GPIO1 = 10, /* Digital Active - btss.gpio[1]:0 */ 361 P1_3_BTSS_RPU_TCK = 11, /* Digital Active - btss.rpu_tck */ 362 P1_3_KEYSCAN_KS_COL16 = 15, /* Digital Deep Sleep - keyscan.ks_col[16]:0 */ 363 P1_3_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 364 P1_3_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 365 P1_3_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 366 P1_3_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 367 P1_3_PERI_TR_IO_INPUT3 = 22, /* Digital Active - peri.tr_io_input[3]:0 */ 368 P1_3_BTSS_GCI_GPIO4 = 25, /* Digital Active - btss.gci_gpio[4] */ 369 P1_3_BTSS_DEBUG8 = 26, /* Digital Active - btss.debug[8]:0 */ 370 P1_3_BTSS_SPI_CLK = 27, /* Digital Active - btss.spi_clk:1 */ 371 P1_3_CPUSS_CLK_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.clk_swj_swclk_tclk */ 372 373 /* P1.4 */ 374 P1_4_GPIO = 0, /* GPIO controls 'out' */ 375 P1_4_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 376 P1_4_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ 377 P1_4_BTSS_GPIO5 = 10, /* Digital Active - btss.gpio[5]:1 */ 378 P1_4_KEYSCAN_KS_COL15 = 14, /* Digital Deep Sleep - keyscan.ks_col[15] */ 379 P1_4_KEYSCAN_KS_COL16 = 15, /* Digital Deep Sleep - keyscan.ks_col[16]:1 */ 380 P1_4_LIN0_LIN_EN1 = 23, /* Digital Active - lin[0].lin_en[1]:0 */ 381 P1_4_BTSS_GCI_GPIO2 = 25, /* Digital Active - btss.gci_gpio[2]:1 */ 382 P1_4_BTSS_DEBUG9 = 26, /* Digital Active - btss.debug[9] */ 383 384 /* P1.5 */ 385 P1_5_GPIO = 0, /* GPIO controls 'out' */ 386 P1_5_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 387 P1_5_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ 388 P1_5_BTSS_GPIO6 = 10, /* Digital Active - btss.gpio[6] */ 389 P1_5_KEYSCAN_KS_COL5 = 14, /* Digital Deep Sleep - keyscan.ks_col[5] */ 390 P1_5_LIN0_LIN_RX1 = 23, /* Digital Active - lin[0].lin_rx[1]:0 */ 391 P1_5_BTSS_DEBUG10 = 26, /* Digital Active - btss.debug[10] */ 392 393 /* P1.6 */ 394 P1_6_GPIO = 0, /* GPIO controls 'out' */ 395 P1_6_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 396 P1_6_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 397 P1_6_BTSS_GPIO7 = 10, /* Digital Active - btss.gpio[7] */ 398 P1_6_KEYSCAN_KS_COL6 = 14, /* Digital Deep Sleep - keyscan.ks_col[6] */ 399 P1_6_SRSS_CAL_WAVE = 15, /* Digital Deep Sleep - srss.cal_wave */ 400 P1_6_LIN0_LIN_TX1 = 23, /* Digital Active - lin[0].lin_tx[1]:0 */ 401 P1_6_BTSS_DEBUG11 = 26, /* Digital Active - btss.debug[11] */ 402 403 /* P2.0 */ 404 P2_0_GPIO = 0, /* GPIO controls 'out' */ 405 P2_0_SMIF_SPIHB_SELECT0 = 27, /* Digital Active - smif.spihb_select0 */ 406 407 /* P2.1 */ 408 P2_1_GPIO = 0, /* GPIO controls 'out' */ 409 P2_1_SMIF_SPIHB_DATA3 = 27, /* Digital Active - smif.spihb_data3 */ 410 411 /* P2.2 */ 412 P2_2_GPIO = 0, /* GPIO controls 'out' */ 413 P2_2_SMIF_SPIHB_DATA2 = 27, /* Digital Active - smif.spihb_data2 */ 414 415 /* P2.3 */ 416 P2_3_GPIO = 0, /* GPIO controls 'out' */ 417 P2_3_SMIF_SPIHB_DATA1 = 27, /* Digital Active - smif.spihb_data1 */ 418 419 /* P2.4 */ 420 P2_4_GPIO = 0, /* GPIO controls 'out' */ 421 P2_4_SMIF_SPIHB_DATA0 = 27, /* Digital Active - smif.spihb_data0 */ 422 423 /* P2.5 */ 424 P2_5_GPIO = 0, /* GPIO controls 'out' */ 425 P2_5_SMIF_SPIHB_CLK = 27, /* Digital Active - smif.spihb_clk */ 426 427 /* P3.0 */ 428 P3_0_GPIO = 0, /* GPIO controls 'out' */ 429 P3_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 430 P3_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ 431 P3_0_KEYSCAN_KS_ROW7 = 14, /* Digital Deep Sleep - keyscan.ks_row[7] */ 432 P3_0_CPUSS_TRACE_DATA3 = 17, /* Digital Active - cpuss.trace_data[3]:0 */ 433 P3_0_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 434 P3_0_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 435 P3_0_BTSS_UART_CTS = 26, /* Digital Active - btss.uart_cts:0 */ 436 437 /* P3.1 */ 438 P3_1_GPIO = 0, /* GPIO controls 'out' */ 439 P3_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 440 P3_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 441 P3_1_BTSS_RPU_NTRST = 11, /* Digital Active - btss.rpu_ntrst */ 442 P3_1_KEYSCAN_KS_ROW4 = 14, /* Digital Deep Sleep - keyscan.ks_row[4] */ 443 P3_1_CPUSS_TRACE_DATA2 = 17, /* Digital Active - cpuss.trace_data[2]:0 */ 444 P3_1_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 445 P3_1_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 446 P3_1_LIN0_LIN_EN0 = 23, /* Digital Active - lin[0].lin_en[0]:0 */ 447 P3_1_BTSS_UART_RTS = 26, /* Digital Active - btss.uart_rts:0 */ 448 P3_1_BTSS_SYSCLK_RF = 27, /* Digital Active - btss.sysclk_rf */ 449 P3_1_CPUSS_RST_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.rst_swj_trstn */ 450 451 /* P3.2 */ 452 P3_2_GPIO = 0, /* GPIO controls 'out' */ 453 P3_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 454 P3_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ 455 P3_2_BTSS_TXD_SYMB_DATA_TEST0 = 11, /* Digital Active - btss.txd_symb_data_test[0] */ 456 P3_2_KEYSCAN_KS_COL13 = 14, /* Digital Deep Sleep - keyscan.ks_col[13] */ 457 P3_2_CPUSS_TRACE_DATA1 = 17, /* Digital Active - cpuss.trace_data[1]:0 */ 458 P3_2_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 459 P3_2_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 460 P3_2_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 461 P3_2_PDM_PDM_CLK0 = 21, /* Digital Active - pdm.pdm_clk[0]:0 */ 462 P3_2_PERI_TR_IO_INPUT6 = 22, /* Digital Active - peri.tr_io_input[6]:0 */ 463 P3_2_LIN0_LIN_RX0 = 23, /* Digital Active - lin[0].lin_rx[0]:0 */ 464 P3_2_CANFD0_TTCAN_RX0 = 24, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 465 P3_2_ADCMIC_CLK_PDM = 25, /* Digital Active - adcmic.clk_pdm:0 */ 466 P3_2_BTSS_UART_RXD = 27, /* Digital Active - btss.uart_rxd:0 */ 467 P3_2_IOSS_DDFT_PIN1 = 31, /* Digital Deep Sleep - ioss.ddft_pin[1]:1 */ 468 469 /* P3.3 */ 470 P3_3_GPIO = 0, /* GPIO controls 'out' */ 471 P3_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 472 P3_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 473 P3_3_BTSS_TXD_SYMB_DATA_TEST1 = 11, /* Digital Active - btss.txd_symb_data_test[1] */ 474 P3_3_KEYSCAN_KS_COL14 = 14, /* Digital Deep Sleep - keyscan.ks_col[14] */ 475 P3_3_KEYSCAN_KS_COL17 = 15, /* Digital Deep Sleep - keyscan.ks_col[17]:1 */ 476 P3_3_CPUSS_TRACE_DATA0 = 17, /* Digital Active - cpuss.trace_data[0]:0 */ 477 P3_3_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 478 P3_3_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 479 P3_3_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 480 P3_3_PDM_PDM_DATA0 = 21, /* Digital Active - pdm.pdm_data[0]:0 */ 481 P3_3_PERI_TR_IO_INPUT7 = 22, /* Digital Active - peri.tr_io_input[7]:0 */ 482 P3_3_LIN0_LIN_TX0 = 23, /* Digital Active - lin[0].lin_tx[0]:0 */ 483 P3_3_CANFD0_TTCAN_TX0 = 24, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 484 P3_3_ADCMIC_PDM_DATA = 25, /* Digital Active - adcmic.pdm_data:0 */ 485 P3_3_BTSS_UART_TXD = 27, /* Digital Active - btss.uart_txd:0 */ 486 P3_3_IOSS_DDFT_PIN0 = 31, /* Digital Deep Sleep - ioss.ddft_pin[0]:1 */ 487 488 /* P3.4 */ 489 P3_4_GPIO = 0, /* GPIO controls 'out' */ 490 P3_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 491 P3_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ 492 P3_4_BTSS_GPIO0 = 10, /* Digital Active - btss.gpio[0]:1 */ 493 P3_4_KEYSCAN_KS_COL7 = 14, /* Digital Deep Sleep - keyscan.ks_col[7] */ 494 P3_4_CPUSS_TRACE_CLOCK = 17, /* Digital Active - cpuss.trace_clock:0 */ 495 P3_4_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 496 P3_4_BTSS_DEBUG3 = 26, /* Digital Active - btss.debug[3]:1 */ 497 498 /* P3.5 */ 499 P3_5_GPIO = 0, /* GPIO controls 'out' */ 500 P3_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 501 P3_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 502 P3_5_BTSS_GPIO1 = 10, /* Digital Active - btss.gpio[1]:1 */ 503 P3_5_KEYSCAN_KS_COL8 = 14, /* Digital Deep Sleep - keyscan.ks_col[8] */ 504 P3_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 505 P3_5_BTSS_DEBUG1 = 26, /* Digital Active - btss.debug[1]:1 */ 506 507 /* P3.6 */ 508 P3_6_GPIO = 0, /* GPIO controls 'out' */ 509 P3_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 510 P3_6_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ 511 P3_6_KEYSCAN_KS_COL9 = 14, /* Digital Deep Sleep - keyscan.ks_col[9] */ 512 P3_6_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 513 P3_6_BTSS_DEBUG2 = 26, /* Digital Active - btss.debug[2]:1 */ 514 515 /* P3.7 */ 516 P3_7_GPIO = 0, /* GPIO controls 'out' */ 517 P3_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 518 P3_7_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ 519 P3_7_BTSS_ANTENNA_SWITCH_CTRL3 = 10, /* Digital Active - btss.antenna_switch_ctrl[3] */ 520 P3_7_KEYSCAN_KS_COL10 = 14, /* Digital Deep Sleep - keyscan.ks_col[10] */ 521 P3_7_BTSS_DEBUG7 = 26, /* Digital Active - btss.debug[7]:1 */ 522 523 /* P4.0 */ 524 P4_0_GPIO = 0, /* GPIO controls 'out' */ 525 P4_0_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 526 P4_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 527 P4_0_BTSS_GPIO2 = 10, /* Digital Active - btss.gpio[2] */ 528 P4_0_BTSS_TXD_SYMB_STRB_TEST = 11, /* Digital Active - btss.txd_symb_strb_test */ 529 P4_0_KEYSCAN_KS_ROW2 = 14, /* Digital Deep Sleep - keyscan.ks_row[2] */ 530 P4_0_SCB0_I2C_SCL = 15, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 531 P4_0_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:2 */ 532 P4_0_BTSS_DEBUG1 = 26, /* Digital Active - btss.debug[1]:0 */ 533 P4_0_BTSS_UART_TXD = 27, /* Digital Active - btss.uart_txd:1 */ 534 P4_0_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 535 536 /* P4.1 */ 537 P4_1_GPIO = 0, /* GPIO controls 'out' */ 538 P4_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 539 P4_1_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ 540 P4_1_BTSS_GPIO4 = 10, /* Digital Active - btss.gpio[4]:1 */ 541 P4_1_BTSS_TXD_PYLD_MOD_TEST0 = 11, /* Digital Active - btss.txd_pyld_mod_test[0] */ 542 P4_1_KEYSCAN_KS_ROW3 = 14, /* Digital Deep Sleep - keyscan.ks_row[3] */ 543 P4_1_SCB0_I2C_SDA = 15, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 544 P4_1_BTSS_DEBUG2 = 26, /* Digital Active - btss.debug[2]:0 */ 545 P4_1_BTSS_SPI_MOSI = 27, /* Digital Active - btss.spi_mosi:0 */ 546 P4_1_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 547 548 /* P5.0 */ 549 P5_0_GPIO = 0, /* GPIO controls 'out' */ 550 P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 551 P5_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ 552 P5_0_BTSS_TXD_SYMB_DATA_TEST2 = 11, /* Digital Active - btss.txd_symb_data_test[2] */ 553 P5_0_KEYSCAN_KS_COL0 = 14, /* Digital Deep Sleep - keyscan.ks_col[0] */ 554 P5_0_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:1 */ 555 P5_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:2 */ 556 P5_0_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:2 */ 557 P5_0_PDM_PDM_CLK0 = 21, /* Digital Active - pdm.pdm_clk[0]:1 */ 558 P5_0_CANFD0_TTCAN_RX0 = 24, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 559 P5_0_ADCMIC_CLK_PDM = 25, /* Digital Active - adcmic.clk_pdm:1 */ 560 P5_0_BTSS_UART_CTS = 26, /* Digital Active - btss.uart_cts:1 */ 561 562 /* P5.1 */ 563 P5_1_GPIO = 0, /* GPIO controls 'out' */ 564 P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 565 P5_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 566 P5_1_BTSS_GPIO3 = 10, /* Digital Active - btss.gpio[3] */ 567 P5_1_BTSS_TXD_SYMB_DATA_TEST3 = 11, /* Digital Active - btss.txd_symb_data_test[3] */ 568 P5_1_KEYSCAN_KS_COL1 = 14, /* Digital Deep Sleep - keyscan.ks_col[1] */ 569 P5_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:2 */ 570 P5_1_PDM_PDM_DATA0 = 21, /* Digital Active - pdm.pdm_data[0]:1 */ 571 P5_1_CANFD0_TTCAN_TX0 = 24, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 572 P5_1_ADCMIC_PDM_DATA = 25, /* Digital Active - adcmic.pdm_data:1 */ 573 P5_1_BTSS_DEBUG0 = 26, /* Digital Active - btss.debug[0] */ 574 P5_1_BTSS_UART_RXD = 27, /* Digital Active - btss.uart_rxd:1 */ 575 P5_1_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 576 577 /* P5.2 */ 578 P5_2_GPIO = 0, /* GPIO controls 'out' */ 579 P5_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 580 P5_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ 581 P5_2_BTSS_GPIO4 = 10, /* Digital Active - btss.gpio[4]:0 */ 582 P5_2_KEYSCAN_KS_COL2 = 14, /* Digital Deep Sleep - keyscan.ks_col[2] */ 583 P5_2_BTSS_DEBUG8 = 26 /* Digital Active - btss.debug[8]:1 */ 584 } en_hsiom_sel_t; 585 586 #endif /* _GPIO_CYW20829B0_56_QFN_H_ */ 587 588 589 /* [] END OF FILE */ 590
