1 /*
2 * Copyright (c) 2021 Synopsys
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT snps_creg_gpio
8
9 #include <errno.h>
10
11 #include <zephyr/kernel.h>
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 #include <zephyr/drivers/gpio.h>
15 #include <zephyr/drivers/i2c.h>
16 #include <zephyr/sys/byteorder.h>
17 #include <zephyr/sys/util.h>
18
19 #include <zephyr/logging/log.h>
20 LOG_MODULE_REGISTER(creg_gpio, CONFIG_GPIO_LOG_LEVEL);
21
22 #include <zephyr/drivers/gpio/gpio_utils.h>
23
24 /** Runtime driver data */
25 struct creg_gpio_drv_data {
26 /* gpio_driver_data needs to be first */
27 struct gpio_driver_data common;
28 uint32_t pin_val;
29 uint32_t base_addr;
30 };
31
32 /** Configuration data */
33 struct creg_gpio_config {
34 /* gpio_driver_config needs to be first */
35 struct gpio_driver_config common;
36 uint32_t ngpios;
37 uint8_t bit_per_gpio;
38 uint8_t off_val;
39 uint8_t on_val;
40 };
41
port_get(const struct device * dev,gpio_port_value_t * value)42 static int port_get(const struct device *dev,
43 gpio_port_value_t *value)
44 {
45 const struct creg_gpio_config *cfg = dev->config;
46 struct creg_gpio_drv_data *drv_data = dev->data;
47 uint32_t in = sys_read32(drv_data->base_addr);
48 uint32_t tmp = 0;
49 uint32_t val = 0;
50
51 for (uint8_t i = 0; i < cfg->ngpios; i++) {
52 tmp = (in & cfg->on_val << i * cfg->bit_per_gpio) ? 1 : 0;
53 val |= tmp << i;
54 }
55 *value = drv_data->pin_val = val;
56
57 return 0;
58 }
59
port_write(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value,gpio_port_value_t toggle)60 static int port_write(const struct device *dev,
61 gpio_port_pins_t mask,
62 gpio_port_value_t value,
63 gpio_port_value_t toggle)
64 {
65 const struct creg_gpio_config *cfg = dev->config;
66 struct creg_gpio_drv_data *drv_data = dev->data;
67 uint32_t *pin_val = &drv_data->pin_val;
68 uint32_t out = 0;
69 uint32_t tmp = 0;
70
71 *pin_val = ((*pin_val & ~mask) | (value & mask)) ^ toggle;
72
73 for (uint8_t i = 0; i < cfg->ngpios; i++) {
74 tmp = (*pin_val & 1 << i) ? cfg->on_val : cfg->off_val;
75 out |= tmp << i * cfg->bit_per_gpio;
76 }
77 sys_write32(out, drv_data->base_addr);
78
79 return 0;
80 }
81
port_set_masked(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)82 static int port_set_masked(const struct device *dev,
83 gpio_port_pins_t mask,
84 gpio_port_value_t value)
85 {
86 return port_write(dev, mask, value, 0);
87 }
88
port_set_bits(const struct device * dev,gpio_port_pins_t pins)89 static int port_set_bits(const struct device *dev,
90 gpio_port_pins_t pins)
91 {
92 return port_write(dev, pins, pins, 0);
93 }
94
port_clear_bits(const struct device * dev,gpio_port_pins_t pins)95 static int port_clear_bits(const struct device *dev,
96 gpio_port_pins_t pins)
97 {
98 return port_write(dev, pins, 0, 0);
99 }
100
port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)101 static int port_toggle_bits(const struct device *dev,
102 gpio_port_pins_t pins)
103 {
104 return port_write(dev, 0, 0, pins);
105 }
106
pin_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)107 static int pin_config(const struct device *dev,
108 gpio_pin_t pin,
109 gpio_flags_t flags)
110 {
111 const struct creg_gpio_config *cfg = dev->config;
112 uint32_t io_flags;
113 bool pin_is_output;
114
115 /* Check for invalid pin number */
116 if (pin >= cfg->ngpios) {
117 return -EINVAL;
118 }
119
120 /* Does not support disconnected pin, and
121 * not supporting both input/output at same time.
122 */
123 io_flags = flags & (GPIO_INPUT | GPIO_OUTPUT);
124 if ((io_flags == GPIO_DISCONNECTED)
125 || (io_flags == (GPIO_INPUT | GPIO_OUTPUT))) {
126 return -ENOTSUP;
127 }
128
129 /* No open-drain support */
130 if ((flags & GPIO_SINGLE_ENDED) != 0U) {
131 return -ENOTSUP;
132 }
133
134 /* Does not support pull-up/pull-down */
135 if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0U) {
136 return -ENOTSUP;
137 }
138
139 pin_is_output = (flags & GPIO_OUTPUT) != 0U;
140 if (pin_is_output) {
141 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
142 return port_set_bits(dev, BIT(pin));
143 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
144 return port_clear_bits(dev, BIT(pin));
145 }
146 }
147
148 return -ENOTSUP;
149 }
150
151 static const struct gpio_driver_api api_table = {
152 .pin_configure = pin_config,
153 .port_get_raw = port_get,
154 .port_set_masked_raw = port_set_masked,
155 .port_set_bits_raw = port_set_bits,
156 .port_clear_bits_raw = port_clear_bits,
157 .port_toggle_bits = port_toggle_bits,
158 };
159
160 static const struct creg_gpio_config creg_gpio_cfg = {
161 .common = {
162 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
163 },
164 .ngpios = DT_INST_PROP(0, ngpios),
165 .bit_per_gpio = DT_INST_PROP(0, bit_per_gpio),
166 .off_val = DT_INST_PROP(0, off_val),
167 .on_val = DT_INST_PROP(0, on_val),
168 };
169
170 static struct creg_gpio_drv_data creg_gpio_drvdata = {
171 .base_addr = DT_INST_REG_ADDR(0),
172 };
173
174 DEVICE_DT_INST_DEFINE(0, NULL, NULL, &creg_gpio_drvdata, &creg_gpio_cfg,
175 POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY,
176 &api_table);
177
