1 /*
2 * Copyright (c) 2019 Brett Witherspoon
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ti_cc13xx_cc26xx_gpio
8
9 #include <zephyr/types.h>
10 #include <zephyr/sys/__assert.h>
11 #include <zephyr/device.h>
12 #include <errno.h>
13 #include <zephyr/drivers/gpio.h>
14 #include <zephyr/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h>
15
16 #include <driverlib/gpio.h>
17 #include <driverlib/interrupt.h>
18 #include <driverlib/ioc.h>
19 #include <driverlib/prcm.h>
20
21 #include <inc/hw_aon_event.h>
22
23 #include <ti/drivers/Power.h>
24 #include <ti/drivers/power/PowerCC26XX.h>
25 #include <zephyr/irq.h>
26
27 #include <zephyr/drivers/gpio/gpio_utils.h>
28
29 /* bits 16-18 in iocfg registers correspond to interrupt settings */
30 #define IOCFG_INT_MASK 0x00070000
31
32 /* the rest are for general (non-interrupt) config */
33 #define IOCFG_GEN_MASK (~IOCFG_INT_MASK)
34
35 struct gpio_cc13xx_cc26xx_data {
36 /* gpio_driver_data needs to be first */
37 struct gpio_driver_data common;
38 sys_slist_t callbacks;
39 };
40
41 static struct gpio_cc13xx_cc26xx_data gpio_cc13xx_cc26xx_data_0;
42
43 static const struct gpio_driver_config gpio_cc13xx_cc26xx_cfg_0 = {
44 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
45 };
46
47 static int gpio_cc13xx_cc26xx_port_set_bits_raw(const struct device *port,
48 uint32_t mask);
49 static int gpio_cc13xx_cc26xx_port_clear_bits_raw(const struct device *port,
50 uint32_t mask);
51
gpio_cc13xx_cc26xx_config(const struct device * port,gpio_pin_t pin,gpio_flags_t flags)52 static int gpio_cc13xx_cc26xx_config(const struct device *port,
53 gpio_pin_t pin,
54 gpio_flags_t flags)
55 {
56 uint32_t config = 0;
57
58 __ASSERT_NO_MSG(pin < NUM_IO_MAX);
59
60 switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) {
61 case GPIO_INPUT:
62 config = IOC_INPUT_ENABLE;
63 break;
64 case GPIO_OUTPUT:
65 config = IOC_INPUT_DISABLE;
66 break;
67 case 0: /* disconnected */
68 IOCPortConfigureSet(pin, IOC_PORT_GPIO, IOC_NO_IOPULL);
69 GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_DISABLE);
70 return 0;
71 default:
72 return -ENOTSUP;
73 }
74
75 config |= IOC_SLEW_DISABLE | IOC_NO_WAKE_UP;
76
77 config |= (flags & CC13XX_CC26XX_GPIO_DEBOUNCE) ?
78 IOC_HYST_ENABLE : IOC_HYST_DISABLE;
79
80 switch (flags & CC13XX_CC26XX_GPIO_DS_MASK) {
81 case CC13XX_CC26XX_GPIO_DS_DFLT:
82 config |= IOC_CURRENT_2MA | IOC_STRENGTH_AUTO;
83 break;
84 case CC13XX_CC26XX_GPIO_DS_ALT:
85 /*
86 * Not all GPIO support 8ma, but setting that bit will use the
87 * highest supported drive strength.
88 */
89 config |= IOC_CURRENT_8MA | IOC_STRENGTH_MAX;
90 break;
91 default:
92 return -ENOTSUP;
93 }
94
95 switch (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
96 case 0:
97 config |= IOC_NO_IOPULL;
98 break;
99 case GPIO_PULL_UP:
100 config |= IOC_IOPULL_UP;
101 break;
102 case GPIO_PULL_DOWN:
103 config |= IOC_IOPULL_DOWN;
104 break;
105 default:
106 return -EINVAL;
107 }
108
109 config |= IOCPortConfigureGet(pin) & IOCFG_INT_MASK;
110 IOCPortConfigureSet(pin, IOC_PORT_GPIO, config);
111
112 if ((flags & GPIO_OUTPUT) != 0) {
113 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
114 gpio_cc13xx_cc26xx_port_set_bits_raw(port, BIT(pin));
115 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
116 gpio_cc13xx_cc26xx_port_clear_bits_raw(port, BIT(pin));
117 }
118 GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_ENABLE);
119 } else {
120 GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_DISABLE);
121 }
122
123 return 0;
124 }
125
gpio_cc13xx_cc26xx_port_get_raw(const struct device * port,uint32_t * value)126 static int gpio_cc13xx_cc26xx_port_get_raw(const struct device *port,
127 uint32_t *value)
128 {
129 __ASSERT_NO_MSG(value != NULL);
130
131 *value = GPIO_readMultiDio(GPIO_DIO_ALL_MASK);
132
133 return 0;
134 }
135
gpio_cc13xx_cc26xx_port_set_masked_raw(const struct device * port,uint32_t mask,uint32_t value)136 static int gpio_cc13xx_cc26xx_port_set_masked_raw(const struct device *port,
137 uint32_t mask,
138 uint32_t value)
139 {
140 GPIO_setMultiDio(mask & value);
141 GPIO_clearMultiDio(mask & ~value);
142
143 return 0;
144 }
145
gpio_cc13xx_cc26xx_port_set_bits_raw(const struct device * port,uint32_t mask)146 static int gpio_cc13xx_cc26xx_port_set_bits_raw(const struct device *port,
147 uint32_t mask)
148 {
149 GPIO_setMultiDio(mask);
150
151 return 0;
152 }
153
gpio_cc13xx_cc26xx_port_clear_bits_raw(const struct device * port,uint32_t mask)154 static int gpio_cc13xx_cc26xx_port_clear_bits_raw(const struct device *port,
155 uint32_t mask)
156 {
157 GPIO_clearMultiDio(mask);
158
159 return 0;
160 }
161
gpio_cc13xx_cc26xx_port_toggle_bits(const struct device * port,uint32_t mask)162 static int gpio_cc13xx_cc26xx_port_toggle_bits(const struct device *port,
163 uint32_t mask)
164 {
165 GPIO_toggleMultiDio(mask);
166
167 return 0;
168 }
169
gpio_cc13xx_cc26xx_pin_interrupt_configure(const struct device * port,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)170 static int gpio_cc13xx_cc26xx_pin_interrupt_configure(const struct device *port,
171 gpio_pin_t pin,
172 enum gpio_int_mode mode,
173 enum gpio_int_trig trig)
174 {
175 uint32_t config = 0;
176
177 if (mode != GPIO_INT_MODE_DISABLED) {
178 if (mode == GPIO_INT_MODE_EDGE) {
179 if (trig == GPIO_INT_TRIG_BOTH) {
180 config |= IOC_BOTH_EDGES;
181 } else if (trig == GPIO_INT_TRIG_HIGH) {
182 config |= IOC_RISING_EDGE;
183 } else { /* GPIO_INT_TRIG_LOW */
184 config |= IOC_FALLING_EDGE;
185 }
186 } else {
187 return -ENOTSUP;
188 }
189
190 config |= IOC_INT_ENABLE;
191 } else {
192 config |= IOC_INT_DISABLE | IOC_NO_EDGE;
193 }
194
195 config |= IOCPortConfigureGet(pin) & IOCFG_GEN_MASK;
196 IOCPortConfigureSet(pin, IOC_PORT_GPIO, config);
197
198 return 0;
199 }
200
gpio_cc13xx_cc26xx_manage_callback(const struct device * port,struct gpio_callback * callback,bool set)201 static int gpio_cc13xx_cc26xx_manage_callback(const struct device *port,
202 struct gpio_callback *callback,
203 bool set)
204 {
205 struct gpio_cc13xx_cc26xx_data *data = port->data;
206
207 return gpio_manage_callback(&data->callbacks, callback, set);
208 }
209
gpio_cc13xx_cc26xx_get_pending_int(const struct device * dev)210 static uint32_t gpio_cc13xx_cc26xx_get_pending_int(const struct device *dev)
211 {
212 return GPIO_getEventMultiDio(GPIO_DIO_ALL_MASK);
213 }
214
gpio_cc13xx_cc26xx_isr(const struct device * dev)215 static void gpio_cc13xx_cc26xx_isr(const struct device *dev)
216 {
217 struct gpio_cc13xx_cc26xx_data *data = dev->data;
218
219 uint32_t status = GPIO_getEventMultiDio(GPIO_DIO_ALL_MASK);
220
221 GPIO_clearEventMultiDio(status);
222
223 gpio_fire_callbacks(&data->callbacks, dev, status);
224 }
225
gpio_cc13xx_cc26xx_init(const struct device * dev)226 static int gpio_cc13xx_cc26xx_init(const struct device *dev)
227 {
228 #ifdef CONFIG_PM
229 /* Set dependency on gpio resource to turn on power domains */
230 Power_setDependency(PowerCC26XX_PERIPH_GPIO);
231 #else
232 /* Enable peripheral power domain */
233 PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
234
235 /* Enable GPIO peripheral */
236 PRCMPeripheralRunEnable(PRCM_PERIPH_GPIO);
237
238 /* Load PRCM settings */
239 PRCMLoadSet();
240 while (!PRCMLoadGet()) {
241 continue;
242 }
243 #endif
244
245 /* Enable edge detection on any pad as a wakeup source */
246 HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) =
247 (HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) &
248 (~AON_EVENT_MCUWUSEL_WU1_EV_M)) |
249 AON_EVENT_MCUWUSEL_WU1_EV_PAD;
250
251 /* Enable IRQ */
252 IRQ_CONNECT(DT_INST_IRQN(0),
253 DT_INST_IRQ(0, priority),
254 gpio_cc13xx_cc26xx_isr, DEVICE_DT_INST_GET(0), 0);
255 irq_enable(DT_INST_IRQN(0));
256
257 /* Peripheral should not be accessed until power domain is on. */
258 while (PRCMPowerDomainsAllOn(PRCM_DOMAIN_PERIPH) !=
259 PRCM_DOMAIN_POWER_ON) {
260 continue;
261 }
262
263 return 0;
264 }
265
266 #ifdef CONFIG_GPIO_GET_DIRECTION
gpio_cc13xx_cc26xx_port_get_direction(const struct device * port,gpio_port_pins_t map,gpio_port_pins_t * inputs,gpio_port_pins_t * outputs)267 static int gpio_cc13xx_cc26xx_port_get_direction(const struct device *port, gpio_port_pins_t map,
268 gpio_port_pins_t *inputs,
269 gpio_port_pins_t *outputs)
270 {
271 uint32_t pin;
272 gpio_port_pins_t ip = 0;
273 gpio_port_pins_t op = 0;
274 const struct gpio_driver_config *cfg = port->config;
275
276 map &= cfg->port_pin_mask;
277
278 if (inputs != NULL) {
279 for (pin = find_lsb_set(map) - 1; map;
280 map &= ~BIT(pin), pin = find_lsb_set(map) - 1) {
281 ip |= !!(IOCPortConfigureGet(pin) & IOC_INPUT_ENABLE) * BIT(pin);
282 }
283
284 *inputs = ip;
285 }
286
287 if (outputs != NULL) {
288 for (pin = find_lsb_set(map) - 1; map;
289 map &= ~BIT(pin), pin = find_lsb_set(map) - 1) {
290 op |= GPIO_getOutputEnableDio(pin) * BIT(pin);
291 }
292
293 *outputs = op;
294 }
295
296 return 0;
297 }
298 #endif /* CONFIG_GPIO_GET_DIRECTION */
299
300 static const struct gpio_driver_api gpio_cc13xx_cc26xx_driver_api = {
301 .pin_configure = gpio_cc13xx_cc26xx_config,
302 .port_get_raw = gpio_cc13xx_cc26xx_port_get_raw,
303 .port_set_masked_raw = gpio_cc13xx_cc26xx_port_set_masked_raw,
304 .port_set_bits_raw = gpio_cc13xx_cc26xx_port_set_bits_raw,
305 .port_clear_bits_raw = gpio_cc13xx_cc26xx_port_clear_bits_raw,
306 .port_toggle_bits = gpio_cc13xx_cc26xx_port_toggle_bits,
307 .pin_interrupt_configure = gpio_cc13xx_cc26xx_pin_interrupt_configure,
308 .manage_callback = gpio_cc13xx_cc26xx_manage_callback,
309 .get_pending_int = gpio_cc13xx_cc26xx_get_pending_int,
310 #ifdef CONFIG_GPIO_GET_DIRECTION
311 .port_get_direction = gpio_cc13xx_cc26xx_port_get_direction,
312 #endif /* CONFIG_GPIO_GET_DIRECTION */
313 };
314
315 DEVICE_DT_INST_DEFINE(0, gpio_cc13xx_cc26xx_init,
316 NULL, &gpio_cc13xx_cc26xx_data_0,
317 &gpio_cc13xx_cc26xx_cfg_0,
318 PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
319 &gpio_cc13xx_cc26xx_driver_api);
320
